KR101726396B1 - CML driver and method for adjusting pre-emphasis ratio between high level and low level - Google Patents

CML driver and method for adjusting pre-emphasis ratio between high level and low level Download PDF

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Publication number
KR101726396B1
KR101726396B1 KR1020150180922A KR20150180922A KR101726396B1 KR 101726396 B1 KR101726396 B1 KR 101726396B1 KR 1020150180922 A KR1020150180922 A KR 1020150180922A KR 20150180922 A KR20150180922 A KR 20150180922A KR 101726396 B1 KR101726396 B1 KR 101726396B1
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South Korea
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driver
mos transistor
emphasis
signal
current source
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KR1020150180922A
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Korean (ko)
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민병훈
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(주) 엠칩스
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching

Abstract

A current mode logic driver and method for adjusting the vertical ratio of pre-emphasis is disclosed. The CML driver includes: a main driver for receiving a serial input signal and outputting an output signal; a first sub driver for adjusting a pre-emphasis ratio at a high level of an output signal; And a second sub driver for adjusting the pre-emphasis ratio of the pre-emphasis output signal of the main driver by the first sub driver and the second sub driver to the same level do.

Figure R1020150180922

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mode logic driver for adjusting the up / down ratio of pre-emphasis,

The present invention relates to a current mode logic driver.

1A is a circuit diagram of a current mode logic (CML) driver having a general pre-emphasis function.

Referring to FIG. 1A, a general CML driver 1 is a circuit module used in a final stage when transmitting data using a wire. The CML driver 1 is composed of a main driver 10 and a preemphasis driver 12. The main driver 10 is composed of MOS transistors M 1 and M 2 , resistors R 1 and R 2 and a current source I ss1 . The main driver 10 receives the serialized differential input signals V IN1 and V IN2 and generates a differential output signal V out1 , And V out2 . Pre-emphasis driver 12 is composed of a MOS transistor M 3, M 4, and a current source I ss2, and adjusts the ratio (ratio) of the pre-emphasis at by varying the current source I ss2 output signal V out1, V out2.

1B is a circuit diagram of a logic circuit portion for providing input data to a general CML driver.

Referring to FIGS. 1A and 1B, the logic circuitry 14 provides input data to the CML driver 1. The logic circuit section 14 includes a data serializer 140 and a 1-tap delay section 142. The data serializer 140 receives the parallel data and the clock signal CLK and serializes the parallel data. The serialized data are input to the main driver 10 of the CML driver 1 as input signals V IN1 and V IN2 . On the other hand, a 1-tap delay unit 142 is used to provide the pre-emphasis circuit unit 12 with input signals V pre1 and V pre2 for pre-emphasis. The 1-tap delay unit 142 is a circuit for delaying the serialized data V IN1 and V IN2 by 1-bit, and the timing chart thereof will be described later with reference to FIG.

2 is a timing diagram showing a pre-emphasis function of a general CML driver.

2, the delay signals V PRE1 230 and V PRE2 240 are the results of delaying the input signals V IN1 210 and V IN2 220 by 1-bit, respectively, and the delay signals V PRE1 230 And V PRE2 240 are provided to the CML driver, the output of the CML driver is the same as the pre-emphasized output signals V out1 250 and V out2 260 of FIG.

In a general CML driver, a pre-emphasis driver is designed to balance the amount of pre-emphasis at a high level and the amount of pre-emphasis at a low level, And the amount of pre-emphasis at the low level is different. For example, the amount of pre-emphasis at a high level and the amount of pre-emphasis at a low level may vary due to process variations, temperature changes, power supply voltage variations, and non-ideal characteristics of the MOS transistors have. FIG. 3 shows such a problem.

3 (a) is a timing chart of the output signal when the pre-emphasis ratio between the high level and the low level is the same, and FIG. 3 (b) shows the pre-emphasis ratio at the high level 3C is a timing chart of the output signal when the pre-emphasis ratio at the low level is higher than the pre-emphasis ratio at the high level. .

Referring to FIG. 3A, it is shown that the amount of pre-emphasis at the high level of the output signal V out1 is equal to the amount of pre-emphasis at the low level. On the other hand, the waveform of the actual output signal V out1 is outputted as shown in FIG. 3 (b) or FIG. 3 (c) depending on the process change, the temperature change, the change in the power supply voltage and the non-ideal characteristics of the MOS transistor.

3 (b) shows a case where the amount of pre-emphasis at the high level is greater than the amount of pre-emphasis at the low level, and FIG. 3 (c) shows the case where the amount of pre- Is greater than the amount of pre-emphasis of. When a waveform as shown in Figs. 3 (b) and 3 (c) is outputted, it is difficult to find a method of correcting it in the CML driver. This is because the MOS transistors M 3 and M 4 and the variable current source I ss2 constituting the pre-emphasis driver are involved in both the pre-emphasis at the high level and the pre-emphasis at the low level.

According to one embodiment, a CML driver and method are provided for adjusting the amount of pre-emphasis at a high level and the amount of pre-emphasis at a low level to be equal to each other.

A CML driver according to an embodiment includes a main driver for receiving a serial input signal and outputting an output signal, a first sub driver for adjusting a pre-emphasis ratio at a high level of an output signal, And a second sub driver for separately adjusting a pre-emphasis ratio at a low level of the output signal, wherein the first sub driver and the second sub driver are used for pre-emphasizing the pre-emphasis output signal of the main driver The ratio is adjusted to be the same.

The main driver according to an embodiment includes a first MOS transistor having a gate terminal connected to a second input signal, a source terminal connected to a first variable current source and a drain terminal connected to a second output node, A second MOS transistor having a source terminal connected to the first variable current source and a drain terminal connected to the first output node, and a second MOS transistor formed between the source terminal of the first MOS transistor and the second MOS transistor and the ground voltage A first resistor formed between the power supply voltage and the second output node; a second resistor formed between the power supply voltage and the first output node; a first output node for outputting a first output signal; And a second output node for outputting a second output signal.

The first sub driver according to an embodiment includes a third MOS transistor having a gate terminal connected to a second input signal, a source terminal connected to a seventh MOS transistor, and a drain terminal connected to a first output node of the main driver, A fourth MOS transistor to which a first input signal is applied to a gate terminal, a seventh MOS transistor is connected to a source terminal, and a second output node of the main driver is connected to a drain terminal, and a fourth MOS transistor having a first logic operation signal A seventh MOS transistor whose source terminal is connected to the second variable current source and whose drain terminal is connected to the source terminal of the third MOS transistor and the fourth MOS transistor and a second variable current source formed between the seventh MOS transistor and the ground voltage .

The first logic operation signal applied to the seventh MOS transistor is an exclusive NOR logic gate circuit in which the first input signal and the first delay signal delaying the first input signal are subjected to an exclusive-NOR operation Or an exclusive-NOR logic gate circuit may output a second input signal and an output signal obtained by performing an exclusive-NOR operation on a second delay signal delayed by the second input signal.

The second sub-driver may include a fifth MOS transistor having a gate terminal connected to a first input signal, a source terminal connected to an eighth MOS transistor, and a drain terminal connected to a first output node of the main driver, A sixth MOS transistor having a gate terminal connected to a second input signal, a source terminal connected to an eighth MOS transistor and a drain terminal connected to a second output node of the main driver, An eighth MOS transistor whose source terminal is connected to the third variable current source and whose drain terminal is connected to the source terminal of the fifth MOS transistor and the sixth MOS transistor, and a third variable current source formed between the eighth MOS transistor and the ground voltage .

The second logic operation signal applied to the eighth MOS transistor is obtained by an exclusive-OR operation of the first input signal and the first delay signal delaying the first input signal by the exclusive-OR logic gate circuit Or an exclusive-OR logic gate circuit may output a second input signal and an output signal obtained by performing an exclusive-OR operation on the second delay signal delayed by the second input signal.

The method of adjusting a pre-emphasis ratio of a CML driver according to another embodiment includes the steps of initializing a first variable current source of a main driver, a second variable current source of a first sub driver, and a third variable current source of a second sub driver, The first variable current source of the main driver is adjusted so that the pre-emphasized high-level voltage and the pre-emphasized low-level voltage of the output signal of the main driver become V D and V B Adjusting a second variable current source of the first sub driver to set a high pre-emphasis voltage of the output signal of the main driver to reach a V C value desired by the user; Adjusting the third variable current source of the second sub driver to set the pre-emphasized low level voltage of the output signal of the main driver to reach the value of V A desired by the user.

Pre-emphasis and down scaling method in accordance with one embodiment, the pre-em-free in-emphasis the high-level voltage V D value and a low level voltage V B minus the high level voltage V C from the emphasis of the low level voltage V A and a step of subtracting the check values are the same, (V D -V C) < (V B -V a) is the third variable current source of the first to the second increase in the variable current source of sub-drivers, and a second sub-driver Thereby adjusting the vertical ratio of the pre-emphasis.

Pre-emphasis and down scaling method in accordance with one embodiment, the pre-em-free in-emphasis the high-level voltage V D value and a low level voltage V B minus the high level voltage V C from the emphasis of the low level voltage V A the method comprising the values are the same check subtracting, (V D -V C)> (V B -V a) is the third variable current source of the first driver of the first sub second variable current source or to reduce the second sub-driver To thereby adjust the vertical ratio of the pre-emphasis.

According to one embodiment, the up / down ratio of the pre-emphasized output signal of the CML driver can be simply matched. That is, by separating the sub driver for adjusting the pre-emphasis at the high level and the sub driver for adjusting the pre-emphasis at the low level, Even when the pre-emphasized output signals have different vertical ratios, the CML driver itself can easily adjust the ratios to be the same. In particular, the upper and lower ratios of the pre-emphasis can be adjusted to be the same amount of pre-emphasis by adjusting the variable current sources of the respective sub-drivers.

1A is a circuit diagram of a CML driver having a general pre-emphasis function,
1B is a circuit diagram of a logic circuit portion for providing input data to a general CML driver,
2 is a timing diagram showing a pre-emphasis function of a general CML driver,
3 is a timing chart of output signals when the pre-emphasis rates are the same or different,
FIG. 4 illustrates a configuration of a logic circuit section for providing an input signal to a CML driver according to an embodiment of the present invention;
FIG. 5A is a timing chart of input / output of a logic circuit according to an embodiment of the present invention, FIG. 5B is a circuit diagram of a logic circuit according to an embodiment of the present invention,
6 is a circuit diagram of a CML driver for adjusting the ratio of the pre-emphasis vertical ratio according to the embodiment of the present invention,
7 is a signal timing diagram for explaining the pre-emphasis operation of the output signal V out1 of the CML driver according to the embodiment of the present invention,
FIG. 8 is a flowchart illustrating a method of adjusting a vertical ratio of pre-emphasis according to an embodiment of the present invention;
9 is a timing diagram of output signals in steps 820, 830, and 840 in the flowchart of FIG. 8 according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, which may vary depending on the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

4 is a block diagram of a logic circuit for providing an input signal to a CML driver according to an embodiment of the present invention.

The logic circuit unit 40 according to an embodiment includes a data serializer 410, a 1-tap delay unit 420, and a pre-emphasis logic circuit unit 430.

The data serializer 410 and the 1-tap delay unit 420 of FIG. 4 may be the data serializer 140 and the 1-tap delay unit 142 described above with reference to FIG. 1B. In order to facilitate understanding of the present invention, a 1-tap delay unit 420 for delaying a signal by 1 bit will be described as an example, but the present invention is not limited to a 1-tap delay.

The pre-emphasis logic circuit unit 430 receives the differential output signals V IN1 and V IN2 of the data serializer 410 and the differential output signals V PRE1 and V PRE2 of the 1-tap delay unit 420, V UP -PRE and V DN -PRE . The output waveforms of the logic operation signals V UP -PRE and V DN -PRE will be described later with reference to FIG. 5A, and the structure thereof will be described later with reference to FIG. 5B.

5A is a timing chart of input and output of a logic circuit according to an embodiment of the present invention, and FIG. 5B is a circuit diagram of a logic circuit according to an embodiment of the present invention.

5A and 5B, an exclusive-NOR logic gate circuit 570 performs an exclusive-NOR operation on the first input signal V IN1 510 and the first delay signal V PRE1 530, And output the first logical operation signal V UP -PRE (550). Or an exclusive-NOR logic gate circuit 570 performs an exclusive-OR operation on the second input signal V IN2 520 and the second delay signal V PRE2 540 to generate the first logical operation signal V UP-PRE ( 550).

The exclusive-OR logic gate circuit 580 performs an exclusive OR operation of the first input signal V IN1 510 and the first delay signal V PRE1 530 to generate the second logical operation signal V DN -PRE 560 Can be output. Or an exclusive-OR logic gate circuit 580 performs an exclusive OR operation on the second input signal V IN2 520 and the second delay signal V PRE2 540 to generate the second logical operation signal V DN-PRE ( 560).

FIG. 6 is a circuit diagram of a CML driver for adjusting the vertical ratio of pre-emphasis according to an embodiment of the present invention.

6, the CML driver 6 includes a main driver 61, a first sub driver 62 for high level preemphasis, and a second sub driver 63 for low level preemphasis .

The main driver 61 includes a first variable current source I ss1 610, a first MOS transistor M 1 611, a second MOS transistor M 2 612, a first resistor R 1 613 and a second resistor R 2 And receives the serial differential input signals V IN1 and V IN2 and outputs the differential output signals V out1 and V out2 .

Specifically, the first MOS transistor M1 (611) has a second input signal V IN2 applied to its gate terminal, a second output node 616 connected to its drain terminal, and a first variable current source I SS1 610 ). The second MOS transistor M2 612 has a gate terminal connected to the first input signal V IN1 , a drain terminal connected to the first output node 615, and a source connected to the first variable current source I SS1 610 do. The first variable current source I SS1 610 is formed between the source terminal of the first MOS transistor M1 611 and the second MOS transistor M2 612 and the ground voltage VSS. The first resistor R1 613 is connected to the power supply voltage VDD 617 and the second output node 616 and the second resistor R2 614 is connected to the power supply voltage VDD 617 and the first output node 616. [ 615). The first output node 615 outputs the first output signal V out1 , and the second output node 615 outputs the second output signal V out2 . The first input signal V IN1 and the second input signal V IN2 are serialized differential signals. The first output signal V out1 and the second output signal V out2 are differential signals.

The first sub driver 62 for high level pre-emphasis is connected to the third MOS transistor M 3 623, the fourth MOS transistor M 4 624, the seventh MOS transistor M 7 627, I ss2 (620).

Specifically, the third MOS transistor M 3 623 has a gate terminal connected to the second input signal V IN2 , a source terminal connected to the seventh MOS transistor M 7 627, and a drain terminal connected to the drain terminal of the main driver 61 1 output node 615 are connected. The fourth MOS transistor M 4 624 has a gate terminal connected to the first input signal V IN1 , a source terminal connected to the seventh MOS transistor M 7 627 and a drain terminal connected to the second output node (Not shown). A seventh MOS transistor M 7 (627) is applied to the first logic operation signal V UP -PRE to the gate terminal and the second variable current source is I ss2 (620) is connected to the source terminal of the third MOS transistor M3 (623 to the drain terminal And the source terminal of the fourth MOS transistor M4 624 are connected. A second variable current source I ss2 (620) is formed between a seventh MOS transistor M 7 (627) and ground (VSS). The pre-emphasis operation characteristic in the above-described configuration can be observed in the period B and the period D in which the output signal V out1 of FIG. 7 is maintained at the high level state for 2-bit or more.

The second sub-driver 63 for low-level pre-emphasis is connected to the fifth MOS transistor M 5 635, the sixth MOS transistor M 6 636, the eighth MOS transistor M 8 638, I ss3 630.

Specifically, the fifth MOS transistor M 5 (635) a first input signal applied to the V IN1 and eighth MOS transistor to the source terminal M 8 (638) are connected, and a main driver 61, the drain terminal to the gate terminal 1 output node 615 are connected. A sixth MOS transistor M 6 (636) the second output of the second input signal V IN2 is applied and an eighth MOS transistor M 8 (638) are connected, and a main driver 61, the drain terminal to the source terminal to a gate terminal node, (Not shown). An eighth MOS transistor M 8 (638) is a second logic operation signal V DN is applied to the -PRE and the third variable current source I ss3 (630) is connected to the source terminal to the gate terminal of the fifth MOS transistor M5 (635 to the drain terminal And the source terminal of the sixth MOS transistor M6 636 are connected. The third variable current source I ss3 (630) is formed between the eighth MOS transistor M 8 (638) and ground (VSS). The pre-emphasis operation characteristic in the above-described configuration can be observed in an interval A in which the output signal V out1 of FIG. 7 is maintained at a low level state for 2-bit or more.

7 is a signal timing chart for explaining the pre-emphasis operation of the output signal V out1 of the CML driver according to the embodiment of the present invention.

First, the V A from the first output signal V out1 waveform of Figure 7 is pre-emphasis of the low level voltage, V B is a low level voltage, V C is the high level voltage, V D are each the pre-emphasis of the high level voltage define. Although the first output signal V out1 is described as an example for ease of explanation in FIG. 7, the second output signal V out2 , which is a differential signal from the first output signal, can also be described on the same principle.

6 and 7, the MOS transistors connected to the operation of the first output signal V out1 are first the second MOS transistor M 2 612 of the main driver 61, and the second sub driver a fifth MOS transistor M 5 (635) and the eighth MOS transistor M 8 (638), and a third MOS transistor of the third first sub-driver (62) M 3 (623) and a seventh MOS transistor M 63) 7 (627).

7 shows the current state of the first output signal V out1 . When the first input signal V IN1 applied to the gate terminal of the second MOS transistor M 2 612 of the main driver 61 is high Level, the first input signal V IN1 and the second logical operation signal V DN (n) applied to the gate terminals of the fifth MOS transistor M 5 635 and the eighth MOS transistor M 8 638 of the second sub- -PRE is included in the segment bit map, and the segment bit map is indicated by {V IN1 , V IN1 , V DN -PRE }. Since the first input signal V IN1 is at the high level, the bit map for each section becomes {1,1, V DN-PRE }.

If the first input signal V IN1 applied to the gate terminal of the second MOS transistor M 2 612 of the main driver 61 is low level, the third MOS transistor M 3 623 of the first sub driver 62, The second input signal V IN2 and the first logic operation signal V UP -PRE applied to the gate terminal of the seventh MOS transistor M 7 627 are included in the bit map for each section to generate {V IN1 , V IN2 , V UP -PRE } indicates the bitmap according to the segment. When the first input signal V IN1 is at the low level, the second input signal V IN2 is at the high level, so that the bit map per section becomes {0, 1, V UP-PRE }.

When the bit map for each section is {1, 1, 1}, the first output signal V out1 has a pre-emphasized low level voltage V A. When the bit map for each section is {1, 1, 0} Level voltage V B , and when the bit map for each section is {0,1,0}, it has the high-level voltage V D pre-emphasized. If the bit map for each section is {0,1,1} A high level voltage V C is obtained.

7 shows a process of transition from the pre-emphasis low level (V A ) to the low level (V B ) through the above-described bit map for each section, and the section B and the section D are pre- (V D ) to a high level (V C ). The section C is switched from a pre-emphasized high level (V D ) to a pre-emphasized low level (V A ) or from a pre-emphasized low level (V A ) to a pre-emphasis high level (V D ) Show the process of transition.

FIG. 8 is a flowchart illustrating a method of adjusting a vertical ratio of pre-emphasis according to an embodiment of the present invention.

6 and 8, the CML driver 6 includes a first variable current source I ss1 610 of the main driver 61, a second variable current source I ss2 620 of the first sub driver 62, All of the third variable current sources I ss3 630 of the two sub-drivers 63 are initialized to '0' (810).

Subsequently, the CML driver 6 adjusts the first variable current source I ss1 610 of the main driver 61, for example, by increasing the current of the first variable current source I ss1 610, The pre-emphasized high-level voltage and the pre-emphasized low-level voltage of the first output signal Vout1 and the second output signal Vout2 are respectively supplied to the V D and V B (820).

The CML driver 6 then adjusts the second variable current source I ss2 620 of the first sub driver 62, for example by increasing the current of the second variable current source I ss2 620 to generate the first output signal V and the second output signal V out1 and the pre-emphasis of the M high-level voltage is not out2 set up to reach the desired value V C 830.

The CML driver 6 then adjusts the third variable current source I ss3 630 of the second sub driver 63, for example by increasing the current of the third variable current source I ss3 630 to generate the first output signal V and a pre-emphasis of the low-level voltage signal V out1 and the second output out2 set up to reach the desired value of V a (840).

Then, the CML driver 6 checks whether the pre-emphasis ratio is the same, and adjusts the vertical ratio of the pre-emphasis to be the same if not identical (850). That is, it is confirmed that (V D -V C ) = (V B -V A ). If it is determined that (V D -V C ) <(V B -V A ), the second variable current source I ss2 620 of the first sub driver 62 is increased or the third variable current source I ss2 620 of the second sub driver 63 Thereby reducing the variable current source I ss3 630. [ If it is determined that (V D -V C )> (V B -V A ), the second variable current source I ss2 620 of the first sub driver 62 is decreased or the third variable current source I ss2 620 of the second sub driver 63 By increasing the variable current source I ss3 630, the vertical ratio of the pre-emphasis is adjusted.

In the above-described process, if step 830 is set to step 840 and step 840 is advanced to step 830, the same result is obtained, and the up-down ratio of the pre-emphasis can be adjusted.

9 is a timing diagram of output signals in steps 820, 830, and 840 in the flowchart of FIG. 8 according to an embodiment of the present invention.

Referring to Figures 8 and 9A, in step 820, the first output signal V out1 swings V D to a high level voltage and V B to a low level voltage. 8 and 9 (b), in step 830, the first output signal V out1 transitions from the pre-emphasized high level voltage V D to the high level voltage V C. Referring to FIGS. 8 and 9C, in step 840, the first output signal V out1 transitions from the pre-emphasized low level voltage V A to the low level voltage V B.

The embodiments of the present invention have been described above. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

6: CML driver 40: logic circuit section
61: main driver 62: first sub driver
63: second sub-driver 410: data serializer
420: 1-tap delay unit 430: Pre-emphasis logic circuit unit

Claims (9)

A main driver for receiving a serialized input signal and outputting an output signal;
A first sub driver for adjusting a pre-emphasis ratio at a high level of the output signal; And
A second sub driver which is separate from the first sub driver and adjusts a pre-emphasis ratio at a low level of the output signal; / RTI &gt;
By adjusting a variable current source of a first sub driver for obtaining a high level pre-emphasis characteristic and a second current driver for obtaining a low pre-emphasis characteristic, a pre-emphasis output signal of the main driver is pre- And the up / down ratio of the emphasis is adjusted to be the same. The apparatus of claim 1, wherein the main driver
A first MOS transistor in which a second input signal is applied to a gate terminal, a first variable current source is connected to a source terminal, and a second output node is connected to a drain terminal;
A second MOS transistor having a gate terminal connected to a first input signal, a source terminal connected to a first variable current source, and a drain terminal connected to a first output node;
A first variable current source formed between the source terminal of the first MOS transistor and the second MOS transistor and the ground voltage;
A first resistor formed between the power supply voltage and the second output node;
A second resistor formed between the power supply voltage and the first output node;
A first output node for outputting a first output signal; And
A second output node for outputting a second output signal;
The current mode logic driver. The apparatus of claim 1, wherein the first sub driver
A third MOS transistor having a gate terminal connected to a second input signal, a source terminal connected to a seventh MOS transistor, and a drain terminal connected to a first output node of the main driver;
A fourth MOS transistor having a gate terminal connected to a first input signal, a source terminal connected to a seventh MOS transistor, and a drain terminal connected to a second output node of the main driver;
A seventh MOS transistor in which a first logic operation signal is applied to a gate terminal, a second variable current source is connected to a source terminal, and a source terminal of the third MOS transistor and a fourth MOS transistor are connected to a drain terminal; And
A second variable current source formed between the seventh MOS transistor and the ground voltage;
The current mode logic driver. 4. The semiconductor memory device according to claim 3, wherein the first logic operation signal applied to the seventh MOS transistor comprises:
An exclusive NOR logic gate circuit is a signal obtained by performing an exclusive-NOR operation on a first input signal and a first delay signal delaying a first input signal,
Wherein the exclusive NOR logic gate circuit is a signal obtained by performing an exclusive-NOR operation on a second input signal and a second delay signal delayed by a second input signal. The apparatus as claimed in claim 1, wherein the second sub driver
A fifth MOS transistor in which a first input signal is applied to a gate terminal, an eighth MOS transistor is connected to a source terminal, and a first output node of the main driver is connected to a drain terminal;
A sixth MOS transistor in which a second input signal is applied to a gate terminal, an eighth MOS transistor is connected to a source terminal, and a second output node of the main driver is connected to a drain terminal;
An eighth MOS transistor in which a second logic operation signal is applied to a gate terminal, a third variable current source is connected to a source terminal, and a source terminal of the fifth MOS transistor and a sixth MOS transistor are connected to a drain terminal; And
A third variable current source formed between the eighth MOS transistor and the ground voltage;
The current mode logic driver. 6. The semiconductor memory device according to claim 5, wherein the second logic operation signal applied to the eighth MOS transistor
The exclusive-OR logic gate circuit is a signal obtained by performing an exclusive OR operation on the first input signal and the first delay signal delaying the first input signal,
Wherein the exclusive-OR logic gate circuit is a signal obtained by performing an exclusive-OR operation on a second input signal and a second delay signal delaying a second input signal. In the method of adjusting the pre-emphasis vertical ratio of the current mode logic driver,
Initializing a first variable current source of the main driver, a second variable current source of the first sub driver, and a third variable current source of the second sub driver;
Adjusting the first variable current source of the main driver so as to set the pre-emphasized high level voltage and the pre-emphasized low level voltage of the output signal of the main driver respectively to the values V D and V B desired by the user;
Adjusting a second variable current source of the first sub driver to set a high pre-emphasis voltage of the output signal of the main driver to reach a desired V C value by the user; And
Adjusting a third variable current source of the second sub driver to set the pre-emphasized low level voltage of the output signal of the main driver to reach a value of V A desired by the user;
And adjusting the pre-emphasis vertical ratio. 8. The method of claim 7, wherein the pre-
Pre-emphasis the high-level voltage value, the method comprising net of the high level voltage V C and V D at the low level voltage pre-M, less emphasis of the low level voltage V A from the value V B are the same check; And
(V D -V C ) < (V B -V A ), the second variable current source of the first sub-driver is increased or the third variable current source of the second sub-driver is decreased to adjust the vertical ratio of the pre- step;
Further comprising the step of adjusting the pre-emphasis vertical ratio. 8. The method of claim 7, wherein the pre-
Pre-emphasis the high-level voltage value, the method comprising net of the high level voltage V C and V D at the low level voltage pre-M, less emphasis of the low level voltage V A from the value V B are the same check; And
(V D -V C ) > (V B -V A ), the second variable current source of the first sub driver is decreased or the third variable current source of the second sub driver is increased to adjust the vertical ratio of the pre- step;
Further comprising the step of adjusting the pre-emphasis vertical ratio.
KR1020150180922A 2015-12-17 2015-12-17 CML driver and method for adjusting pre-emphasis ratio between high level and low level KR101726396B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110719047A (en) * 2019-10-24 2020-01-21 杭州雄迈集成电路技术有限公司 Novel low-power consumption MIPI current mode drive
US11552656B2 (en) 2020-08-10 2023-01-10 Magnachip Semiconductor, Ltd. Current mode logic driver and transmission driver including the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090017086A (en) * 2007-08-14 2009-02-18 주식회사 하이닉스반도체 Circuit for controlling pre-emphasis of semiconductor memory apparatus
KR20140084399A (en) * 2012-12-26 2014-07-07 에스케이하이닉스 주식회사 de-emphasis buffer circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090017086A (en) * 2007-08-14 2009-02-18 주식회사 하이닉스반도체 Circuit for controlling pre-emphasis of semiconductor memory apparatus
KR20140084399A (en) * 2012-12-26 2014-07-07 에스케이하이닉스 주식회사 de-emphasis buffer circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110719047A (en) * 2019-10-24 2020-01-21 杭州雄迈集成电路技术有限公司 Novel low-power consumption MIPI current mode drive
US11552656B2 (en) 2020-08-10 2023-01-10 Magnachip Semiconductor, Ltd. Current mode logic driver and transmission driver including the same

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