KR101725127B1 - ARIA encoding/decoding apparatus and method - Google Patents

Abstract

The present invention relates to a block cipher ARIA encryption / decryption apparatus, which comprises: a data input unit for dividing and storing input plain text data; A counter generating unit for generating a predetermined counter value; An ARI round operator for performing an encryption operation on the input data with respect to a predetermined counter value according to an ARIA algorithm; And an ary key generation unit for generating a round key used in each round of the aria round operation unit. According to the present invention, in performing the message authentication and the encryption at the same time, the aria encryption device can reduce the hardware size by using one aria encryption module. Also, it is possible to increase the operation speed of the message authentication and encryption using the block cipher ARIA by providing a calculation method of performing the encryption on the counter before the plaintext data is input. Also, it reduces the computation delay time that can occur when the message authentication code is generated by using the Aria round operation unit using the pipeline register.

Description

 {ARIA encoding / decoding apparatus and method}

 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block cipher ARIA encryption / decryption apparatus, and more particularly, to a high speed cipher encryption / decryption apparatus for performing message authentication and encryption at the same time.

 The aria encryption decryption algorithm is a public-private key block symmetric key encryption algorithm developed by National Institute of Security Technology (NSRI).

The rounding number and the key size of the aria algorithm are recommended to use 12 rounds when the master key is 128 bits, 14 rounds when the master key is 192 bits, and 16 rounds when the master key is 256 bits.

The Aria algorithm performs an encryption / decryption operation by round operation, and each round operation is performed by a substitution operation (diffusion) and a diffusion operation (diffusion operation).

The key expansion process in the aria algorithm is a key initialization process for generating four 128-bit initial key values W0, W1, W2, and W3 when the master key (MK) and specific initialization constants (CK1, CK2, CK3) Round key generation process.

There is a difference between the time required for the aria encryption decryption operation and the hardware resources used according to the method of performing the replacement operation and the diffusion operation and the method of performing the key expansion process, It becomes a problem.

When message authentication is performed using conventional block encryption, a MAC (message authentication code) is generated. This is accomplished by using a block cipher algorithm to perform a ciphertext operation on the exclusive OR of the ciphertext and the current plaintext of the previous block. On the other hand, various methods of operation such as ECB (Electronic Code Book), CBC (Cipher Block Chaining) and CTR (Counter) exist in the message encryption method using the block cipher. Here, among the block cipher operating modes that simultaneously perform message authentication and encryption using a block cipher, the CCM mode includes a CBC-MAC mode for message authentication and a CTR mode for message encryption.

There is a problem that the hardware size is increased due to the separately provided aria cryptographic operation module for operating the CBC-MAC and the ariya cryptographic operation module for operating the CTR mode in constructing the aria cryptosystem for performing the conventional CCM mode there was.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems of the prior art, and it is an object of the present invention to provide a method of reducing hardware size by using a single encryption module in simultaneously performing message authentication and encryption using a block cipher architecture .

It is another object of the present invention to provide a method of performing encryption before a plaintext data is input, and to provide a method for increasing the speed of operation of message authentication and encryption using a block cipher.

According to an aspect of the present invention, there is provided an apparatus for decoding an aria coded data, comprising: a data input unit for dividing and storing input plain text data; A counter generating unit for generating a predetermined counter value; An ARI round operator for performing an encryption operation on the input data with respect to a predetermined counter value according to an ARIA algorithm; And an ary key generation unit for generating a round key used in each round of the aria round operation unit.

The encryption / decryption apparatus further includes a data output unit for outputting a result of the aria round operation unit.

The encryption / decryption apparatus includes a control unit for setting a limit value of the counter value and controlling the encryption / decryption unit to perform the encryption operation on the counter value corresponding to the limit value.

The control unit may include a counter encrypting step of encrypting the counter value, a message encrypting step of encrypting the divided data, and a message authentication code generating step of generating an authentication code of the divided data, And controls the arithmetic operation unit and the ary key generation unit.

Wherein the counter encrypting step comprises: incrementing the counter value; Encrypting the counter according to an aria algorithm; And storing the encrypted value.

The message encrypting step may include: comparing the number of the divided data blocks with the counter threshold value; Encrypting the counter value exceeding the threshold value; Performing an XOR operation on the encrypted counter value and the data block; And storing the cipher text of the input data as a result of the OR operation.

Wherein the message authentication code generation step comprises a step of performing a bitwise OR operation on the data block corresponding to the counter value and the ciphertext block of the cipher text; And outputting the ciphertext block as a message authentication code value.

 According to the present invention, in performing the message authentication and the encryption at the same time, the aria encryption device can reduce the hardware size by using one aria encryption module. Also, it is possible to increase the operation speed of the message authentication and encryption using the block cipher ARIA by providing a calculation method of performing the encryption on the counter before the plaintext data is input.

Also, it reduces the computation delay time that can occur when the message authentication code is generated by using the Aria round operation unit using the pipeline register.

1 is a block diagram illustrating an apparatus for decoding an aria according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating an aria rounding unit of an aria decoding apparatus according to an embodiment of the present invention. Referring to FIG.
3 is a flowchart illustrating a counter encrypting step in the method of decrypting aria according to the present embodiment.
FIG. 4 is a flowchart illustrating a message encryption step in the method of decrypting aria according to the present embodiment.
5 is a flowchart illustrating a message authentication code generation step in the method of decoding an aria according to the present embodiment.
6 is a flowchart showing the message authentication code generation step of FIG. 5 in more detail.

The following merely illustrates the principles of the invention. Therefore, those skilled in the art will be able to devise various apparatuses which, although not explicitly described or shown herein, embody the principles of the invention and are included in the concept and scope of the invention. It is also to be understood that all conditional terms and examples recited in this specification are, in principle, expressly intended for the purpose of enabling the inventive concept to be understood, and are not intended to be limiting as to such specifically recited embodiments and conditions .

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: . In the following description, a detailed description of known technologies related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily blurred. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of an encryption apparatus 100 for performing message authentication and encryption according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 1, an arial-decoding apparatus 100 according to the present embodiment includes a data input unit 110, a counter generating unit 120, an aria rounding unit 130, an ariary key generating unit 140, a controller 150 And a data output unit 160.

The data input unit 110 divides and stores the input plain text data. That is, the input plain text data is divided into 128-bit units and stored. Therefore, the data input unit according to the present embodiment divides the plaintext data into 128-bit messages.

The counter generation unit 120 generates and stores a predetermined number of counter values.

The Aria round calculator 130 performs an encryption operation on the counter value according to the Aria algorithm.

The ARI key generation unit 140 generates a round key used in each round of the Arya round operation unit.

The control unit 150 sets a counter threshold value, controls the counter threshold value to perform an encryption operation on the counter values as many as the counter threshold value, and performs the counter encryption step, the message encryption step, and the message authentication code generation step, The arithmetic operation unit 130, and the ariaki key generation unit 140, as shown in FIG.

Furthermore, the data output unit 160 outputs the result of the aria round calculator 130.

The arithmetic round unit 130 of FIG. 1 includes a plurality of round operation units for performing a CTR mode at high speed, a pipeline register is inserted between each round operation units, and a sub-pipeline register is inserted in the round operation unit .

However, if the CBC-MAC mode is performed using the pipeline-type Arya round operation unit as described above, the encryption operation speed is reduced due to the internal sub-pipeline register. Therefore, the aria round operation unit according to the present invention utilizes a sub-pipeline register in the CTR mode and does not utilize the sub-pipeline register in the CBC-MAC mode. Hereinafter, the aria round operation unit will be described in more detail with reference to FIG.

FIG. 2 is a detailed block diagram of the aria round calculator 130 according to an embodiment of the present invention, illustrating an aria round calculator 130 for performing a first round of the aria algorithm.

The ariah round calculation unit 130 after the first round can recycle the ariah round calculation unit for performing the first round.

2, the aria round operation unit according to the present embodiment includes first and second multiplexers 131a and 131b, a first XOR operator 133a, a first permutation unit 134, a sub-pipeline register 135 A third multiplexer 131c, a second permutation unit 131c, a spreading unit 137, and a second XOR operator 133b.

 In FIG. 2, in the block cipher algorithm, the master key is divided into a first key and a second key.

The first XOR operator 133a receives the key initialization constant and / or the round key through the first multiplexer 131a of the plain text and / or the first key through the second multiplexer 131b and performs the exclusive-OR operation do.

The first replacement unit 134a performs a part of the replacement operation for the result value of the first XOR unit.

The sub pipeline register 135 stores the result of the first permutation.

The third multiplexer 131c selects an output value of the sub-pipeline register 135 and a result value of the first permutation unit 134a.

The second permutation unit 134b performs a part of the permutation operation on the output value of the third multiplexer 131c.

The spreading unit 137 performs a spreading operation on the result of the second permutation unit and the second XOR operator 133b performs an exclusive OR operation on the result of the spreading unit 137 and the second key .

The multiplexers 131a and 131b for selecting the input of the first XOR operator 133a and the second XOR operator 133b may use the Aria round operator 130 for performing the first round It is necessary to perform the round operation and the key initialization process for the plain text.

Hereinafter, a method of decoding an aria coded by the aria-decoding apparatus 100 according to the present embodiment will be described with reference to Figs. 3 to 5. Fig.

The method includes a counter encrypting step of encrypting a counter value, a message encrypting step of encrypting the divided data, and a message authentication code generating step of generating an authentication code of the divided data.

3 is a flowchart illustrating a counter encrypting step in the method of decrypting aria according to the present embodiment. Referring to FIG. 3, the counter encrypting step includes a counter value increasing step S110, a counter encrypting step S120, an encrypted value storing step S130, and a counter threshold value comparing step S140.

The counter value increasing step (S110) increments the counter value composed of predetermined bits by one.

The counter encryption step (S120) encrypts the counter value according to the aria algorithm.

The encryption value storage step (S130) stores the encrypted value.

If the counter value is less than the counter threshold value, the counter is compared with the counter threshold value. If the counter value is less than the counter threshold value, the process is repeated (S140) .

The counter encryption step according to the present embodiment is preferably performed before the message for encryption is input, at the time when the counter limit value is set.

By performing counter encryption in advance according to the present embodiment, it is possible to shorten the time of encryption of a message when a message is actually input. The message encryption step will be described below.

FIG. 4 is a flowchart illustrating a message encryption step in the method of decrypting aria according to the present embodiment. Referring to FIG. 4, the message encryption step includes a counter threshold value comparison step S210, an excess counter encryption step S220, a counter value and date block logical sum step S230, and a ciphertext storage step S240.

The counter threshold value comparison step (S210) compares the set counter threshold value with the number of input data blocks. In the message encrypting step, if the number of input data blocks is larger than the counter limit value as a result of the comparison, the counter encrypting step is performed to perform encryption of the counter by the number of input data blocks exceeding the counter limit value.

For example, assuming that the block size of the input data is 128 bits, the number of blocks is 10, and the counter limit value is 6, six counter blocks are calculated before the input data for encryption is inputted. Therefore, encryption of four counter values exceeding the counter threshold value is required.

Therefore, in the present embodiment, the excess counter encryption step (S220) exceeds the counter limit value through the above-described counter encryption step, and performs encryption on the counter value that is insufficient compared to the number of blocks.

If the number of blocks of the input data is equal to or smaller than the counter limit value, the counter value and data block logical sum operation S230 are performed without performing a separate counter increment operation, And performs a logical sum operation.

Further, the ciphertext storage step (S240) stores the result as a ciphertext of the input data and outputs the ciphertext. The message authentication code generation step will be described below.

FIG. 5 illustrates a message authentication code generation step in the method of decoding an aria according to the present embodiment. The message authentication code generation step includes an exclusive-OR step S310 and a message authentication code value output step S320.

The exclusive-OR step S310 performs a bitwise OR operation on the data block corresponding to the counter value and the ciphertext block of the cipher text.

Further, the message authentication code value output step (S320) outputs the ciphertext block as a message authentication code value.

6, the exclusive-OR step sets an initial value (S302), where i denotes an arbitrary counter value, M denotes an input message, and C denotes a cipher text. C [i] means the i-th input data block. C [0] means the initial value of C. For example, if the input data consists of 10 blocks in units of 128 bits, it is expressed as C [1] to C [10]. Set i = 0 and C [0] = 0 in the initial parameter setting process.

After setting the initial value, the counter value is increased by 1 (S304).

Then, an exclusive OR operation is performed between the i-th input message block and the i-th ciphertext block (S312). If the counter value i is smaller than the number of input data blocks, the above step is repeated. If the counter value i is equal to the number of input data blocks, the last ciphertext block is set as the message authentication code value (S322).

Meanwhile, the method of the present invention may be embodied as a computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like. Computer-readable code in a distributed fashion can be stored and executed. In addition, functional programs, codes, and code segments for implementing the present invention can be easily deduced by programmers skilled in the art to which the present invention belongs.

It will be apparent to those skilled in the art that various modifications, substitutions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. will be.

Therefore, the embodiments disclosed in the present invention and the accompanying drawings are intended to illustrate and not to limit the technical spirit of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments and the accompanying drawings . The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims (9)

A data input unit for dividing input plain text data into a plurality of data blocks;
A counter generating unit for generating a counter value;
An aria round operator for performing an encryption operation on the data block with respect to the counter value using a round key according to an ARIA algorithm; And
And an ary key generation unit for generating the round key used in each round of the aria round operation unit,
The round calculator calculates,
A first multiplexer for outputting the data block or the first key;
A second multiplexer for outputting a key initialization constant or the round key;
A first XOR operator for calculating an exclusive OR of the data block or the first key and the key initialization constant or the round key;
A first permutation unit for generating a first permutation operation value by applying a permutation operation to the exclusive logical sum;
A sub-pipeline register for storing the first permutation operation value;
A third multiplexer for receiving and outputting a first permutation operation value from the first permutation unit or the subpipeline line register;
A second permutation unit for applying a further permutation operation to the first permutation operation value to generate a second permutation operation value;
A diffusion unit for applying a diffusion operation to the second permutation operation value to generate a diffusion operation value; And
A second XOR operator for generating an exclusive OR for the spreading operation value and the second key;
, ≪ / RTI &
The third multiplexer transmits the first permutation value received from the sub-pipeline register in the CTR (Counter) mode to the second permutation unit, and transmits the first permutation value to the second permutation unit in the Cipher Block Chaining (MAC) And transfers the first replacement operation value received from the first replacement unit to the second replacement unit.
The method according to claim 1,
The aria round operation unit
A plurality of round operators;
And a pipeline register for connecting between the round operation units.
delete The method according to claim 1,
The counter value is incremented by one to a counter limit value through the counter generation unit, and the counter value is encrypted and stored through the aria round operation unit,
When the number of data blocks exceeds the counter limit value through the aria round operation unit,
Further comprising a controller for generating a ciphertext by performing an exclusive OR operation on at least one of the encrypted counter value and the encrypted exceeded value counter and the data block.
5. The method of claim 4,
Wherein the control unit performs a bitwise OR operation on the data block corresponding to the counter value and the ciphertext block of the cipher text through the ariA round operation unit,
And outputting the last ciphertext block of the ciphertext block as a message authentication code value.
A method for performing a cryptographic aria encryption in an aria cryptosystem,
Generating a counter value and encrypting the counter value;
Encrypting a data block of plaintext data; And
Generating a message authentication code for the plaintext data;
Lt; / RTI >
The step of encrypting the counter value
In the first multiplexer, outputting the data block or the first key;
Outputting, in the second multiplexer, a key initialization constant or a round key;
Calculating, in the first XOR operator, an exclusive OR of the data block or the first key and the key initialization constant or the round key;
Generating a first permutation operation value by applying a permutation operation to the exclusive-OR in the first permutation unit;
Storing, in a sub-pipeline register, the first permutation operation value;
Receiving and outputting a first permutation operation value from the first permutation unit or the subpipeline line register in the third multiplexer;
Generating a second permutation operation value by applying an additional permutation operation to the first permutation operation value in a second permutation unit;
Generating a spreading operation value by applying a spreading operation to the second permutation operation value in a spreading unit; And
In a second XOR operator, generating an exclusive OR for the spreading operation value and the second key;
, ≪ / RTI &
In the third multiplexer, the step of receiving and outputting the first permutation operation value from the first permutation unit or the subpipeline line register may include receiving the first permutation operation from the subpipeline line register in the CTR (Counter) mode, Value to the second replacing unit and transmits the first permutation value received from the first permutation unit to the second permutation unit in a CBC (Cipher Block Chaining) -MAC (message authentication code) mode. A method for decoding an aria.
The method according to claim 6,
Generating a counter value, and encrypting the counter value,
Wherein the counter value is incremented by 1 to a counter limit value, and the counter value is encrypted and stored through an aria round operation unit.
8. The method of claim 7,
The step of encrypting the data block of plaintext data comprises:
If the number of data blocks exceeds the counter limit value through the ariah rounding operation, encrypting the counter value exceeds the limit value; And
Generating a ciphertext by performing an XOR operation on at least one of the encrypted counter value and the encrypted exceeded counter value and the data block;
/ RTI >
9. The method of claim 8,
Wherein generating the message authentication code for the plaintext data comprises:
Performing a beta OR operation on the cipher text block of the cipher text and the data block corresponding to the counter value through the aria round operation unit; And
And outputting the last ciphertext block of the ciphertext block as a message authentication code value.

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