KR101717687B1 - The circuit of the detector for positron emission tomography with selecting effective signals and reducing channels - Google Patents

Abstract

The present invention provides a driving circuit having a function of selecting only an effective signal by using a digital logic within a circuit. The present invention comprises: a first OR gate configured to output a fourth signal obtained by OR operation of a first delay signal and a second delay signal; a second D flip flop receives a fifth signal outputted by inputting the fourth signal and a third signal to a second OR gate; and an AND gate configured to output a timing signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a positron emission tomography detector drive circuit for positron emission tomography

TECHNICAL FIELD The present invention relates to a detector driving circuit for positron emission tomography which has an effective signal selection and channel reduction function.

PET (Positron Emission Tomography) injects different tracers according to the diagnosis target. This tracer moves to a position to observe, emitting a certain amount of positron according to the amount of positron emission material being injected. When it is collected in the observation area, the positron is continuously emitted at the corresponding position. At this time, the released positon is annihilated by binding with electrons in the body. At the same time, two photons (ex: gamma rays) emerge in the opposite direction (coincidence event). At this time, the principle of PET is to detect a gamma ray to generate a reaction line (LOR, line of response), and to accumulate the reaction line to produce a sectional image. Therefore, it is necessary to detect two radiation arising from one extinction, which means to detect "concurrent event".

The detection time and the energy of the detected signal when detecting the "coincidence event" are the same, and it is necessary to be able to record the position where each radiation is detected. In particular, the detection time is the interval between two incident radiation. In the case of general PET, the detection time of two radiation is less than 5 ns. In the case of TOF (time of flight) PET, do. Therefore, the time resolution of the system is a very important factor in the PET system.

The PET system has a variety of structures depending on the type of detector and the circuit. In order to realize the above-mentioned reaction line (LOR), the time, energy and position information of the first incident radiation should be extracted within a predetermined time.

In general, the photon detection circuit for PET consists of a gamma camera using a photomultiplier tube (PMT) as a detector. In recent years, there is a tendency to be replaced by a signal detection circuit using a silicon photomultiplier (SiPM) as a detector. The above mentioned photocatalytic pipe (PMT) has high operating voltage (~ 1000V) and is very bulky than SiPM. In addition, the operation is unstable in the magnetic field, and the price is several tens times higher than the SiPM.

However, when SiPM is used, the number of signal channels to be received is greatly increased. PET requires tens of thousands of modules consisting of SiPMs. Thus, by implementing a PET system that requires tens of thousands of SiPM outputs from the detector as discrete devices, the prior art requires a significantly larger system. Therefore, by changing the detector from PMT to SiPM, the volume of the PET detector is reduced, but the volume change of the data acquisition system (DAS) is not large.

Figure 1 is a graph showing the detector output signal 1000 output by the detector described above over time, according to one embodiment of the prior art.

The detector output signal 1000 of Figure 1 may be input to a comparator. In addition, the comparator may further input preset comparison reference values (ex: 1001 and 1002). The comparator may output different output values depending on whether the detector output signal 1000 is greater than the comparison reference value. It is possible to determine whether the detector output signal provides a sufficiently large output value by using the output value of the comparator. If the detector is provided with a sufficiently large output value, it can be determined that the above-mentioned radiation reaches the detector.

The above-mentioned comparison reference value can be preset in order to extract from the signal generated by the detector the time of incidence or detection time of the radiation incident on the detector. The time information may be different, and the difference of the time information may be defined in terms of 'time walk' in the present specification.

Referring to the detector output signal 1000 shown in FIG. 1, a human can recognize that the time at which a signal generated by the detector is incident is t0. However, the above- . At this time, the time information obtained when the comparison reference value compared to the detector output signal 1000 is set as the 'first reference signal 1001' is t1, and the comparison reference value is referred to as a 'second reference signal 1002) ', the time information obtained is t2. That is, a time work determined according to the comparison reference value occurs.

From the above description, it can be understood that when the comparator is used in the PET system, the temporal resolution tends to increase as the comparison reference value input to the comparator has a smaller value. That is, as the comparison reference value has a smaller value, the time at which the radiation reaches the detector can be more accurately measured.

Therefore, in order to accurately obtain the incidence time of the radiation incident on the detector by using only one fixed comparison reference value, that is, when the comparison reference value inputted to the comparator is constantly changed without varying according to the situation, The reference value should be set small.

On the other hand, it may happen that the noise generated due to the characteristic of the detector can not be distinguished from the actual signal. Fig. 2 is for explaining this phenomenon.

Fig. 2 shows a case in which a valid signal 1101 and an invalid signal 1102 (ex: noise) are included in the detector output signal 1000 output by the detector as shown in Fig.

As shown in FIG. 2, according to the 'first reference signal 1003', two pieces of time information, t1 and t2, can be obtained. At this time, since the signal at t1 is 'valid signal 1101' and the signal at t2 is 'invalid signal 1102', time information should not be obtained for such an invalid signal. Thus, there is a "trade off" in which it is difficult to obtain accurate information if the comparison reference value is too low.

3 is a graph for explaining an example of acquiring data using two reference signals when a valid signal and an invalid signal are included in the detector output signal 1000 output from the detector as shown in FIG. to be.

As shown in FIG. 3, according to another embodiment of the prior art, a signal having two comparison reference values ('first reference signal 1004', 'second reference signal 1005'), So that data can be acquired only when it passes all of the data. At this time, the 'first reference signal 1004' may be set to a low level to obtain all of the time information regardless of whether it is a valid signal from the detector output signal, and the 'second reference signal 1005' So that only the energy information of the signal can be obtained.

For example, in the graph shown in FIG. 3, 'first signal 1201', 'invalid signal 1202', and 'effective signal 2 1203' of 'first reference signal 1004' Energy information of the valid signal 1 1201 and the valid signal 2 1203 can be obtained according to the second reference signal 1005. [

Meanwhile, according to the detection system according to the related art, the analog type signal coming from the detector is connected to the DAS to receive the input. At this time, when an analog signal is transmitted over 3 m, distortion of the signal occurs and a correction circuit for this is required. When the ADC is used near the sensor to convert an analog signal to a digital signal, the analog signal is distorted due to a clock signal supplied to the ADC.

In the present invention, a detector driving circuit device having a function of selecting only valid signals using digital logic in a circuit is provided.

A detector unit driving circuit device according to one aspect of the present invention includes a first delay unit that receives a first delay signal output from a first common module that receives an output signal of a first positron emission tomography detector and an output signal from a second positron emission tomography detector A first OR gate for outputting a fourth signal obtained by performing an OR operation on a second delay signal output from a second common module to be input; A second D flip-flop which receives a fourth signal and a third signal as a clock signal, which is input to the second OR gate, and which receives the second signal as a status signal and outputs an enable signal, ; And an AND gate for outputting a timing signal by ANDing the third delay signal delayed by the first signal and the energy signal.

Here, the second common module has the same structure as the first common module, and the first common module compares the output signal of the first positron emission tomograph and the first reference signal of the first level with each other A first comparator adapted to output the first signal obtained by the first comparator; A second comparator adapted to output the second signal obtained by comparing the output signal with a second reference signal of a second level greater than the first level; A first XOR gate for XORing the first signal and the second signal to output the third signal; A first D flip-flop which receives the third signal as a clock signal, receives the second signal as a status signal, and outputs the energy signal; And a first delay unit for delaying the energy signal and outputting the first delay signal.

Here, the energy signal includes information on the energy of radiation sensed by the first positron emission tomography detector connected to the input terminal of the first common module, and outputs the energy signal of the first common module .

According to another aspect of the present invention, there is provided a detector driving circuit device including a plurality of detector unit driving circuit devices, the detector driving circuit device including a plurality of detector unit driving circuit devices, wherein the enable signal is a logical high value The determination unit may determine that the radiation has arrived at the first positron emission tomography detector more than the second positron emission tomography detector.

At this time, based on the signals output from the plurality of detector unit driving circuit devices, a winner detector that first detects radiation among a plurality of positron emission tomography detectors connected to the input ends of the plurality of detector unit driving circuit devices is determined Wherein the first identification information (Pos) of the plurality of positron emission tomography detectors is provided to the detector driving circuit device through the detector unit driving circuit device, and (1) the first identification Information (Pos); (2) the energy signal output from the detector unit driving circuit device connected to the winner detector; And (3) outputting the timing signal output from the detector unit driving circuit device connected to the winner detector.

According to another aspect of the present invention, there is provided a driving circuit device comprising a plurality of detector driving circuit devices, wherein each of the detector driving circuit devices includes: (1) a second identification of the detector driving circuit device Information (Mod_id); (2) the identification information (Pos) of the winner detector determined by the respective detector drive circuit devices, (3) the energy signal of the winner detector determined by the respective detector drive circuit devices, and (4) The timing signal of the winner detector determined by the device to the drive circuit device.

Here, the driving circuit may include a first upper delay signal output from the first upper common module, which receives the output signal of the first detector driving circuit device among the plurality of detector driving circuit devices, and a second upper delay signal output from the second detector driving circuit device A fourth OR gate for outputting an eighth signal obtained by performing an OR operation on a second upper delay signal output from a second upper common module receiving a signal; A second XOR gate receiving a third delay signal and an output signal of each of the detector driving circuit devices and outputting a seventh signal; A fifth OR gate for ORing the eighth signal and the seventh signal to output a ninth signal; And a third D flip-flop that receives the ninth signal as a clock signal and receives an output signal of each of the detector driving circuit devices as a status signal to output an enable signal.

In this case, the first upper common module has the same structure as the second upper common module, and the first upper common module delays the output signal of the first detector driving circuit device to output the third delay signal A third delay unit; And a fourth delay unit delaying the third delay signal and outputting the first upper delay signal.

According to the present invention, since it has a function of selecting only effective signals, the number of outputs from a plurality of detectors can be significantly reduced.

Further, according to the present invention, it is possible to extract information of a desired signal without distortion of an analog signal as a circuit which does not use a clock signal.

In addition, when implementing the PET system through the present invention, it is possible to construct a PET using a smaller-sized DAS because a much smaller number of inputs is required than in the prior art, which can reduce the size and production cost of the PET .

1 is a graph showing, over time, a detector output signal output by the above-described detector, according to an embodiment of the prior art.
Fig. 2 shows a case where a valid signal and an invalid signal are included in the detector output signal outputted by the detector as shown in Fig.
FIG. 3 is a graph for explaining an example of acquiring data using two reference signals when a valid signal and an invalid signal are included in a detector output signal output from the detector, as shown in FIG.
4 is a view for explaining a driving circuit according to an embodiment of the present invention.
5 is a view for explaining the structure of the detector driving circuit device shown in Fig.
6 is a block diagram of the detector unit driving circuit device shown in Fig.
FIG. 7 shows signals (waveforms) outputted from the respective components included in the detector unit driving circuit device shown in FIG.
FIG. 8 is a diagram for explaining a difference between signals output from respective components included in the detector unit driving circuit device according to a signal input to the detector unit driving circuit device shown in FIG.
9 is a block diagram for explaining the structure of the first router shown in FIG.
10 shows signals output from the respective components included in the first router shown in FIG.
11 is a diagram for explaining a difference between signals output from respective components included in the first router according to signals input to the first router shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, but may be implemented in various other forms. The terminology used herein is for the purpose of understanding the embodiments and is not intended to limit the scope of the present invention. Also, the singular forms as used below include plural forms unless the phrases expressly have the opposite meaning.

Hereinafter, the structure of the driving circuit 100 according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG.

4 is a view for explaining a driving circuit 100 according to an embodiment of the present invention.

FIG. 5 is a view for explaining the structure of the detector driving circuit device 110 shown in FIG.

4, a driving circuit 100 according to an embodiment of the present invention includes a plurality of detector driving circuit devices 110, 111, 112, 113, and 114, and a plurality of detector driving circuit devices 110 And a first router 20 that receives the signals to be output and extracts the first signal input from the plurality of detector driving circuit devices 110.

5, each of the detector driving circuit devices 110 outputs an output signal from a plurality of detector unit driving circuit devices 10, 1, 2, 3, 4 and a plurality of detector unit driving circuit devices 10, And a second router 30 that receives signals from the plurality of detector unit driving circuit devices 10, and extracts the first signal input to each of the plurality of detector unit driving circuit devices 10 connected to the input ends thereof.

At this time, the driving circuit 100 according to an embodiment of the present invention is a circuit for a currently commercialized SiPM, and it is particularly easy to apply to a product in which a SiPM is a 4x4 array. The driving circuit 100 shown in FIG. 4 according to an embodiment of the present invention is applied to a 4 × 4 array SiPM.

5 is an m-to-1 router, and the router 20 of FIG. 4 is an m * n-to-1 router. In the case of using SiPM having an m * n matrix structure to implement the present invention, -1 router. Or the router 30 of FIG. 5 may be an n-to-1 router and the router 20 of FIG. 4 may be an m * n-to-1 router.

At this time, a signal output from each detector unit driving circuit device 10 is a 4-bit bus signal, and includes an energy signal (1 bit), a time signal (1 bit), an enable signal (1 bit) Time signal (1 bit).

6, the time signal (1 bit) is a signal of reference numeral 120 shown in FIG. 6, and the enable signal (1 bit) is a signal of reference numeral 118 Lt; / RTI >

That is, in the embodiment of the present invention, since the detector driving circuit device 110 includes the four detector unit driving circuit devices 10, the signals output from the four detector unit driving circuit devices 10 are 16 bits Lt; / RTI > At this time, a signal (4 bits) including an energy signal (Energy) (1 bit), a time signal (Time), and a position signal (Position) (2 bits) may be output through the second router (30).

In FIG. 5, the position signal is represented by 2 bits (Position 0, Position 1), which is a suitable example when the SiPM connected to the detector unit driving circuit device 10 is provided in the form of a 4 * 4 matrix.

In an embodiment of the present invention, since the driving circuit device 100 includes four detector driving circuit devices 110, signals output from the four detector driving circuit devices 110 may be a total of 16 bits. At this time, an energy signal (Energy & Part), a time signal (Time), a position signal (Position) (2 bits), and a module identifier signal (Mod_id) (2 bits) are transmitted through the first router (6 bits) including the signal can be output.

The above-described module identifier signal may be a signal indicating the row position (or column position) of the detector included in the SiPM in which the detectors are arranged in a matrix form. And the position signal may be a signal indicative of the column position (or row position) of the detector included in the SiPM in which the detectors are arranged in a matrix form.

Fig. 6 is a block diagram of the detector unit driving circuit device 10 shown in Fig.

FIG. 7 shows signals (waveforms) output from the individual components included in the detector unit driving circuit device 10 shown in FIG.

8 is a diagram for explaining the difference of signals output from the respective components included in the detector unit driving circuit device 10 in accordance with signals inputted to the detector unit driving circuit device 10 shown in Fig. 6 . In this case, the waveforms shown in FIG. 8 show the waveforms output from the respective components in the case of the valid signal 40 shown in FIG.

6, 7, and 8, the structure of the detector unit driving circuit device 10 according to an embodiment of the present invention and the signals output from the respective components will be described.

The detector unit driving circuit device 10 includes a first comparator 13 configured to output a first signal 111 obtained by comparing an output signal of the detector 11 with a first reference signal of a first level, And a second comparator (14) adapted to output a second signal (112) obtained by comparing an output signal of the first reference signal (11) with a second reference signal of a second level greater than the first level. The output signal of the detector 11 may be amplified through a preamplifier 12 and input to the first comparator 13 and the second comparator 14.

The first signal 111 and the second signal 112 are inputted to the first XOR gate 15 and the third signal 113 outputted from the first D flip flop DFF 16 And the energy signal 114 may be output when the second signal 112 is input to the first D flip-flop 16 as a status signal. At this time, the energy signal 114 may include information on the energy of the radiation sensed by the detector 11 connected to the input terminal of the detector unit driving circuit device 10.

At this time, the energy signal 114 may be delayed through the first delay unit 17 to output the first delay signal 115.

In one embodiment of the present invention, the first comparator 13, the second comparator 14, the XOR gate 15, the first D flip-flop 16, and the first delay unit 17 Can be defined as a 'common module 200'. At this time, the common modules 200 included in each detector unit driving circuit device 10 may have the same structure.

At this time, four signals 114 generated from each of the four detector unit driving circuit devices 10 may occur at different points in time. In order to extract only signals generated by the fastest incident radiation among the four detectors 11 connected to the respective input terminals of the detector unit driving circuit device 10 and ignore other signals, The first delay signal ex_1 115_1 outputted from the common module 200 included in the specific detector unit driving circuit devices is input to the input terminal of the 1 OR gate 18, 115_2, 115_3, and 115_4 that are output from the common module 200. [

That is, for example, the first delay signals 115 and 115_1 output from the first common modules 200 and 201 included in the first detector unit driving circuit device 10, The first delay signals 115 and 115_2 output from the included second common modules 200 and 202 and the first delay signals 115 and 115_2 output from the third common modules 200 and 203 included in the third detector unit driving circuit device 10 1 delay signals 115 and 115_3 and first delay signals 115 and 115_4 output from the fourth common module 200 and 204 included in the fourth detector unit driving circuit device 10 to the first OR gate 18).

The fourth signal 116 and the third signal 113 outputted through the first OR gate 18 are input to the second OR gate 19 and the fifth signal 117 outputted from the second D flip- Flop 21 and the second signal 112 is input to the second D flip-flop 21 as a status signal, the enable signal 118 may be output.

If the second delay signal 119 and the energy signal 114 delayed by a predetermined time through the second delay unit 22 are input to the AND gate 23, the timing signal 120 Can be output.

At this time, the enable signal 118 may be a signal to prevent circuit operation from being disturbed when other radiation is incident while processing the fastest incident radiation. That is, since the signal is used as a signal for operating the entire circuit, necessary information must be located in the enable signal 118.

At this time, time information can be obtained at the rising edge of the first signal 111. At this time, the first signal 111 is delayed for a certain time to be positioned in the enable signal 118 in order to place the time information in the enable signal 118.

The energy signal 114 obtained according to this process represents the energy of the first radiation incident, and the timing signal 120 represents the time of the first radiation incident. At this time, the position of the generated signal can be indicated through an encoder.

7, since the energy signal 114 and the timing signal 120 have no output for a signal that does not exceed the energy reference, only the information about the valid signal 40 is obtained through the above operation .

5, in the detector driving circuit device 110, the second router 30 receives the energy signal 114 output from the plurality of detector unit driving circuit devices 10, the enable signal 118, And the timing signal 120 to determine a winner detector that first detects radiation among a plurality of detectors 11 connected to an input terminal of the plurality of detector unit driving circuit devices 10. [

At this time, in order to extract only the signal 41 generated from the winner detector that has detected the radiation from among the valid signals 41 and 42 generated from the respective detectors 11, the enable signal 118) can be used. When the circuit shown in FIG. 6 is used, the fact that the enable signal 118 is not outputted from the detector unit driving circuit device 10 other than the detector unit driving circuit device 10 connected to the winner detector is shown in FIG. 8 . Therefore, the timing signals 120 output from the remaining detector unit driving circuit device 10 may not be provided to the detector driving circuit device 110.

The timing signal 120 is a signal indicating the timing at which the enable signal 118 should be confirmed. That is, it is assumed that the detector 11 determines that the radiation first arrives at the detector 11 only when the enable signal 118 is the detector 11 including the logical high value while the timing signal 120 has the logical high value .

Accordingly, the signal output from the detector driving circuit device 110 is the first identification information of the winner detector that first detects radiation among the plurality of detectors 11 connected to the input terminal of the plurality of detector unit driving circuit devices 10 (Energy) outputted from the detector unit driving circuit device 10 connected to the winner detector, and the timing signal (Time) outputted from the detector unit driving circuit device 10 connected to the winner detector, . ≪ / RTI >

4, the first router 20 receives signals output from each of the plurality of detector driving circuit devices 110, and may output information on the fastest incoming signal have. At this time, the first router 20 may be further configured to receive, from each of the plurality of detector driving circuit devices 110, signals relating to second identification information (Mod_id) of each detector driving circuit device. Here, the second identification information may refer to the module identifier signal.

In contrast, the structure of the first router 20 according to an embodiment of the present invention and the signals output from the respective components will be described below with reference to FIGS. 4, 9, 10, and 11. FIG.

FIG. 9 is a block diagram for explaining the structure of the first router 20 shown in FIG.

10 shows signals output from the respective components included in the first router 20 shown in Fig. At this time, the waveforms shown in FIG. 10 show the waveforms output from the respective components when the signal 40 is valid.

11 is a diagram for explaining a difference of signals output from respective components included in the first router 20 according to a signal input to the first router 20 shown in FIG.

The first router 20 delays the energy signal 212 among the signals (Pos, Mod_id, Energy, and Time) received from the detector driving circuit device 110 through the third delay unit 31, And may output the delay signal 213. [ At this time, the third delay signal 213 and the energy signal 212 may be input to the second XOR gate 32 to output the seventh signal 24. At this time, in order to generate the enable signal, the energy signal 212 is delayed and the output third delay signal 213 is further delayed through the fourth delay unit 33 to output the fourth delay signal 215 .

Here, in this specification, for example, the 'fourth delay signal 215' may be referred to as the 'upper delay signal 215'.

In this case, in one embodiment of the present invention, the third delay unit 31 and the fourth delay unit 33 shown in FIG. 9 may be defined as an 'upper common module 300'.

At this time, in the case of the first router 20 of FIG. 4, four circuits shown in FIG. 9 may be included. In Fig. 9, only one of them is shown for the sake of convenience. Therefore, in the case of the first router 20 of FIG. 4, four upper common modules 300 may be included. Different energy signals 212 output from different detector driving circuit devices 110 may be input to each upper common module 300. In the case of the first router 20 of FIG. 4, the four fourth delay signals 215 output from the four upper common modules 300 are input to the four fourth OR gates 34 included therein have.

The fourth delay signal 215 output from each of the upper common modules 300 is supplied to the OR gate 35 through the eighth signal 216 and the seventh signal 24 which are ORed through the fourth OR gate 34, The ninth signal 217 can be output. When the ninth signal 217 is applied to the clock signal of the third D flip flop 36 and the energy signal 212 is applied to the status signal, the tenth signal 218 may be output.

11, the tenth signal 218 can be used as an enable signal, and according to the structure shown in Fig. 9, the first of the plurality of detector driving circuit devices 110 is detected The enable signal may not be outputted to the detector driving circuit device 110 except for the detector driving circuit device 110 for the winner detector.

At this time, the first identification information (Pos) and the second identification information (Pos) indicating the row position and column position of the winner detector that detects the earliest radiation among the plurality of detector driving circuit devices 110 using the tenth signal 218 Mod_id), the energy signal (Energy & Part), and the timing signal (Time).

The driving circuit 100 according to an embodiment of the present invention includes 16 modules and is expandable. In the case of 64 channels, four modules can be extended using the detector drive circuit 110 in the module. That is, a 64-channel module does not need four times as many outputs as a 16-channel module, but only two outputs for indicating the position. In the circuit according to the related art, the output required is doubled as the number of detectors is increased. However, when the driving circuit 100 according to an embodiment of the present invention is used, only the information about the signal is extracted Therefore, even if the number of detectors is increased, only an output for displaying position information is added.

In particular, the driving circuit 100 according to an embodiment of the present invention can perform the contents without a periodic clock signal. In the detector, the clock signal acts as a noise source. However, since the clock signal is not required in the driving circuit 100 according to an embodiment of the present invention, even if it is installed close to the detector, there is no influence on extracting the signal. Therefore, if the driver circuit 100 is designed as an application specific integrated circuit (ASIC), the structure of the PET system can be greatly simplified.

In this case, the driving circuit 100 according to an exemplary embodiment of the present invention may extract the first signal among a plurality of channels, such as SPECT (single photon emission computed tomography), as well as a PET system It is possible to apply it to a circuit that performs

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the essential characteristics thereof. The contents of each claim in the claims may be combined with other claims without departing from the scope of the claims.

Claims (4)

A second delay signal output from the second common module, which receives the first delay signal output from the first common module and the output signal from the second positron emission tomograph for detecting the output signal of the detector for the first positron emission tomography A first OR gate for outputting a fourth signal obtained by an OR operation;
A second D flip-flop which receives a fourth signal and a third signal as a clock signal, which is input to the second OR gate, and which receives the second signal as a status signal and outputs an enable signal, ; And
An AND gate configured to output a timing signal by ANDing a third delay signal delaying the first signal and an energy signal;
/ RTI >
The second common module has the same structure as the first common module,
Wherein the first common module comprises:
A first comparator configured to output the first signal obtained by comparing the output signal of the first positron emission tomography detector with a first reference signal of a first level;
A second comparator adapted to output the second signal obtained by comparing the output signal with a second reference signal of a second level greater than the first level;
A first XOR gate for XORing the first signal and the second signal to output the third signal;
A first D flip-flop which receives the third signal as a clock signal, receives the second signal as a status signal, and outputs the energy signal; And
A first delay unit for delaying the energy signal to output the first delay signal;
/ RTI >
Detector unit drive circuit device. The method according to claim 1,
Wherein the energy signal includes information about the energy of the radiation sensed by the first positron emission tomography detector connected to the input terminal of the first common module,
And to output the energy signal of the first common module,
Detector unit drive circuit device. A detector driving circuit device comprising a plurality of detector unit driving circuit devices according to claim 2,
It is determined that the radiation is first reached to the first positron emission tomograph detector only when the enable signal includes a logical high value while the timing signal has a logical high value ≪ / RTI >
Based on the signals output from the plurality of detector unit driving circuit devices, a winner detector that detects radiation first among the plurality of positron emission tomography detectors connected to the input ends of the plurality of detector unit driving circuit devices is determined ,
Wherein the first identification information (Pos) of the plurality of positron emission tomography detectors is provided to the detector driving circuit device through the detector unit driving circuit device,
(1) first identification information (Pos) of the winner detector;
(2) the energy signal output from the detector unit driving circuit device connected to the winner detector; And
(3) the timing signal outputted from the detector unit driving circuit device connected to the winner detector;
To be output,
Detector drive circuit device. A drive circuit device comprising a plurality of detector drive circuit devices according to claim 3,
Each of the detector driving circuit devices includes (1) second identification information (Mod_id) of the detector driving circuit device; (2) the identification information (Pos) of the winner detector determined by the respective detector drive circuit devices, (3) the energy signal of the winner detector determined by the respective detector drive circuit devices, and (4) The timing signal of the winner detector determined by the device to the drive circuit device,
A second upper common signal receiving unit for receiving an output signal of the first detector driving circuit and an output signal of the second detector driving circuit; A fourth OR gate for outputting an eighth signal obtained by performing an OR operation on a second upper delay signal output from the module;
A second XOR gate receiving a third delay signal and an output signal of each of the detector driving circuit devices and outputting a seventh signal;
A fifth OR gate for ORing the eighth signal and the seventh signal to output a ninth signal; And
A third D flip flop for receiving the ninth signal as a clock signal and receiving an output signal of each of the detector driving circuit devices as a status signal to output an enable signal;
/ RTI >
Wherein the first upper common module has the same structure as the second upper common module,
Wherein the first upper common module comprises:
A third delay unit delaying the output signal of the first detector driving circuit device to output the third delay signal; And
A fourth delay unit delaying the third delay signal to output the first upper delay signal;
/ RTI >
Drive circuit device.

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