KR101706240B1 - Differential receiver circuit and method for driving the same - Google Patents
Differential receiver circuit and method for driving the same Download PDFInfo
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- KR101706240B1 KR101706240B1 KR1020100138791A KR20100138791A KR101706240B1 KR 101706240 B1 KR101706240 B1 KR 101706240B1 KR 1020100138791 A KR1020100138791 A KR 1020100138791A KR 20100138791 A KR20100138791 A KR 20100138791A KR 101706240 B1 KR101706240 B1 KR 101706240B1
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Abstract
The present invention relates to a differential signal receiving circuit capable of preventing an undesired output caused by noise from a part from being supplied to a rear stage circuit. The differential signal receiving circuit includes a termination resistor connected between a first differential line and a second differential line, A differential amplifier for amplifying and outputting a difference voltage between a voltage applied to the first differential line and a voltage applied to the second differential line, a determination is made as to whether the pulse width of the output generated from the differential amplifier has a length equal to or longer than a preset reference pulse width A pulse detector for generating an output based on a result of the determination; and an error determiner for allowing or blocking the output from the differential amplifier based on the output from the pulse detector.
Description
The present invention relates to a differential signal receiving circuit and, more particularly, to a differential signal receiving circuit capable of preventing an undesired output generated by noise from the outside from being supplied to a subsequent stage circuit, and a driving method thereof.
The differential signal receiving circuit receives a pair of differential signals (LVDS: Low Voltage Differential Signals) from the differential signal transmitting circuit, amplifies the difference voltage, and supplies the differential voltage to the following circuit. At this time, when the differential lines transmitting the differential signals are turned off, the differential lines are floated, so that the voltages of these differential lines may be affected by noise from the outside. Accordingly, an undesired voltage due to noise may be supplied to the subsequent stage circuit, causing a malfunction of the following stage circuit.
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and it is an object of the present invention to provide a differential amplifier circuit, which can judge whether or not the output from the differential amplifier is to be transmitted to the following stage circuit, And to provide a differential signal receiving circuit capable of normally outputting the differential signals regardless of the magnitude of the differential signals with respect to the reference voltage, and a driving method thereof.
According to another aspect of the present invention, there is provided a differential receiving circuit including a terminating resistor connected between a first differential line and a second differential line, a voltage applied to the first differential line and a voltage applied to the second differential line, A pulse detector for determining whether a pulse width of an output generated from the differential amplifier has a length equal to or longer than a preset reference pulse width and generating an output based on the determination result; And an error determination unit for allowing or blocking an output from the differential amplifier based on an output from the detection unit.
Wherein when the pulse width of the output detected from the pulse detecting section is smaller than the reference pulse width, the error judging section blocks the output from the differential amplifier, and the pulse width of the output detected from the pulse detecting section is equal to the reference pulse width Or when it is larger than the predetermined value, the error determination unit allows the output from the differential amplifier.
The error determination unit may include a first pull-up resistor connected between the power supply unit for supplying the power supply voltage and the first differential line, a second pull-up resistor connected between the power supply unit and the second differential line, A first comparator that compares a voltage from the first differential line with a preset reference voltage and generates an output based on the comparison result, a comparator that compares the voltage from the second differential line with the reference voltage, A first NAND gate for generating an output based on an output from the second comparator, an output from the first comparator, an output from the second comparator, and an output from the pulse detector; And a second non-exclusive-OR gate for generating an output based on an output from the differential amplifier, It characterized in that it comprises an inversion for inverting the output.
Wherein the error determination unit further includes a voltage divider circuit for generating the reference voltage and the voltage divider circuit generates the reference voltage by dividing the power supply voltage from the power supply unit using a pull-up resistor and a pull- do.
Wherein at least one of the first and second pullup resistors has a resistance value that is higher than the termination resistance, the pullup resistor has a higher resistance value than the pull down resistor, and the power supply voltage is greater than the reference voltage .
Wherein the reference pulse width has a length equal to a pulse width of a first differential voltage supplied from the differential signal transfer unit to the first differential line or a second differential voltage supplied from the differential signal transfer unit to the second differential line And has a length equal to the pulse width of the pulse width.
When the pulse width of the first differential voltage is different from the pulse width of the second differential voltage, the reference pulse width is equal to the pulse width of the differential voltage having the pulse width of the smaller one of the first and second differential voltages .
According to another aspect of the present invention, there is provided a method of driving a differential receiving circuit, including: a termination resistance connected between a first differential line and a second differential line; A method of driving a differential signal receiving circuit including a differential amplifier for amplifying and outputting a difference voltage between voltages applied to a line, the method comprising the steps of: detecting an output from the differential amplifier; And a step C for allowing or blocking the output from the differential amplifier according to a result of the determination.
Wherein the step c) interrupts the output from the differential amplifier when the pulse width of the detected output is smaller than the reference pulse width, and when the pulse width of the detected output is equal to or larger than the reference pulse width And allowing the output from the differential amplifier.
When the pulse width of the first differential voltage is different from the pulse width of the second differential voltage, the reference pulse width is equal to the pulse width of the differential voltage having the pulse width of the smaller one of the first and second differential voltages .
The differential signal receiving circuit and the driving method thereof according to the present invention provide the following effects.
First, even when the first and second differential voltages swing with respect to the reference voltage, are all greater than the reference voltage, or both are smaller than the reference voltage, the first and second differential voltages can be normally transmitted to the following circuit .
Second, when the first and second differential voltages are not supplied, it is possible to prevent the output from the differential amplifier from being supplied to the rear stage circuit in order to prevent an abnormal output due to noise from the outside.
1 is a diagram showing a differential signal receiving circuit according to an embodiment of the present invention;
2 is a diagram showing signal levels of a first differential voltage and a second differential voltage
3 is a circuit diagram of a simulation circuit for confirming the operation of the differential signal receiving circuit according to the embodiment of the present invention
Fig. 4 is a diagram showing input signals input to the simulation circuit of Fig. 3 and output signals of the simulation circuit diagram
1 is a diagram illustrating a differential signal receiving circuit according to an embodiment of the present invention.
The differential signal receiving circuit according to the present invention includes a differential amplifier (D-amp), a pulse detector (PD), and an error detector (ED), as shown in FIG.
The differential amplifier D-amp amplifies and outputs the difference voltage between the voltage applied to the first differential line DL1 and the voltage applied to the second differential line DL2. To this end, the first differential line DL1 is connected to the non-inverting terminal of the differential amplifier D-amp, and the second differential line DL2 is connected to the inverting terminal. A terminating resistor Rt is connected between the first differential line DL1 and the second differential line DL2. In a normal driving state, a pair of differential signals (LVDS: Low Voltage Differential Signal) having different polarities are supplied to the first and second differential lines DL1 and DL2. For example, the first differential line VP1 is supplied to the first differential line DL1 and the second differential voltage VN is supplied to the second differential line DL2.
The pulse detector PD is provided with an output from the differential amplifier D-amp, and judges whether or not the output has a constant pulse width. Then, an output is generated based on the determination result. That is, the pulse detector PD checks the output generated from the differential amplifier D-amp, and generates an output of high logic when the output maintains the pulse width length equal to or greater than a predetermined value. Specifically, the pulse detector PD generates a low logic output when the output from the differential amplifier D-amp has a pulse width shorter than a preset reference pulse width. On the other hand, when the output from the differential amplifier (D-amp) has a pulse width equal to or longer than this reference pulse width, an output of a high logic is generated. The pulse detector may be configured using a plurality of logic gates and flip-flops.
The reference pulse width may have a length equal to the pulse width of the first differential voltage VP supplied to the first differential line DL1 from the differential signal transfer circuit or may have a length from the differential signal transfer circuit to the second differential line DL2 And may have a length equal to the pulse width of the supplied second differential voltage VN.
The pulse width of the first differential voltage VP and the pulse width of the second differential voltage VN may be the same or the pulse width of the first differential voltage VP and the pulse width of the second differential voltage VN may be the same. May have different pulse widths. When the pulse width of the first differential voltage VP is different from the pulse width of the second differential voltage VN, the reference pulse width is smaller than the smaller one of the first and second differential voltages VP and VN Its length is set equal to the pulse width of the differential voltage having the pulse width.
The error determination unit ED allows or blocks the output from the differential amplifier D-amp based on the output from the pulse detection unit PD. That is, the error determination unit ED blocks the output from the differential amplifier D-amp from being transmitted to the subsequent stage circuit when the output from the pulse detection unit PD is a low logic output. On the other hand, when the output from the pulse detector PD is the output of the high logic, the output from the differential amplifier D-amp is allowed to be transmitted to the subsequent stage circuit. This rear stage circuit may be a signal restoration circuit for restoring the output from the differential amplifier (D-amp) to a TTL (Transistor Transistor Logic) level.
1, the error determination unit ED includes a first pull-up resistor Rpu1, a second pull-up resistor Rpu2, a first comparator comp1, a second comparator comp2, An OR gate NOR1, a second NOR gate NOR2, an inverter inv, and a voltage divider circuit VD.
The first pull-up resistor Rpu1 is connected between the first differential line and a power supply for supplying the power supply voltage VCC.
The second pull-up resistor Rpu2 is connected between the power supply and the second differential line.
The first comparator comp1 compares the voltage from the first differential line DL1 with a predetermined reference voltage VREF, and generates an output based on the comparison result. To this end, the inverting terminal of the first comparator comp1 is connected to the first differential line DL1 and the non-inverting terminal is connected to the output terminal OT of the voltage dividing circuit VD for providing the reference voltage VREF Respectively.
The second comparator comp2 compares the voltage from the second differential line DL2 with the reference voltage VREF and generates an output based on the comparison result. To this end, the inverting terminal of the second comparator comp2 is connected to the second differential line DL2, and the non-inverting terminal is connected to the output terminal of the voltage dividing circuit VD.
The first NOR gate NOR1 generates an output based on the output from the first comparator comp1, the output from the second comparator comp2, and the output from the pulse detector PD. This first NOR gate NOR1 generates an output of a logic high only when any of the input signals inputted to it is high logic while generating an output of high logic when any one of the input signals is high logic, do.
The second NOR gate NOR2 generates an output based on the output from the first NOR gate NOR1 and the output from the differential amplifier D-amp. This second NOR gate NOR2 generates an output of a logic high only when any of the input signals inputted to it is high logic while generating an output of high logic when any of the input signals are high logic, do.
The inverter inv inverts the output from the second NOR gate NOR2.
The voltage distribution circuit VD generates the reference voltage VREF. To this end, the voltage divider circuit VD includes a pull-up resistor Rpu and a pull-down resistor Rpd. The pull-up resistor Rpu and the pull-down resistor Rpd are connected between the voltage supply and the ground terminal. The voltage divided by the pull-up resistor Rpu and the pull-down resistor Rpd is the reference voltage VREF.
At least one of the first and second pull-up resistors Rpu1 and Rpu2 has a resistance value that is higher than the termination resistance Rt. For example, both the first pull-up resistor Rpu1 and the second pullup resistor Rpu2 have a resistance value higher than the termination resistance Rt.
The pull-up resistor Rpu has a higher resistance value than the pull-down resistor Rpd.
The power supply voltage VCC is larger than the reference voltage VREF.
The operation of the differential signal receiving circuit according to the present invention will now be described in detail with reference to FIGS. 1 and 2. FIG.
2 is a diagram showing the signal levels of the first differential voltage VP and the second differential voltage VN.
First, as shown in FIG. 2A, the operation of the differential signal receiving circuit when the first differential voltage VP and the second differential voltage VN are larger or smaller than the reference voltage VREF will be described do. For example, when the first differential voltage VP has a level of the power supply voltage VCC higher than the reference voltage VREF and the second differential voltage VN is lower than the reference voltage VREF at a level of 0 [V] The operation of the differential signal receiving circuit will be described.
The first differential voltage VP is supplied to the first differential line DL1 and the second differential voltage VN is supplied to the second differential line DL2. At this time, a current flowing through the termination resistor Rt is generated by the first differential voltage VP and the second differential voltage VN. This current has a direction from the top to the bottom of the terminating resistor Rt. Since the first and second pull-up resistors Rpu1 and Rpu2 have a resistance value significantly larger than the termination resistance Rt, the first and second pull-up resistors Rpu1 and Rpu2 are connected to the first and second differential lines Rpu1 and Rpu2 through the first and second pull- The current supplied to the first and second differential lines DL1 and DL2 is considerably smaller than the current supplied to the first and second differential lines DL1 and DL2 through the terminating resistor Rt. Therefore, the current supplied through the first and second pull-up resistors Rpu1 and Rpu2 can be ignored.
The differential amplifier D-amp amplifies and outputs the difference voltage between the first differential voltage VP and the second differential voltage VN. At this time, since the first differential voltage VP is larger than the second differential voltage VN, the output from the differential amplifier D-amp has high logic.
The pulse detector PD compares the pulse width of the output from the differential amplifier D-amp with the reference pulse width. At this time, since the output from the differential amplifier D-amp is generated based on the first and second differential voltages VP and VN in the pulse form as described above, the output from the differential amplifier D-amp Has a pulse width. Assuming that the reference pulse width is set to the same pulse width as the pulse widths of the first and second differential voltages VP and VN, the output from the differential amplifier D-amp has the same length as the reference pulse width Since the pulse width has a pulse width, the pulse detector PD generates an output of high logic.
The first comparator comp1 compares the first differential voltage VP with the reference voltage VREF, and generates an output in accordance with the comparison result. At this time, since the first differential voltage VP is larger than the reference voltage VREF, the first comparator comp1 generates an output of low logic.
The second comparator comp2 compares the second differential voltage VN with the reference voltage VREF, and generates an output according to the comparison result. At this time, since the second differential voltage VN is smaller than the reference voltage VREF, the second comparator comp2 generates an output of high logic.
The output of the high logic generated from the pulse detector PD, the output of the low logic generated from the first comparator comp1 and the output of the high logic generated from the second comparator comp2 are input to the first NOR gate NOR1 . This first NOR gate NOR1 generates an output of low logic because at least one of the three outputs supplied to the input terminals of the first NOR gate NOR1 is high logic.
The output of the low logic generated from the first NOR gate NOR1 and the output of the high logic generated from the above-described differential amplifier D-amp are supplied to the second NOR gate NOR2. This second NOR gate NOR2 generates an output of low logic because at least one of the two outputs supplied to the input terminals of the second NOR gate NOR2 is high logic.
The output of the row logic generated from this second NOR gate NOR2 is inverted through the invulner. That is, this inverter inv generates the output VO of the high logic (normal output). The output VO of the high logic output from this inverter inv corresponds to the difference voltage between the first differential voltage VP and the second differential voltage VN, Circuit is normally supplied. That is, the error determination unit ED determines that the first and second differential voltages VP and VN are normally supplied to the first and second differential lines DL1 and DL2, and the first differential voltage VP ) And the second differential voltage (VN) to the rear stage circuit normally.
2 (a), when the first differential voltage VP has a level lower than the reference voltage VREF and the second differential voltage VN has a level higher than the reference voltage VREF, A current flowing from the lower side to the upper side of the resistor Rt is generated. Also, the differential amplifier D-amp generates an output of low logic, a first comparator comp1 generates an output of high logic, a second comparator comp2 generates an output of low logic, The NOR gate NOR1 generates an output of low logic, the second NOR gate NOR2 generates an output of a high logic, and the inverter inv generates an output of a low logic. The output of the low logic output from this inverter inv corresponds to the difference voltage between the second differential voltage VN and the first differential voltage VP and the output of this low logic is normally supplied to the subsequent stage circuit.
Next, the operation of the differential signal receiving circuit when the first and second differential voltages VP and VN are all greater than the reference voltage VREF as shown in FIG. 2B will be described. For example, when the first differential voltage VP has a level higher than the reference voltage VREF and the second differential voltage VN has a level lower than the second differential voltage VN than the reference voltage VREF The operation of the differential signal receiving circuit of Fig.
The first differential voltage VP is supplied to the first differential line DL1 and the second differential voltage VN is supplied to the second differential line DL2. At this time, a current flowing through the termination resistor Rt is generated by the first differential voltage VP and the second differential voltage VN. This current has a direction from the top to the bottom of the terminating resistor Rt. Since the first and second pull-up resistors Rpu1 and Rpu2 have a resistance value significantly larger than the termination resistance Rt, the first and second pull-up resistors Rpu1 and Rpu2 are connected to the first and second differential lines Rpu1 and Rpu2 through the first and second pull- The current supplied to the first and second differential lines DL1 and DL2 is considerably smaller than the current supplied to the first and second differential lines DL1 and DL2 through the terminating resistor Rt. Therefore, the current supplied through the first and second pull-up resistors Rpu1 and Rpu2 can be ignored.
The differential amplifier D-amp amplifies and outputs the difference voltage between the first differential voltage VP and the second differential voltage VN. At this time, since the first differential voltage VP is larger than the second differential voltage VN, the output from the differential amplifier D-amp has high logic.
The pulse detector PD compares the pulse width of the output from the differential amplifier D-amp with the reference pulse width. At this time, since the output from the differential amplifier D-amp is generated based on the first and second differential voltages VP and VN in the pulse form as described above, the output from the differential amplifier D-amp Has a pulse width. Assuming that the reference pulse width is set to the same pulse width as the pulse widths of the first and second differential voltages VP and VN, the output from the differential amplifier D-amp has the same length as the reference pulse width Since the pulse width has a pulse width, the pulse detector PD generates an output of high logic.
The first comparator comp1 compares the first differential voltage VP with the reference voltage VREF, and generates an output in accordance with the comparison result. At this time, since the first differential voltage VP is larger than the reference voltage VREF, the first comparator comp1 generates an output of low logic.
The second comparator comp2 compares the second differential voltage VN with the reference voltage VREF, and generates an output according to the comparison result. At this time, since the second differential voltage VN is also larger than the reference voltage VREF, the second comparator comp2 also generates a low logic output.
The output of the high logic generated from the pulse detector PD, the output of the low logic generated from the first comparator comp1 and the output of the low logic generated from the second comparator comp2 are input to the first NOR gate NOR1 . This first NOR gate NOR1 generates an output of low logic because at least one of the three outputs supplied to the input terminals of the first NOR gate NOR1 is high logic.
The output of the low logic generated from the first NOR gate NOR1 and the output of the high logic generated from the above-described differential amplifier D-amp are supplied to the second NOR gate NOR2. This second NOR gate NOR2 generates an output of low logic because at least one of the two outputs supplied to the input terminals of the second NOR gate NOR2 is high logic.
The output of the row logic generated from this second NOR gate NOR2 is inverted through the invulner. That is, this inverter inv generates an output VO of high logic. The output VO of the high logic output from this inverter inv corresponds to the difference voltage between the first differential voltage VP and the second differential voltage VN, Circuit is normally supplied. That is, the error determination unit ED determines that the first and second differential voltages VP and VN are normally supplied to the first and second differential lines DL1 and DL2, and the first differential voltage VP ) And the second differential voltage VN to the subsequent stage circuit normally.
2 (b), when the second differential voltage VN has a level higher than the first differential voltage VP, a current flowing from the lower side to the upper side of the termination resistor Rt is generated. Also, the differential amplifier D-amp generates an output of low logic, a first comparator comp1 generates an output of low logic, a second comparator comp2 generates an output of low logic, The NOR gate NOR1 generates an output of low logic, the second NOR gate NOR2 generates an output of a high logic, and the inverter inv generates an output of a low logic. The output VO of the low logic output from this inverter inv corresponds to the difference voltage between the second differential voltage VN and the first differential voltage VP, Circuit is normally supplied.
2 (b), even if both the first and second differential voltages VP and VN are smaller than the reference voltage VREF, the error determination unit ED outputs the output from the differential amplifier D-amp Is allowed to be applied to the subsequent stage circuit.
Next, the operation of the differential signal receiving circuit in an abnormal situation in which the first and second differential lines DL1 and DL2 are opposed and floating will be described. That is, the operation of the differential signal receiving circuit in a situation where normal first and second differential voltages VP and VN are not supplied to the first and second differential lines DL1 and DL2 will be described.
When the first and second differential lines DL1 and DL2 are opened, the first differential line DL1 is maintained at a voltage substantially close to the power supply voltage VCC by the first pull-up resistor Rpu1, The second pull-up resistor DL2 is also held at a voltage substantially close to the power supply voltage VCC by the second pull-up resistor Rpu2. At this time, when the first pull-up resistor Rpu1 and the second pull-up resistor Rpu2 have the same resistance value, both the first differential line DL1 and the second differential line DL2 are maintained at the same voltage. Therefore, the differential amplifier D-amp does not generate an output. Accordingly, the pulse detector PD generates an output of low logic.
Further, since the voltages supplied to the first and second differential lines DL1 and DL2 are larger than the reference voltage VREF, the first and second comparators comp1 and comp2 all generate a low logic output.
Thereby, the output of the row logic generated from the pulse detector PD, the output of the row logic generated from the first comparator comp1, and the output of the row logic generated from the second comparator comp2 are supplied to the first NOR gate Gate NOR1 generates an output of high logic.
Accordingly, the second NOR gate NOR2 receiving the output of the high logic generated from the first NOR gate NOR1 generates the output of the low logic regardless of the output from the differential amplifier D-amp . The output of this row logic is changed to high logic via an inv (inv). In the state where the first and second differential lines DL1 and DL2 are open, the error determination unit ED controls the differential amplifier D-amp in order to prevent undesired output due to noise from the outside, (FS) of high logic is always generated regardless of the output from the high logic (FS), and the output (FS) of the high logic outputted at this time acts as a fail-safe signal. That is, the error prevention signal FS is supplied to the subsequent stage circuit so that the latter stage circuit does not operate anymore.
Since noises from the outside can be supplied to the first and second differential lines DL1 and DL2 which are open and thus in a floating state, the noise has a very short pulse width, and this noise causes the differential amplifier D -amp) generates an output, the pulse detector PD does not judge it as an output. That is, the pulse detector PD compares the pulse width of the output due to the noise with the reference pulse width, and the pulse width of the noise is necessarily smaller than the reference pulse width. Thus, even if the differential amplifier D-amp is operated due to noise, the pulse detector PD still generates an output of low logic.
Therefore, even if noises from the outside are applied to the first and second differential lines DL1 and DL2 while the first and second differential lines DL1 and DL2 are disconnected from the differential signal transmission circuit, ) Can stably block unwanted output generated from the differential amplifier (D-amp) from being transmitted to the receiving circuit due to such noise.
FIG. 3 is a simulation circuit diagram for confirming the operation of the differential signal receiving circuit according to the embodiment of the present invention, and FIG. 4 is a diagram showing input signals input to the simulation circuit of FIG. 3 and output signals of the simulation circuit diagram.
The configuration of FIG. 3 is substantially the same as the configuration shown in FIG. 3, three buffers BF1, BF2 and BF3 are added for stable simulation. The first buffer BF1 is divided into a first buffer BF1, a second buffer BF2 and a third buffer BF3. The first buffer BF1 is connected between the differential amplifier D-amp and the second NOR gate NOR2. And the second buffer BF2 is connected between the first comparator comp1 and the first NOR gate NOR1 and the third buffer BF3 is connected between the second comparator comp2 and the second negator And is connected between the logical sum gate NOR2.
Fig. 4 includes two kinds of signal waveforms. The signal waveforms shown on the upper side correspond to the signal waveforms shown in Fig. 3 (a), and the signal waveforms shown on the lower side correspond to the signal waveforms shown in Fig. 3 ≪ / RTI >
4, when the first and second differential voltages VP and VN swing with respect to the reference voltage VREF, or when the first and second differential voltages VP and VN swing based on the reference voltage VREF, It can be seen that the output from the error determination unit ED is normally generated even when the voltage VREF is larger than the voltage VREF.
On the other hand, the reference voltages VREF shown on the upper and lower sides in Fig. 4 are all 1.2 [V], and the common voltage VREF, which means the intermediate voltage between the first differential voltage VP and the second differential voltage VN, The voltage Vcom is 1.2 V and the common voltage Vcom, which means the intermediate voltage between the first differential voltage VP and the second differential voltage VN shown at the lower side, is 1.6 [V].
As described above, according to the present invention, the first and second differential voltages VP and VN are swung with reference to the reference voltage VREF, or are both greater than or equal to the reference voltage VREF The first and second differential voltages VP and VN are normally transmitted to the subsequent circuit even when both are small. When the first and second differential voltages VP and VN are not supplied, the output from the differential amplifier D-amp is supplied to the rear stage circuit in order to prevent an abnormal output due to noise from the outside prevent.
The differential signal receiving circuit according to the present invention can be used in an interface part between a timing controller and a data driver of various display devices (a liquid crystal display device, an organic light emitting display device, a plasma display device, etc.).
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.
VP: first differential voltage VP2: second differential voltage
DL1: first differential line DL2: second differential line
Rt: Termination resistance VCC: Power supply voltage
Rpu1: first pull-up resistor Rpu2: second pull-up resistor
Rpu: pull-up resistor Rpd: pull-down resistor
VREF: Reference voltage D-Amp: Differential amplifier
comp1: first comparator comp2: second comparator
PD: Pulse detection part NOR1: First NAND gate
NOR2: 2nd negation OR gate inv:
ED: error judgment unit OT: output terminal
VD: Voltage distribution circuit VO: Normal output
FS: error prevention signal
Claims (10)
A differential amplifier for amplifying and outputting a difference voltage between a voltage applied to the first differential line and a voltage applied to the second differential line;
A pulse detector for determining whether a pulse width of an output generated from the differential amplifier has a length equal to or longer than a preset reference pulse width and generating an output based on the determination result; And
And an error determination unit for allowing or blocking an output from the differential amplifier based on an output from the pulse detection unit.
When the pulse width of the output detected from the pulse detecting unit is smaller than the reference pulse width, the error judging unit interrupts the output from the differential amplifier; And,
And the error determination unit allows the output from the differential amplifier when the pulse width of the output detected from the pulse detection unit is equal to or larger than the reference pulse width.
The error judging unit judges,
A first pull-up resistor connected between the power supply for supplying the power supply voltage and the first differential line;
A second pull-up resistor connected between the power supply and the second differential line;
A first comparator for comparing a voltage from the first differential line with a preset reference voltage and generating an output based on the comparison result;
A second comparator for comparing the voltage from the second differential line with the reference voltage and generating an output based on the comparison result;
A first NAND gate for generating an output based on an output from the first comparator, an output from the second comparator, and an output from the pulse detector;
A second NOR gate for generating an output based on an output from the first NOR gate and an output from the differential amplifier; And
And a reverser for inverting the output from said second NOR gate.
The error determination unit further includes a voltage distribution circuit for generating the reference voltage;
Wherein the voltage divider circuit divides the power supply voltage from the power supply unit using a pull-up resistor and a pull-down resistor to generate the reference voltage.
At least one of the first and second pull-up resistors has a resistance value that is higher than the termination resistance;
The pull-up resistor having a higher resistance value than the pull-down resistor; And,
Wherein the power supply voltage is higher than the reference voltage.
Wherein the reference pulse width has a length equal to a pulse width of a first differential voltage supplied from the differential signal transfer circuit to the first differential line or a second differential voltage supplied from the differential signal transfer circuit to the second differential line And the pulse width of the pulse signal is equal to the pulse width of the pulse signal.
When the pulse width of the first differential voltage is different from the pulse width of the second differential voltage, the reference pulse width is equal to the pulse width of the differential voltage having the pulse width of the smaller one of the first and second differential voltages And outputs the differential signal.
A step of detecting an output from the differential amplifier;
Determining whether a pulse width of the detected output has a length equal to or longer than a preset reference pulse width;
And a step (C) of allowing or blocking an output from the differential amplifier according to a result of the determination.
In the step C,
Blocking the output from the differential amplifier when the pulse width of the detected output is smaller than the reference pulse width;
And allowing the output from the differential amplifier when the pulse width of the detected output is equal to or greater than the reference pulse width.
Wherein the reference pulse width has a length equal to a pulse width of a first differential voltage supplied from the differential signal transfer circuit to the first differential line or a second differential voltage supplied from the differential signal transfer circuit to the second differential line And a pulse width equal to the pulse width of the differential signal.
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| KR1020100138791A KR101706240B1 (en) | 2010-12-30 | 2010-12-30 | Differential receiver circuit and method for driving the same |
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| KR1020100138791A KR101706240B1 (en) | 2010-12-30 | 2010-12-30 | Differential receiver circuit and method for driving the same |
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| WO2024039185A1 (en) * | 2022-08-19 | 2024-02-22 | 삼성전자 주식회사 | Method for controlling fail-safe resistance connection to both ends of communication lines in differential voltage communication, and communication device that employs method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002335145A (en) | 2001-05-09 | 2002-11-22 | Hitachi Ltd | Hysteresis comparator circuit and inspection apparatus using the same |
| US20050200404A1 (en) | 2002-07-10 | 2005-09-15 | Derek Bernardon | Amplifier circuit |
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- 2010-12-30 KR KR1020100138791A patent/KR101706240B1/en active IP Right Grant
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002335145A (en) | 2001-05-09 | 2002-11-22 | Hitachi Ltd | Hysteresis comparator circuit and inspection apparatus using the same |
| US20050200404A1 (en) | 2002-07-10 | 2005-09-15 | Derek Bernardon | Amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20120076993A (en) | 2012-07-10 |
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