KR101703049B1 - PCB with embedded capacitor and method of manufacturing the same - Google Patents

Abstract

The present invention provides a method of manufacturing an embedded printed circuit board having a built-in capacitor according to an embodiment of the present invention. In the method of manufacturing an embedded printed circuit board, a carrier substrate including an insulating layer is provided. And first and second metal electrode patterns disposed adjacent to the carrier substrate and insulated from each other are formed. A dielectric material layer covering the first and second metal electrode patterns is laminated on the carrier substrate. The carrier substrate and the first and second metal electrode patterns are separated to form a capacitor structure including the first and second metal electrode patterns and the dielectric material layer. An interlayer insulating layer is laminated on both surfaces of the capacitor structure. And first and second vias electrically connected to the first and second metal electrode patterns are formed in the interlayer insulating layer. And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer is formed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board having a built-in capacitor,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a printed circuit board (PCB), and more particularly, to a printed circuit board having a built-in capacitor and a method of manufacturing the same.

With the miniaturization of electronic devices, electronic components are becoming more sophisticated and smaller. Due to the advancement of digital networks, portable information terminal devices such as mobile phones and portable computers are becoming more sophisticated and sophisticated, and various functions are being combined and integrated into one device.

As electronic devices are miniaturized and highly functionalized, the number of component elements to be mounted on a printed circuit board is greatly increased. On the other hand, the area of the substrate is not reduced. Rather, it is demanded to reduce the thickness of the existing printed circuit board and the thickness of the component element in accordance with the trend of downsizing described above.

Recently, as a method of manufacturing a printed circuit board to satisfy the above-mentioned requirements, an embedded printed circuit board technology in which a device chip or a circuit pattern is embedded in a printed circuit board has appeared. Embedded printed circuit board technology can be advantageous in reducing the thickness of the entire component by embedding the component chip or circuit pattern in the printed circuit board.

As an example of a manufacturing technique of such an embedded printed circuit board, there is a technique disclosed in Korean Patent Publication No. 2012-0070075.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a thin printed circuit board incorporating a capacitor element having a high capacitance value.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an embedded printed circuit board in which a capacitor having a high capacitance value is embedded in a printed circuit board having a small thickness.

The present invention provides a method of manufacturing an embedded printed circuit board having a built-in capacitor according to an aspect of the present invention. In the method of manufacturing an embedded printed circuit board, a carrier substrate including an insulating layer is provided. And first and second metal electrode patterns disposed adjacent to the carrier substrate and insulated from each other are formed. A dielectric material layer covering the first and second metal electrode patterns is laminated on the carrier substrate. The carrier substrate and the first and second metal electrode patterns are separated to form a capacitor structure including the first and second metal electrode patterns and the dielectric material layer. An interlayer insulating layer is laminated on both surfaces of the capacitor structure. First and second vias electrically connected to the first and second metal electrode patterns are formed in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively. And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer is formed.

The present invention also provides a method of manufacturing an embedded printed circuit board having a built-in capacitor according to another aspect. In the method of manufacturing the embedded printed circuit board, a preliminary structure having a dielectric material layer is prepared. The dielectric material layers are processed to form the first and second trench patterns in the form of the adjacently disposed or separate structures. First and second metal electrode patterns filling the trench pattern are formed to form a capacitor structure including the first and second metal electrode patterns and the dielectric material layer. An interlayer insulating layer is laminated on both surfaces of the capacitor structure. First and second vias electrically connected to the first and second metal electrode patterns are formed in the interlayer insulating layer, the interlayer insulating layer, and the dielectric material layer, respectively. And a circuit pattern layer connected to the first and second vias is formed on the interlayer insulating layer.

There is provided an embedded printed circuit board having an embedded capacitor according to another aspect. Wherein the embedded printed circuit board comprises at least one capacitor comprising first and second metal electrode patterns in the form of traces disposed adjacent to each other and electrically insulated from each other and a dielectric material layer between the first and second metal electrode patterns, structure; An interlayer dielectric layer deposited on the dielectric material layer of the capacitor structure; First and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively; And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer, respectively.

According to one embodiment, various types of capacitor structures can be fabricated first with a printed circuit board manufacturing method using a carrier substrate. Thereafter, a wiring is laminated on both surfaces of the capacitor structure by using a via and a circuit pattern layer by a plating method, whereby a printed circuit board having the capacitor structure built therein can be manufactured.

As a result, the area of the capacitor structure incorporated in the printed circuit board can be sufficiently secured, and sufficient capacitance can be ensured. In addition, a capacitor structure may be buried in a printed circuit board manufacturing process such as stacking an interlayer insulating layer and a circuit pattern layer on a capacitor structure. In the conventional method of manufacturing an embedded printed circuit board, it is possible to omit the process of forming the cavity in which the device is placed in the substrate, and to reduce the thickness of the embedded printed circuit board as a whole.

1 to 4 are sectional views schematically showing a method of manufacturing a capacitor structure of an embedded printed circuit board according to a first embodiment of the present invention.
5A to 5C are plan views schematically showing the shape of a metal electrode pattern of a capacitor structure manufactured according to an embodiment of the present invention.
6 to 8 are sectional views schematically showing a method of manufacturing a capacitor structure of an embedded printed circuit board according to a second embodiment of the present invention.
9 to 11 are sectional views schematically showing a method of manufacturing an embedded printed circuit board having an embedded capacitor according to an embodiment of the present invention.
12A through 12D are cross-sectional views schematically illustrating an embedded printed circuit board having embedded capacitors according to other embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the techniques disclosed in the present invention are not limited to the embodiments described herein but may be embodied in other forms. It should be understood, however, that the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements .

Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Further, in carrying out the method or the manufacturing method, the respective steps of the method may take place differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

As used herein, the term " top surface " or " bottom " of a substrate or chip is a relative concept observed at an observer's point of view. Therefore, either side of the substrate or a side of the chip may be referred to as an 'upper side' or 'lower side', and the other side may be referred to as 'lower side' or 'upper side' correspondingly. Likewise, in the present specification, the concept of 'upper', 'upper' or 'lower' and 'lower' can be used as a relative concept as well.

1 to 4 are sectional views schematically showing a method of manufacturing a capacitor structure of an embedded printed circuit board according to a first embodiment of the present invention.

Referring to FIG. 1, there is provided a carrier substrate 100 including an insulating layer 101 and a seed copper layer 105 for plating. The insulating layer 101 may include, for example, a resin such as epoxy. As another example, the insulating layer 101 may be a prepreg layer.

Referring to FIG. 2, first and second metal electrode patterns 110a and 110b, which are disposed adjacent to each other on the carrier substrate 100 and are insulated from each other, are formed. The first and second metal electrode patterns 110a and 110b may be formed in the form of a trace pattern arranged to be staggered from each other as shown in FIGS. 5A to 5C. The first and second metal electrode patterns 110a and 110b may function as first and second electrodes of a capacitor structure described later.

In one embodiment, the method of forming the first and second metal electrode patterns 110a and 110b includes a step of forming a copper plating pattern by an additive process using the seed copper layer 105 for plating Lt; / RTI > As an example, the method may include a semi-additive process (SAP).

In another embodiment, the first and second metal electrode patterns 110a and 110b may be formed by first forming a copper plating layer on the seed copper layer 105 for plating, the patterning may be performed by a subtractive process. The subtractive method includes a step of selectively etching the copper plating layer with an etching solution.

In some other embodiments, when the first and second metal electrode patterns 110a and 110b are formed by using the subtractive method, the plating seeds 110a and 110b are formed on the insulating layer 101 of the carrier substrate 100, The copper layer 105 may be omitted. That is, the copper plating layer may be directly formed on the insulating layer 101 by a plating method.

Referring to FIG. 3, a dielectric material layer 120 is formed on the carrier substrate 100 to cover the first and second metal electrode patterns 110a and 110b. Specifically, the present process can be carried out in various ways as follows.

In one embodiment, first, a film-shaped dielectric sheet having a predetermined dielectric constant is prepared. Next, the dielectric sheet is bonded to the metal electrode pattern so that the dielectric sheet seals the metal electrode pattern. Thereby, the dielectric material layer 120 can be laminated.

In another embodiment, a dielectric material having a predetermined dielectric constant and having fluidity is applied onto the carrier substrate. The applied dielectric material is then dried. At this time, the dielectric material may be applied, for example, in the form of liquid or paste. Thereby, the dielectric material layer 120 can be laminated.

After laminating the dielectric material layer 120 in accordance with the embodiments described above, a process may also be performed to further planarize the surface of the layer of dielectric material 120 deposited. The planarization process may be performed by a chemical etching method, a physico-chemical polishing method, a grinding method, or the like.

Referring to FIG. 4, the first and second metal electrode patterns 110a and 110b and the dielectric material layer 120 are formed by separating the carrier substrate 100 and the first and second metal electrode patterns 110a and 110b from each other, To form a capacitor structure (10).

 The step of separating the carrier substrate 100 and the first and second metal electrode patterns 110a and 110b from each other may be performed by forming a boundary surface between the insulating layer 101 of the carrier substrate 100 and the seed copper layer 105 for plating The intermediate structure in which the first and second metal electrode patterns 110a and 110b and the dielectric material layer 120 are laminated is formed on the seed copper layer 105 for plating first, The seed copper layer 105 may be removed.

5A to 5C are plan views schematically showing the shape of a metal electrode pattern of a capacitor structure manufactured according to an embodiment of the present invention. 5A to 5C, the metal electrode pattern includes a pair of first metal electrode patterns 110a and a second metal electrode pattern 110b physically separated from each other to be electrically isolated from each other, . The first metal electrode pattern 110a and the second metal electrode pattern 110b may be in the form of a ladder in which the metal pattern layers shown in FIG. 5A are staggered from each other, the metal pattern layers shown in FIGS. 5B and 5C, And may have a spiral shape arranged to be staggered from each other.

6 to 8 are sectional views schematically showing a method of manufacturing a capacitor structure of an embedded printed circuit board according to a second embodiment of the present invention. Referring to FIG. 6, a preliminary structure having a layer of dielectric material 620 is prepared. The preliminary structure may have a sheet shape of a predetermined thickness made of the dielectric material layer 620.

Referring to FIG. 7, a dielectric material layer 620 is formed to form first and second trench patterns 310a and 310b, which are disposed adjacent to each other, but separated from each other. The first and second trench patterns 310a and 310b may be formed in regions where the first and second metal electrode patterns 110a and 110b are to be formed, respectively, in FIGS. 5A to 5C. Accordingly, the first and second trench patterns 310a and 310b may be formed in the form of a trace pattern, but may be physically separated from each other.

At this time, the method of processing the dielectric material layer 620 can be performed by applying at least one method selected from mechanical drilling, laser drilling, chemical etching, and plasma etching, for example.

Referring to FIG. 8, first and second metal electrode patterns 110a and 110b filling the first and second trench patterns 310a and 310b are formed. The first and second metal electrode patterns 110a and 110b may be formed using at least one method selected from a plating method, a printing method, and a chemical vapor deposition method. Thus, the capacitor structure 10 including the first and second metal electrode patterns 110a and 110b and the dielectric material layer 120 can be formed.

9 to 11 are sectional views schematically showing a method of manufacturing an embedded printed circuit board having an embedded capacitor according to an embodiment of the present invention. Referring to Fig. 9, a capacitor structure 10 manufactured according to the first embodiment described above with reference to Figs. 1 to 4 and the second embodiment described above with reference to Figs. 6 to 8 is prepared. Then, an interlayer insulating layer 910 is laminated on both surfaces of the capacitor structure 10. Further, a seed copper layer 920 for plating is laminated on the interlayer insulating layer 910.

10, first and second metal electrode patterns 110a and 110b are electrically connected to the first and second metal electrode patterns 110a and 110b in the interlayer insulating layer 910 or the interlayer insulating layer 910 and the dielectric material layer 120, respectively. Thereby forming second vias 931a and 931b. Next, first and second circuit pattern layers 932a and 932b are formed on the interlayer insulating layer 910 so as to be connected to the first and second vias, respectively.

The step of forming the first and second vias 931a and 931b and the first and second circuit pattern layers 932a and 932b may include forming an interlayer insulating layer 910 or an interlayer insulating layer 910 and a dielectric material layer 120 Forming a copper plating pattern 932, 932a, 932b disposed on the interlayer insulating layer 910 by patterning copper plating layers 931a, 931b filling the via holes using a plating method; Lt; / RTI > Portions 932a and 932b of the copper plating pattern may be connected to the first and second vias 931a and 931b. The remaining portion 932 can constitute the circuit wiring on the interlayer insulating layer 930. [

The process of forming the copper plating layers 931a and 931b and the copper plating patterns 932 and 932a and 932b may be performed using a well-known SAP (Semi-Additive Process) or MSAP (Modified Semi-Additive Process) .

Referring to FIG. 11, a solder resist layer 940 selectively exposing the first and second circuit pattern layers 932a and 932b is formed on the interlayer insulating layer 910. The portions of the first and second circuit pattern layers 932a and 932b exposed by the solder resist layer 940 can function as connection pads connected to external devices.

Through the above-described processes, an embedded printed circuit board having embedded capacitors according to an embodiment of the present invention can be manufactured.

According to one embodiment of the present invention, various types of capacitor structures can be manufactured first with a printed circuit board manufacturing method using a carrier substrate. Thereafter, a wiring is laminated on both surfaces of the capacitor structure by using a via and a circuit pattern layer by a plating method, whereby a printed circuit board having the capacitor structure built therein can be manufactured.

As a result, the area of the capacitor structure incorporated in the printed circuit board can be sufficiently secured, and sufficient capacitance can be ensured. In addition, a capacitor structure may be buried in a printed circuit board manufacturing process such as stacking an interlayer insulating layer and a circuit pattern layer on a capacitor structure. In the conventional method of manufacturing an embedded printed circuit board, it is possible to omit the process of forming the cavity in which the device is placed in the substrate, and to reduce the thickness of the embedded printed circuit board as a whole.

Meanwhile, the embedded printed circuit board manufactured by the manufacturing method according to the embodiment of the present invention may include at least one capacitor structure 10, as shown in FIG. The capacitor structure 10 includes first and second metal electrode patterns 110a and 110b in the form of traces disposed adjacent to each other and electrically insulated from each other and a dielectric material 110a and 110b filling between the first and second metal electrode patterns 110a and 110b. And a material layer 120. At this time, the first and second metal electrode patterns 110a and 110b may be disposed on the same plane.

The embedded printed circuit board may further include an interlayer insulating layer 910 laminated on the dielectric material layer 120 of the capacitor structure 10 and a first and a second metal electrode pattern in the interlayer insulating layer 910, First and second circuit pattern layers 932a and 932b connected to the first and second vias 931a and 931b on the interlayer dielectric layer 910. The first and second circuit pattern layers 932a and 932b are connected to the first and second via patterns 931a and 931b, .

12A through 12D are cross-sectional views schematically illustrating an embedded printed circuit board having embedded capacitors according to other embodiments of the present invention.

The embodiment of FIG. 12A is different from the embedded printed circuit board of the embodiment disclosed in FIG. 11 in that, in the capacitor structure 10, pairs of first and second metal electrode patterns in the form of traces are arranged in a multi- . At this time, a pair of the first and second metal electrode patterns of the multiple layers may be insulated by the dielectric material layer 120.

On the other hand, the first capacitor element constituted by the first metal electrode pattern 110a and the second metal electrode pattern 110b and the first capacitor element constituted by the first metal electrode pattern 111a and the second metal electrode pattern 111b The second capacitor element is connected in parallel by the first and second connection vias 112a and 112b. Thus, the capacitance of the built-in capacitor can be improved.

The embodiment of FIG. 12B further includes a first and a second internal electrode pattern 1210a. 1210b disposed on the dielectric material layer 120, as opposed to the embedded printed circuit board of the embodiment disclosed in FIG. It is possible to provide a differentiating point.

The first and second internal electrode patterns 1210a and 1210b may be disposed so as to be buried by the interlayer insulating layer 910 on the dielectric material layer 120. [ Also, the first internal electrode pattern 1210a may be electrically connected to the first via 931a and the first metal electrode pattern 110a. At this time, the first connection via 1211a can electrically connect the first metal electrode pattern 110a and the first internal electrode pattern 1210a. Meanwhile, the second internal electrode pattern 1210b may be electrically connected to the second via 931b and the second metal electrode pattern 110b. At this time, the second connection via 1211b may electrically connect the second metal electrode pattern 11b and the second internal electrode pattern 1210b.

The first and second internal electrode patterns 1210a and 1210b have an effect of reducing the electrical resistance inside the circuit wiring through which current flows.

The embodiment of FIG. 12C is different from the embedded printed circuit board of the embodiment shown in FIG. 11 in that the first and second electrode patterns 110a and 110b are arranged in a zigzag form on different planes.

The embodiment of Figure 12D is a stacked structure of a plurality of dielectric layers 212 and 214 that are different from each other in the dielectric material layer 210 as compared to the embedded printed circuit board of the embodiment disclosed in Figure 11, And 214 are arranged to cover different portions of the first and second electrode patterns 110a and 110b in the height direction.

In this embodiment, two capacitors having different capacitances may be connected in parallel. Thus, the capacitance of the capacitor structure can be increased.

 While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

100: carrier substrate, 101: insulating layer, 105: seed copper layer for plating,
110a: a first metal electrode pattern, 110b: a second metal electrode pattern,
120 620: dielectric material layer, 10: capacitor structure,
210: dielectric material layer, 212 214: plural dielectric layers,
310a: first trench pattern, 310b: second trench pattern,
910: interlayer insulating layer, 920: seed copper layer for plating,
931a: first via, 931b: second via,
932, 932a and 932b: a circuit pattern layer,
940: solder resist layer,
1210a: first internal electrode pattern, 1210b: second internal electrode pattern,
1211a: first connection via, 1211b: second connection via.

Claims (20)

(a) providing a carrier substrate comprising an insulating layer;
(b) forming first and second metal electrode patterns disposed adjacent to and insulated from each other on the carrier substrate;
(c) laminating a dielectric material layer covering the first and second metal electrode patterns on the carrier substrate;
(d) separating the carrier substrate and the first and second metal electrode patterns to form a capacitor structure including the first and second metal electrode patterns and the dielectric material layer;
(e) laminating an interlayer dielectric on both surfaces of the capacitor structure;
(f) forming first and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively;
(g) forming a circuit pattern layer on the interlayer dielectric layer, the circuit pattern layer being connected to the first and second vias, respectively
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
The first and second metal electrode patterns function as first and second electrodes of the capacitor structure,
The first and second metal electrode patterns are formed in the form of a trace pattern
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
In step (a)
Wherein the carrier substrate comprises a seed copper layer for plating laminated on the insulating layer
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method of claim 3,
(b)
And a step of forming a copper plating pattern by an additive method using the seed copper layer for plating
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
(b)
(b1) forming a copper plating layer on the insulating layer; And
(b2) patterning the copper plating layer by a subtractive method
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
(c)
Preparing a dielectric sheet in the form of a film; And
And bonding the dielectric sheet to the metal electrode pattern so that the dielectric sheet seals the metal electrode pattern
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
(c)
Applying a flowable dielectric material onto the carrier substrate; And
And drying said dielectric material
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
(h) forming a solder resist layer selectively exposing the circuit pattern layer on the interlayer insulating layer
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
(a) preparing a preform having a dielectric material layer;
(b) fabricating the dielectric material layer to form first and second trench patterns adjacent to each other or separated from each other;
(c) forming first and second metal electrode patterns filling the trench pattern to form a capacitor structure including the first and second metal electrode patterns and the dielectric material layer;
(d) laminating an interlayer insulating layer on both surfaces of the capacitor structure;
(e) forming first and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively;
(f) forming a circuit pattern layer on the interlayer dielectric layer, the circuit pattern layer being connected to the first and second vias, respectively
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
10. The method of claim 9,
The first and second metal electrode patterns function as first and second electrodes of the capacitor structure,
The first and second metal electrode patterns are formed in the form of a trace pattern
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
10. The method of claim 9,
The method of processing the dielectric material layer in step (b) may be performed by applying at least one method selected from mechanical drilling, laser drilling, chemical etching, and plasma etching
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
10. The method of claim 9,
(c)
A plating method, a printing method, and a chemical vapor deposition method.
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
The method according to claim 1,
(g) forming a solder resist layer selectively exposing the circuit pattern layer
A method of manufacturing an embedded printed circuit board having an embedded capacitor.
delete delete delete At least one capacitor structure including first and second metal electrode patterns in the form of traces disposed adjacent to each other and electrically insulated from each other, and a dielectric material layer filling between the first and second metal electrode patterns;
An interlayer dielectric layer deposited on the dielectric material layer of the capacitor structure;
First and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively; And
And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer,
Wherein the capacitor structure includes a plurality of pairs of the first and second metal electrode patterns in the trace shape,
And the pair of the first and second metal electrode patterns of the multiple layers are insulated by the dielectric material layer
An embedded printed circuit board having an embedded capacitor.
At least one capacitor structure including first and second metal electrode patterns in the form of traces disposed adjacent to each other and electrically insulated from each other, and a dielectric material layer filling between the first and second metal electrode patterns;
An interlayer dielectric layer deposited on the dielectric material layer of the capacitor structure;
First and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively; And
And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer,
A dielectric layer disposed on the dielectric material layer so as to be buried by the interlayer dielectric layer,
And an inner electrode pattern electrically connected to the first metal electrode pattern and the first via or electrically connected to the second metal electrode pattern and the second via,
An embedded printed circuit board having an embedded capacitor.
At least one capacitor structure comprising first and second metal electrode patterns in the form of traces disposed adjacent to each other and electrically insulated from each other, and a dielectric material layer filling between the first and second metal electrode patterns;
An interlayer dielectric layer deposited on the dielectric material layer of the capacitor structure;
First and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively; And
And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer,
The first and second metal electrode patterns are arranged in a zigzag pattern on different planes
An embedded printed circuit board having an embedded capacitor.
At least one capacitor structure comprising first and second metal electrode patterns in the form of traces disposed adjacent to each other and electrically insulated from each other, and a dielectric material layer filling between the first and second metal electrode patterns;
An interlayer dielectric layer deposited on the dielectric material layer of the capacitor structure;
First and second vias electrically connected to the first and second metal electrode patterns in the interlayer insulating layer or the interlayer insulating layer and the dielectric material layer, respectively; And
And a circuit pattern layer connected to the first and second vias on the interlayer insulating layer,
Wherein the dielectric material layer is a stacked structure of a plurality of dielectric layers different from each other,
The plurality of different dielectric layers are arranged to cover different portions of the first and second metal electrode patterns in the height direction
An embedded printed circuit board having an embedded capacitor.

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