KR101698198B1 - Analog decoder and clock generator for passive tag, and method thereof - Google Patents

Analog decoder and clock generator for passive tag, and method thereof Download PDF

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KR101698198B1
KR101698198B1 KR1020150132696A KR20150132696A KR101698198B1 KR 101698198 B1 KR101698198 B1 KR 101698198B1 KR 1020150132696 A KR1020150132696 A KR 1020150132696A KR 20150132696 A KR20150132696 A KR 20150132696A KR 101698198 B1 KR101698198 B1 KR 101698198B1
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data
process environment
value
voltage
tari
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KR1020150132696A
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Korean (ko)
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이종욱
이재훈
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경희대학교 산학협력단
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
    • G06K7/10009—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation sensing by radiation using wavelengths larger than 0.1 mm, e.g. radio-waves or microwaves

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Abstract

The present invention relates to an analog decoder of a passive tag. The analog decoder includes: a process corner sensing circuit which detects a process corner in which a tag is fabricated, by comparing the data-0 interval length of the pulse interval encoding (PIE) symbol calculated by using a ring oscillator with the data-0 length (Tari value) of the PIE symbol, and generates a control signal based on the detected process corner; a voltage generator which selects a capacitor to be charged based on the control signal, charges the capacitor according to the signal of the PIE symbol, and outputs a charged capacitor voltage; and a voltage comparator which compares a reference voltage with the output voltage of the voltage generator and determines the data of the PIE symbol. So, the data can be determined regardless of a corner deviation.

Description

ANALOG DECODER AND CLOCK GENERATOR FOR PASSIVE TAG, AND METHOD THEREOF BACKGROUND OF THE INVENTION < RTI ID = 0.0 > [0001] <

The present invention relates to a passive tag.

The passive tag generates its own power without a battery or an external power source, and thus has a semi-permanent lifetime. On the other hand, since the passive tag uses its own power source, a low power chip design is required and a circuit design is required to realize a stable operation in a power-free environment. The digital control circuit, which is a sub-block of the tag chip, is operated by a clock generator that generates a certain frequency according to the international standard EPC Class-1 Generation-2 (EPC C1G2). In order to communicate without errors, the clock generator must generate a constant frequency within ± 4% of the error range from the tag backscattering frequency to the reader in accordance with the EPC C1G2 standard. In general, resistor trimming can be used to obtain the frequency within the error range, but it is difficult to apply when considering the price of the tag chip (10 cents). Therefore, there is a need for a method to generate the required frequency in the EPC C1G2 using the self-calibration process in the tag chip. Because the passive tag chip can not sustain its own reference voltage or frequency source, it must perform its own frequency correction through the signal received from the reader.

The reader modulates the pulse interval encoding (PIE) signal at the 900 MHz band frequency with the tag. The tag extracts a PIE symbol through demodulation of the signal (downlink) transmitted from the reader. The PIE decoder, which is a sub-block of the tag chip, decodes the PIE symbol to determine binary data.

The clock generator performs self-frequency correction using the data determined by the PIE decoder. The digital decoder consumes a large amount of power because it discriminates data using a value obtained by counting a data period included in the PIE symbol with a clock having a high frequency of several MHz. Furthermore, since the digital decoder operates with a clock within an error range, there is a problem that the digital decoder can not be used before the clock generator is stabilized in the tag chip without power source. An analog decoder that does not use a clock can be used, but the analog decoder has a problem that a data discrimination error may occur due to a process variation occurring in a chip manufacturing process.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an analog decoder for discriminating data regardless of a process deviation through a process corner sensing circuit of a semiconductor manufacturing process. Another object of the present invention is to provide a clock generator that performs self-frequency correction using discrimination data of an analog decoder.

As an analog decoder of a passive tag according to an embodiment of the present invention, a difference between a data-0 section length of a PIE (pulse interval encoding) symbol calculated using a ring oscillator and a data-0 length (Tari value) of the PIE symbol A process environment sensing circuit for sensing a process environment in which the tag is fabricated and generating a control signal based on the sensed process environment, a capacitor to be charged based on the control signal, A voltage generator for charging the capacitor and outputting the charged capacitor voltage, and a voltage comparator for comparing the reference voltage with the output voltage of the voltage generator to discriminate the data of the PIE symbol.

Wherein the process environment sensing circuit calculates a first value for each process environment in which the data-0 length is virtually counted using the frequency of each ring oscillator in the process environment, And a second value obtained by counting the length of the ring oscillator, and comparing the first value with the second value to detect a process environment of the ring oscillator, wherein the data-0 length is 6.25us, 12.5us, 25us It may be any one value.

Wherein the voltage generator includes a plurality of capacitors configured to operate in accordance with a process environment and selects a capacitor to be charged among the plurality of capacitors based on the control signal, the plurality of capacitors having different capacitances, Can be determined in view of the process variation of the process environment.

The voltage generator may determine the capacitance of each of the plurality of capacitors so that the output voltage by the data-1 signal is larger than the output voltage by the data-0 signal even if the process environment is changed.

The voltage generator includes a switch for controlling the charging of each of the plurality of capacitors, and can control on / off of the switch based on the control signal.

The voltage generator may include a transistor circuit for varying the amount of current flowing to the capacitor according to a data-0 length of the PIE symbol.

Wherein the process environment sensing circuit receives the value calculated by the ring oscillator and the data-0 length from the clock generator of the tag and the data-0 length is 6.25us, 12.5us, 25us Can be one value.

The voltage comparator may transmit the data discrimination result of the PIE symbol to the clock generator of the tag.

A method of operating an analog decoder included in a passive tag according to another embodiment of the present invention includes detecting a process environment by comparing a count value obtained by calculating a data-0 interval of a PIE (pulse interval encoding) symbol with a ring oscillator, Selecting a capacitor corresponding to the sensed process environment from among a plurality of capacitors configured to operate in accordance with the PIE symbol, a step, and a process environment, charging the selected capacitor according to the data signal of the PIE symbol, And comparing the voltage to determine the value of the data signal.

The reference value may be a count value of Tari calculated using the frequency of the ring oscillator depending on the process environment, and the Tari may be a value of 6.25us, 12.5us, or 25us.

Wherein the step of detecting the process environment comprises the steps of: detecting a Tari of the PIE symbol; counting a Tari detected using the frequency of the ring oscillator in accordance with the process environment to calculate a reference count value for each process environment; And determining a process environment by comparing the count value calculated by the process environment with the reference count value by the process environment.

The plurality of capacitors have different capacitances, and each capacitance can be determined in consideration of a process variation of a set process environment.

The operation method may further include transmitting the determined value to a clock generator.

The clock generator of the passive tag according to another embodiment of the present invention is a clock generator of a passive tag, comprising: a reference count value storing a first reference value obtained by counting a first data length at a target frequency and a second reference value obtained by counting a second data length at the target frequency A control unit for receiving a reference value corresponding to input data from the reference count value management unit and comparing the input reference value with a count value counted by the frequency of the oscillator to control the frequency of the oscillator to be lowered or increased And the reference count value management unit may transmit either the first reference value or the second reference value to the circuit unit based on the discrimination data of the input data.

The discrimination data of the input data is transmitted from a decoder, and the decoder charges the capacitor on the basis of the input data and discriminates the input data based on the charging voltage of the capacitor.

The circuit unit may calculate the first data length and the second data length using a sampling oscillator in a preamble period of the input signal and stop the operation of the sampling oscillator when a data interval of the input signal starts.

According to the embodiment of the present invention, the analog decoder senses the process environment and compensates for the process deviation, thereby outputting a constant voltage regardless of the process deviation. Therefore, according to the embodiment of the present invention, it is possible to reduce a discrimination error due to a process deviation even if an analog decoder is used.

According to the embodiment of the present invention, since an analog decoder is used, power consumption is reduced as compared with a digital decoder which discriminates data using a clock.

According to the embodiment of the present invention, the clock generator has the effect of reducing the frequency error of the frequency clock required by the EPC C1G2 standard using the discrimination data of the analog decoder.

1 is a diagram illustrating a structure of a tag according to an embodiment of the present invention.
2 is a block diagram of a tag chip according to an embodiment of the present invention.
3 is a diagram showing PIE symbols.
4 is a block diagram of a PIE decoder according to an embodiment of the present invention.
5 is an illustration of a circuit diagram of a voltage generator of a PIE decoder according to an embodiment of the present invention.
FIG. 6 is a graph comparing a voltage generator of a PIE decoder according to an embodiment of the present invention with a conventional output voltage when Tari is 6.25 us.
FIG. 7 is a diagram comparing a voltage generator of a PIE decoder according to an embodiment of the present invention with a conventional output voltage when Tari is 12.5 us.
8 is a graph comparing the output voltage of the prior art with the voltage generator of the PIE decoder according to an embodiment of the present invention when Tari is 25 us.
9 is a diagram comparing the output voltage of the PIE decoder and the output voltage of the prior art according to an embodiment of the present invention.
10 is a diagram comparing a decoding margin of a PIE decoder and a decoding margin of a conventional art according to an embodiment of the present invention.
11 to 14 are diagrams illustrating self-frequency correction of a clock generator according to an embodiment of the present invention.
15 is a diagram for explaining self-frequency correction results of a clock generator according to an embodiment of the present invention.
16 is a flowchart illustrating a method of operating a PIE decoder according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise. Also, the terms " part, "" module," and " module ", etc. in the specification mean a unit for processing at least one function or operation and may be implemented by hardware or software or a combination of hardware and software have.

FIG. 1 is a diagram illustrating a structure of a tag according to an embodiment of the present invention. FIG. 2 is a block diagram of a tag chip according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a PIE symbol.

Referring to FIG. 1, the RFID tag 10 includes an antenna 11 for transmitting and receiving a radio wave signal, and a tag chip 13 for storing information on objects and processing a communication function. The RFID tag 10 may be designed to vary in frequency, for example, to use frequencies in the vicinity of UHF 900 MHz.

The tag chip 13 is a passive tag that does not have its own power source and may be an analog circuit such as a rectifier, a bandgap, a regulator, a low voltage detector, a power-on-reset (POR), a demodulator, a modulator, A clock generator for providing a clock to the digital control circuit, a memory, and the like.

Referring to FIG. 2, the tag chip 13 includes a digital control circuit, a memory, and an analog circuit for receiving and processing the RF signal.

The analog circuit may include a demodulator and a modulator, such as a rectifier, a bandgap, a regulator, a low voltage detector, a power-on-reset (POR) The tag chip 13 includes an analog decoder 100 and a clock generator 200.

The analog decoder 100 decodes a pulse interval encoding (PIE) symbol and is called a PIE decoder in the future. The PIE decoder 100 determines the data to be 0 or 1 based on the capacitor voltage charged by the signal of the PIE symbol. The PIE decoder 100 includes a process environment sensing circuit that senses the process environment in which the tag chip is fabricated and selects the charge capacitor according to the process environment, which will be described in detail below.

The clock generator 200 provides a clock (CLK) to the digital control circuit. The clock generator 200 must generate a clock at a constant frequency so that the digital control circuit operates without error. For this purpose, the clock generator 200 performs its own frequency correction until a clock of a desired frequency (1.92 MHz) is obtained using the received PIE symbol before the digital control circuit operates. The clock generator 200 adjusts the current frequency while comparing the count value of the input data counted at the current frequency with the reference count value. At this time, the reference count value is selected as the reference count value for data-0 or the reference count value for data-1 by the discrimination data (0 or 1) of PIE decoder 100.

The PIE symbol will be described below.

The passive tag follows the EPC C1G2 standard and compatible version for data exchange with the reader. According to the EPC C1G2 standard, the PIE symbol as shown in FIG. 3 is transmitted from the reader to the tag.

The downlink PIE symbol includes a preamble section and a data section. The PIE symbol distinguishes between 0 and 1 according to the length of the high level. The length of the low level is constant.

The preamble section includes a delimiter section, a data-0 section (Tari), a reader-to-tag calibration (RTcal) for reader-to-tag calibration, a tag- to-Reader calibration, TRcal).

The delimiter interval is a constant length (12.5us5%), which indicates the start of the PIE symbol.

The data-0 period (Tari) represents the length (pulse width) of the data-0. Tari has one of the following values: 6.25us, 12.5us, and 25us.

The RTcal interval has a sum length [(2 + x) Tari] of data-0 (Tari) and data-1 [(1 + x) Tari]. Where the value of x has a value between 0.5 and 1.0 in EPC C1G2.

The TRcal interval is a parameter for determining the backscattering modulation frequency when transmitting data from the tag to the reader.

The data interval is a data chain in which data-0 and data-1 are randomly contiguous, data-0 is logically determined as 0 (low), and data-1 is logically determined as 1 (high).

The PIE symbol-modulated downlink RF signal is passed through a rectifier to a demodulator. The demodulator demodulates the carrier modulated at a transmission frequency (e.g., around 900 MHz) to extract the PIE symbol.

The PIE decoder 100 decodes the data (DATA) section of the PIE symbol to determine 0 and 1.

The PIE decoder 100 decodes the preamble period and obtains information that can distinguish between data-0 (Tari) and data-1 [(1 + x) Tari]. Since the high-level lengths of data-0 and data-1 are different, the capacitor voltage charged by the data-0 and data-1 signals is different. The PIE decoder 100 compares the output voltage by the capacitor voltage with the reference voltage to determine 0 and 1. In an ordinary analog decoder, the ON time of the transistor may be varied according to the process variation, and the capacitor charging voltage may vary, resulting in a large number of discrimination errors. Next, the PIE decoder 100 which is robust to process variations using the process environment sensing circuit will be described.

4 is a block diagram of a PIE decoder according to an embodiment of the present invention.

Referring to FIG. 4, the PIE decoder 100 includes a process environment sensing circuit 110, a voltage generator 130, and a voltage comparator 150. Although all of the configurations of the process environment sensing circuit 110 are described as being included in the PIE decoder 100 for the purpose of explanation, the data used to determine the process environment in the process environment sensing circuit 110 (for example, Ntick , Tari) may be designed to receive input from another block (e.g., a clock generator).

The process environment sensing circuit 110 senses a process corner where the tag chip is manufactured. The process environment sensing circuit 110 outputs control signals (for example, FF_cont, TT_cont, SS_cont) so that a capacitor corresponding to the sensed process environment among the plurality of capacitors implemented in the voltage generator 130 is charged. The control signal controls on / off of the switch connected to the capacitor. The process environment sensing circuit 110 for sensing the process environment can be designed in various ways.

The process environment sensing circuit 110 utilizes the output frequency of a ring oscillator that oscillates at a relatively high frequency to cause a process variation in accordance with the process environment. The process environment detection circuit 110 detects the process environment by classifying the frequency of a ring oscillator (hereinafter referred to as a sampling VCO) that changes according to the process environment into three or more.

In general, the process environment can be represented using two alphabets. The first alphabet is an N-channel MOSFET (NMOS) corner and the second alphabet represents a P-channel MOSFET (PMOS) corner. (Slow-slow), TT (typical-typical), and FF (high-speed), depending on the mobility of electrons and holes. (fast-fast). In the present invention, only three representative process environments (SS, TT, FF) are shown, but more various process environments can be considered.

The process environment sensing circuit 110 calculates the count value Ntick corresponding to the data-0 (Tari) period of the PIE symbol at the frequency of the sampling VCO. When the rise-edge detector 111 detects the pulse width (

Figure 112015091295242-pat00001
And counts the number of clocks (count value, Ntick) at which the binary counter 112 counts to the frequency of the sampling VCO during the pulse width. Referring to Table 1, the frequency deviation of the sampling VCO occurs according to the process environment (SS, TT, FF). If the count values (Ntick) calculated according to the Tari and the process environment do not overlap, the three process environments can be discriminated based on the count value even if the process environment changes to SS, TT, and FF. For example, for Tari = 6.25us, the value counted in the FF process is 26, and for Tari = 12.5us, the value counted in the SS process is 30. That is, even if the process is changed, the value counted from a single Tari value does not overlap with the value counted in another process.

process
corner 샘플 주파수 Ntick
Tari = 6.25us Ntick
Tari = 6.25us Ntick
Tari = 25us SS 1.21MHz 15 30 60 TT 1.54 MHz 19 38 77 FF 2.09MHz 26 52 105

The Tari value output from the Tari detector 113 is input to the two muxes 114 and 115, respectively. The MUX1 114 stores a reference count value for determining the process environment of the SS and the TT. In Table 1, values between SS and TT, for example, 17 when Tari = 6.25us, 34 when Tari = 12.5us, and 68 when Tari = 25us are pre-calculated and stored, respectively.

The MUX2 115 stores a reference count value for determining the process environment of the TT and the FF. In Table 1, values between TT and FF, for example, 23 when Tari = 6.25us, 45 when Tari = 12.5us, and 90 when Tari = 25us are pre-calculated and stored, respectively. The reference count value for discriminating the process environment output from the MUX1 114 and the MUX2 115 is a value obtained by counting the data-0 using the sampling VCO and a digital comparator, (116, 117). The values output from the two digital comparators 116 and 117 are input to the process environment determination logic gate 118.

The process environment determination logic gate 118 is comprised of a plurality of logic gates according to the process environment. The process environment determination logic gate 118 may be configured with three logic gates and the three logic gates are configured to correspond to one of the three process environments (SS, TT, FF) according to the values output from the two digital comparators . The process environment determination logic gate 118 outputs a process environment control signal according to the values output from the two digital comparators. The process environment control signal may be one of the SS control signal SS_cont, the TT control signal TT_cont, and the FF control signal FF_cont . For example, when Tari = 6.25us and the process environment is SS, the value output from the Tari detector 113 is input to the mux 114,115. The MUX1 114 outputs a reference count value 17 for discriminating SS and TT corresponding to the stored Tari = 6.25us. The MUX2 115 outputs a reference count value 23 for discriminating TT and FF. (Ntick) 15, which is the count value of the data-0 using the sampling VCO, and MUX1 114 Since the value obtained by counting the data-0 is smaller than the reference count value 17, the output of the digital comparator 116 is zero. Since the value obtained by counting the data-0 is smaller than the reference count value 23 output from the MUX2 115, the output of the digital comparator 117 is also zero. This output is applied to the input of each logic gate that outputs the SS control signal SS_cont, the TT control signal TT_cont, and the FF control signal. The SS control signal unit is composed of a NOR gate. When the input signal is 0, the SS control signal unit outputs 1 to control the voltage generator 130. The TT control signal section is an AND gate composed of one inverting input and outputs 0 when an input of 0 is applied. The FF control signal part is supplied with an input of 0 to the AND gate and outputs 0.

The voltage generator 130 receives the Tari value output from the Tari detector 113, the process environment control signal output from the process environment determination logic gate 118, and the PIE symbol.

The voltage generator 130 charges and discharges the capacitor according to the signal of the PIE symbol to output a voltage corresponding to the PIE symbol. At this time, the voltage generator 130 controls the switch according to the Tari value and the process environment control signal to control the amount of current to be charged and the capacitance of the capacitor. Accordingly, even if a process variation occurs according to the process environment, the voltage generator 130 selects a capacitor to be charged adaptively to the process environment, and as a result, outputs a constant voltage.

The voltage comparator 150 compares the reference voltage with the output voltage of the voltage generator 130 and outputs discrimination data (0 or 1). At this time, the discrimination data is used by the clock generator 200 to select the reference count value N0 ref_freq of the data-0 and the reference count value N1 ref_freq of the data-1. In this case, the discrimination data may be called Ni (i is 0 or 1) selection value.

5 is an illustration of a circuit diagram of a voltage generator of a PIE decoder according to an embodiment of the present invention.

Referring to FIG. 5, the voltage generator 130 is an adaptive PIE voltage generator that generates a voltage for a PIE symbol in accordance with a process environment. The voltage generator 130 receives a Tari value, a process environment control signal, and a PIE symbol.

The voltage generator 130 may be designed in various ways and may include a plurality of transistors M1, M2, M3, M4, M5, M6 and a plurality of capacitors C1, C2, C3, A plurality of switches Tari_S1, Tari_S2, and Tari_S3 that are turned on / off by a process environment control signal and a plurality of switches SS_S1, TT_S2, and FF_S3 that are turned on / off in response to a process environment control signal.

When the inverted signal (/ PIE_SIG) of the PIE symbol is input to the gate of the M1 transistor and the M1 transistor is turned on by / PIE_SIG, the M1 transistor and the C1 capacitor are connected so that the C1 capacitor is charged by the current flowing through the M1 transistor. When the M1 transistor is turned off by / PIE_SIG, a transistor for discharging the C1 capacitor is added.

The C1 capacitor is connected to the gate of the M2 transistor such that the M2 transistor is driven by the voltage of the C1 capacitor. When the C1 capacitor is charged, the M2 transistor is turned on and the M3 transistor is connected to the M2 transistor so that the current (I total ) of the M2 transistor flows to the M3 transistor.

On the other hand, the amount of charges charged in the C1 capacitor varies depending on the Tari value (6.25 us, 12.5 us, 25 us). Therefore, the gate voltage of the M2 transistor is changed according to the Tari value, and the amount of current (I total ) flowing in the M2 transistor is changed. Therefore, the gates of the M3 transistor and the M4, M5, and M6 transistors are connected to each other so that the current flowing in the M2 transistor flows to any transistor (any one of the M4, M5, and M6 transistors connected in parallel) selected according to the Tari value.

The plurality of switches (Tari_S1, Tari_S2, Tari_S3) are controlled on and off by the Tari value. The switch Tari_S1 is on when Tari = 6.25us and causes some current I1 flowing in the M2 transistor to flow to the M4 transistor. The switch Tari_S2 is turned on when Tari = 12.5us and causes some current I2 flowing in the M2 transistor to flow to the M5 transistor. The switch Tari_S3 is turned on when Tari = 25us and causes some current I3 flowing in the M2 transistor to flow to the M5 transistor. The sizes of the transistors M4, M5, and M6 operating according to the Tari value are determined in consideration of the amount of current (I total ) of the M2 transistor depending on the Tari value. Therefore, even if the Tari value changes, the charge current flowing to the capacitors (C2, C3, C4) is controlled to some extent.

The plurality of switches SS_S1, TT_S2, and FF_S3 are on / off controlled in accordance with the process environment control signal. The switch SS_S1 is turned on at the SS process environment and allows the charge current (any one of I1, I2, and I3) to charge the C2 capacitor. The switch TT_S2 is turned on in the TT process environment and causes the charge current (any one of I1, I2, I3) to charge the C3 capacitor. The switch FF_S1 is turned on in the FF process environment and allows the charge current (any one of I1, I2, and I3) to charge the C4 capacitor. The capacitances of the capacitors C2, C3 and C4 are determined on the basis of the process variation occurring according to the process environment, so that the voltage charged in the capacitors C2, C3 and C4 is constantly outputted even if the process environment is changed.

FIG. 6 is a graph comparing a voltage generator of a PIE decoder according to an embodiment of the present invention with a conventional output voltage when Tari is 6.25 us, and FIG. 8 is a graph comparing a voltage generator of a PIE decoder according to an exemplary embodiment of the present invention with an output voltage of the prior art when a Tari is 25 us Fig.

Referring to FIG. 6, when Tari is 6.25 us, (a) is the output voltage of data-0 and data-1 according to the process environment (SS, TT, FF) in the conventional structure to which the present invention is not applied, Shows output voltages of data-0 and data-1 according to the process environment (SS, TT, FF) of the voltage generator 130 of the present invention.

(a), the data-0 voltage in the FF process environment is higher than the data-1 voltage in the SS process environment because the conventional structure does not consider the process variation. Therefore, the conventional PIE decoder erroneously discriminates the data by the process deviation.

On the other hand, referring to (b), the voltage generator 130 generates a voltage difference between data-0 and data-1 irrespective of process variations. Since the data-0 voltage is smaller than the data-1 voltage in any process environment, the voltage comparator 150 can determine the data without error.

Referring to FIG. 7, when Tari is 12.5 us, (a) is the output voltage of data-0 and data-1 according to the process environment (SS, TT, FF) in the conventional structure to which the present invention is not applied, Shows output voltages of data-0 and data-1 according to the process environment (SS, TT, FF) of the voltage generator 130 of the present invention.

(A) is the output voltage of data-0 and data-1 according to the process environment (SS, TT, FF) in the conventional structure to which the present invention is not applied, (b) Shows the output voltages of data-0 and data-1 according to the process environment (SS, TT, FF) of the voltage generator 130 of the present invention.

5, the voltage generator 130 sufficiently provides margins for discriminating data-0 and data-1 with respect to all of Tari, so that even if a process deviation occurs, the voltage comparator 150 can generate a margin without error Data can be determined.

FIG. 9 is a graph comparing an output voltage of a PIE decoder according to an embodiment of the present invention with an output voltage of the prior art. FIG. 10 is a graph showing a relationship between a decoding margin of a PIE decoder and a decoding margin Fig.

9, (a) shows the output voltages of data-0 and data-1 according to the Tari, temperature and process environment of the conventional structure to which the present invention is not applied, (b) ) And the output voltage of data-0 and data-1 according to the temperature and the process environment.

(a), the process deviation is not compensated and the data-0 and data-1 voltages are mixed. Therefore, in the conventional structure, it is difficult to set a reference voltage for discriminating data-0 and data-1, and a data discrimination error may occur even if a proper reference voltage is set.

(b), the voltage generator 130 of the PIE decoder compensates the process deviation and outputs the data-0 and data-1 voltages. Therefore, if the value near 450 mV is set to the reference voltage (Vref), data-0 and data-1 can be discriminated without error even if the Tari, temperature, and process environment are changed.

10 is a diagram illustrating a decoding margin according to the Tari, temperature, and process environment of a conventional structure to which the present invention is not applied. FIG. 10 (b) The decoding margin according to FIG. The decoding margin is the voltage difference required to determine data-0 and data-1.

(a), the process margin is not compensated and the temperature is changed. If there is a process deviation, the decoding margin is reduced to 25 mV or less. The smaller the decoding margin, the higher the probability of data discrimination errors.

(b), the voltage generator 130 of the PIE decoder provides a decoding margin of at least 150 mV even if the temperature changes and there is a process deviation. If there is a decode margin of more than 150 mV, most digital logic can determine the data without error.

FIGS. 11 to 14 are diagrams for explaining self-frequency correction of a clock generator according to an embodiment of the present invention, and FIG. 15 is a view for explaining self-frequency correction results of a clock generator according to an embodiment of the present invention.

Referring to FIG. 11, a clock generator 200 that provides a clock (CLK) to a digital control circuit must generate a clock (1.92 MHz) of a constant frequency. For this purpose, the clock generator 200 performs self-frequency correction using the received PIE symbols to generate a clock of a certain frequency.

The clock generator 200 may include a digital frequency locked loop (FLL) circuit 210, a count divider 230, and a reference count value manager 250. The reference count value management unit 250 stores a reference count value N0 ref_freq of a data-0 length calculated with the reference frequency and a reference count value N1 ref_freq of a data-1 length. The reference frequency ref_freq may be 1.92 MHz.

The FLL circuit 210 includes a rise-edge detector 211 that senses the pulse width of the PIE symbol, a frequency f s of the sampling VCO 212 or a digital controlled oscillator (DCO) A symbol time-length counter 214 for counting the pulse width using the frequency f osc of the DCO 213, a frequency detector and a loop filter for controlling the frequency of the DCO 213 215).

The frequency detector and loop filter 215 of the FLL circuit 210 compares the count value obtained by counting the input data with the current frequency f osc of the DCO 213 and the reference count value corresponding to the reference frequency, The frequency of the signal 213 is corrected or lowered. A frequency detector and a loop filter 215 uses the reference count value (N0, or N1 ref_freq ref _ freq) received from the reference count value management unit (250). Any of N0 and N1 ref _ freq ref _ freq of the reference count value management unit 250 by the value of Ni selection PIE decoder 100 is selected and is designed to be input to a frequency detector and a loop filter (215). For this purpose, the input data of the clock generator 200 and the PIE decode 100 must be synchronized.

The count divider 230 may include a Tari detector 231 and a divider 233. In the FLL circuit 210, a loop filter for each of the three Tari values is required. In order to reduce the complexity of the circuit, an operation for dividing Tari is performed. If the reference Tari is set to 6.25us and Tari = 6.25us

Figure 112015091295242-pat00002
1, Tari = 12.5us
Figure 112015091295242-pat00003
2 and Tari = 25us
Figure 112015091295242-pat00004
4. The count divider 230 inputs the calculation result for Tari = 6.25us to the loop filter 215 and the reference count value management unit 250. [ The Tari detector 231 can be used as a function for judging the process environment after determining the Tari for self-frequency correction.

The self-frequency correction method of the clock generator 200 according to the PIE symbol input in the following will be sequentially described. Particularly, the conventional clock generator does not operate properly due to a process deviation of the PIE decoder. However, the clock generator 200 of the present invention uses the discrimination data of the PIE decoder 100, which stably operates in spite of the process variation, Can be performed.

12 schematically illustrates a Tari discrimination method using the Tari section of the preamble.

The clock generator 200 determines the Tari value before performing the self-frequency correction using the PIE symbol data interval.

The rising edge detector 211 calculates the length (pulse width) of the Tari section.

Counter 214 calculates the count value (Ntick) corresponding to the length of the Tari interval using the frequency of the sampling VCO (f s). The sampling VCO has a frequency deviation depending on the process environment. However, as described with reference to Table 1, the range of the Ntick value does not overlap with the three typical process environments (SS, TT, FF).

The Tari detector 231 can detect any one of 6.25us, 12.5us, and 25us as the Tari value of the input PIE symbol using the count value (Ntick).

The count value (Ntick) and the Tari value of Tari calculated in the clock generator (200) at the frequency (f s ) of the sampling VCO can be input to the PIE decoder (100).

Since the count value of the data-0 with respect to the reference frequency is calculated from the Tari value, the count value (N0 1.92 MHz ) of the data-0 with respect to the reference frequency ( 1.92 MHz ) Is stored in the reference count value storage.

As described above, the value of N0 1.92 MHz means a value obtained by counting the data-0 when the output frequency of the DCO 213 is 1.92 MHz. Since the data-0 value is any one of three types (6.25 us, 12.5 us, 25 us), the reference count value is also required for each Tari. Therefore, in order to reduce the complexity of the circuit, the count divider that divides Tari has a count value corresponding to Tari = 6.25us according to Tari according to the amount of distribution. When the clock frequency is 1.92MHz, the value obtained by counting Tari = 6.25us is 24 and the previously calculated value is stored at N0 1.92MHz .

FIG. 13 is a diagram for explaining a method of setting a reference count value (N1 ref_freq ) of data-1 using an interval after a Tari interval in a preamble interval of a PIE symbol.

Data-1 has a pulse width corresponding to (1 + x) * Tari, and the pulse width (period) varies depending on x. The reference count value managing unit 250 calculates a reference count value (N1 1.92 MHz ) of the data-1 with respect to the reference frequency ( 1.92 MHz ) using the count value of the RTcal interval and the count value of the Tari interval.

N1 1. 92 MHz is input to the FLL circuit 210 when the input of the PIE symbol is data-1 while the FLL circuit 210 performs its own frequency correction.

Thus, the clock generator 200 calculates a reference count value corresponding to the pulse width of data-0 and data-1. The clock generator 200 can calculate the reference count value using the sampling VCO only in the preamble period. The sampling VCO may be set to be off when the preamble interval ends and the data interval starts.

FIG. 14 is a diagram schematically illustrating a method in which the clock generator 200 performs its own correction using a data interval after a preamble period ends in a PIE symbol.

The clock generator 200 performs self-frequency correction using the data-0 and data-1 lengths of the data interval.

When the data-0 is input, the control signal Ni select of the PIE decoder 100 is output as 0, and the reference count value (N0 1.92 MHz ) corresponding to the data-0 is input to the FLL circuit 210. The FLL circuit 210 compares the reference count value (N0 1.92 MHz ) with the count value by the current frequency, and performs self-frequency correction to lower or raise the current frequency.

When the data-1 is input, the control signal Ni select of the PIE decoder 100 is outputted as 1, and the reference count value N1 1.92 MHz corresponding to the data-1 is inputted to the FLL circuit 210. The FLL circuit 210 compares the reference count value (N1 1.92 MHz ) with the count value by the current frequency, and performs self-frequency correction to lower or raise the current frequency.

The clock generator 200 repeats its own frequency correction process using the data interval until the desired 1.92 MHz frequency is output as shown in FIG.

FIG. 15 is a diagram showing self-frequency correction results of a clock generator according to an embodiment of the present invention. FIG.

Referring to FIG. 15, the clock generator 200 performs self-frequency correction based on the PIE symbol discrimination data of the PIE decoder 100 with a small data discrimination error. As a result, the clock generator 200 generates a clock of 1.92 MHz within an error of 0.5% .

16 is a flowchart illustrating a method of operating a PIE decoder according to an embodiment of the present invention.

Referring to FIG. 16, the PIE decoder 100 receives a count value (Ntick) obtained by calculating a Tari interval (data-0 interval) of the PIE symbol using a sampling VCO (S110).

The PIE decoder 100 receives the Tari value of the PIE symbol (S120).

The PIE decoder 100 determines the process environment by comparing the count value (Ntick) calculated by the sampling VCO with the count value of the Tari value (S130). A frequency deviation occurs in the sampling VCO depending on the process environment, and as a result, the value counted by the clock of the sampling VCO changes. Therefore, the process environment can be determined on the basis of the count value (Ntick) obtained by calculating the input Tari section by the sampling VCO. At this time, a method of comparing the count value (Ntick) of the Tari section of the PIE symbol calculated by the sampling VCO with the count value of the Tari value may be variously implemented. For example, as described with reference to FIG. 4, the MUX1 114 outputs a reference count value for determining the process environment of the SS and the TT according to the Tari value, and the MUX2 115 outputs And outputs a reference count value for discriminating the process environment of TT and FF according to the Tari value. The reference count value output from each of the MUX1 114 and the MUX2 115 and the value Ntick obtained by counting the Tari interval using the sampling VCO are used to determine the process environment determination logic gate 118 may be designed to operate.

The PIE decoder 100 selects a capacitor corresponding to the process environment from among the plurality of capacitors (S140). The amount of current that charges the capacitor may be changed by the deviation of the devices generated according to the process environment. Each of the plurality of capacitors has a capacitance value corresponding to the process environment so that a constant voltage is output even when the charge current amount is changed.

The PIE decoder 100 charges and discharges the selected capacitor according to the signal of the PIE symbol (S150).

The PIE decoder 100 compares the voltage of the capacitor with the reference voltage to discriminate the data of the PIE symbol (S160).

The PIE decoder 100 transmits the determined result to the clock generator 200 (S170).

As described above, according to the embodiment of the present invention, the analog decoder senses the process environment through the process environment sensing circuit and compensates the process deviation, thereby outputting a constant voltage regardless of the process variation. Therefore, according to the embodiment of the present invention, even if an analog decoder is used, it is possible to reduce a discrimination error due to a process deviation. According to the embodiment of the present invention, since the analog decoder is used, power consumption can be reduced as compared with a digital decoder that discriminates data using a clock. According to an embodiment of the present invention, the clock generator can generate a clock of the frequency required by the EPC C1G2 standard using the discrimination data of the analog decoder.

The embodiments of the present invention described above are not implemented only by the apparatus and method, but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (16)

As an analog decoder of a passive tag,
(Tari value) used in the inputted PIE (pulse interval encoding) symbol is received, and the data-0 length (Tari value) is virtually set to each frequency of the ring oscillator of the ring oscillator varying according to the process environment Calculating a first value for each process environment by comparing the first value for each process environment with a second value counted by the actual frequency of the ring oscillator, A process environment sensing circuit for sensing a process environment and generating a control signal based on the sensed process environment,
A voltage generator for selecting a capacitor to be charged based on the control signal, charging the capacitor according to the signal of the PIE symbol, and outputting the charged capacitor voltage,
A voltage comparator for comparing the reference voltage and the output voltage of the voltage generator to determine data of the PIE symbol,
/ RTI > The method of claim 1,
Wherein the data-0 length is a value of one of 6.25us, 12.5us, and 25us. The method of claim 1,
The voltage generator
A plurality of capacitors having a capacitance determined based on a process variation of each of a plurality of process environments, and a capacitor corresponding to the specific process environment among the plurality of capacitors is charged based on a specific process environment included in the control signal An analog decoder to select with a capacitor. 4. The method of claim 3,
The voltage generator
Wherein the capacitance of each of the plurality of capacitors is determined such that the output voltage by the data-1 signal has a value larger than the output voltage by the data-0 signal even if the process environment is changed. 4. The method of claim 3,
The voltage generator
And a switch for controlling the charging of each of the plurality of capacitors, and controls on / off of the switch based on the control signal. The method of claim 1,
The voltage generator
And a transistor circuit for varying the amount of current flowing to the capacitor according to a data-0 length of the PIE symbol. The method of claim 1,
The process environment sensing circuit
A value obtained by calculating the data-0 interval from the clock generator of the tag by the ring oscillator and the data-0 length,
Wherein the data-0 length is a value of one of 6.25us, 12.5us, and 25us. The method of claim 1,
The voltage comparator
And transmits the data discrimination result of the PIE symbol to the clock generator of the tag. A method of operating an analog decoder included in a passive tag,
Detecting a process environment by comparing a count value obtained by calculating a data-0 interval of a PIE (pulse interval encoding) symbol with a ring oscillator and a reference value,
Selecting a capacitor corresponding to the sensed process environment from among a plurality of capacitors having a capacitance determined based on a process variation of each of the plurality of process environments,
Charging the selected capacitor according to the data signal of the PIE symbol, and
Comparing the voltage of the charged capacitor with a reference voltage to determine the value of the data signal
Lt; / RTI >
The reference value
A count value of Tari calculated according to the process environment of the ring oscillator varying according to the process environment,
Wherein Tari is a value of one of 6.25us, 12.5us, and 25us. delete The method of claim 9,
The step of sensing the process environment
Detecting Tari of the PIE symbol,
Calculating a reference count value for each process environment by counting Tari detected using the frequency of the ring oscillator in each process environment, and
Determining a process environment by comparing a count value calculated by the ring oscillator with a reference count value for each process environment
≪ / RTI > delete The method of claim 9,
And transmitting the determined value to the clock generator
≪ / RTI > A clock generator of a passive tag,
A reference count value management unit for storing a first reference value obtained by counting a first data length at a target frequency and a second reference value obtained by counting a second data length at the target frequency,
And a circuit unit for receiving the reference value corresponding to the input data from the reference count value management unit and controlling the frequency of the oscillator to be lowered or increased by comparing the input reference value with a count value counted by the frequency of the oscillator and,
And the reference count value management unit transmits either the first reference value or the second reference value to the circuit unit based on the discrimination data of the input data. The method of claim 14,
The discrimination data of the input data is transmitted from the decoder,
The decoder
A capacitor is charged based on the input data, and the input data is determined based on a charge voltage of the capacitor. The method of claim 14,
The circuit part
Calculating a first data length and a second data length using a sampling oscillator in a preamble period of an input signal,
And stops the operation of the sampling oscillator when a data interval of the input signal starts.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109635908A (en) * 2018-12-13 2019-04-16 中山大学 Numerical model analysis decoding circuit, coding/decoding method and system architecture
CN109921860A (en) * 2018-12-31 2019-06-21 浙江悦和科技有限公司 A kind of PIE coded demodulation method of super low-power consumption

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006311561A (en) * 2005-04-29 2006-11-09 Seiko Epson Corp Circuits oscillator, ring oscillator and method for generating a plurality of oscillation signals
KR20080051846A (en) * 2006-12-07 2008-06-11 주식회사 하이닉스반도체 Circuit for generating clock of semiconductor memory apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006311561A (en) * 2005-04-29 2006-11-09 Seiko Epson Corp Circuits oscillator, ring oscillator and method for generating a plurality of oscillation signals
KR20080051846A (en) * 2006-12-07 2008-06-11 주식회사 하이닉스반도체 Circuit for generating clock of semiconductor memory apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
X. Wang et al, "A Novel Low-Power Digital Baseband Controller for Passive UHF RFID Tag", IEEE WiCOM 2012(2012.09.23.)* *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109635908A (en) * 2018-12-13 2019-04-16 中山大学 Numerical model analysis decoding circuit, coding/decoding method and system architecture
CN109635908B (en) * 2018-12-13 2020-09-11 中山大学 Digital-analog hybrid decoding circuit, decoding method and system architecture
CN109921860A (en) * 2018-12-31 2019-06-21 浙江悦和科技有限公司 A kind of PIE coded demodulation method of super low-power consumption
CN109921860B (en) * 2018-12-31 2021-10-26 浙江悦和科技有限公司 PIE coding and demodulating method with ultra-low power consumption

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