KR101695091B1 - SVPWM scheme for common-mode voltage reduction in five-level ANPC inverters - Google Patents

Abstract

The present invention relates to a SVPWM method for reducing the common mode voltage of a 5-level ANPC that reduces the variation of other capacitor voltages in switching while reducing the common mode voltage of the ANPC, Level ANPC having three-phase and three-legs, and each of the legs is a SVPWM method for reducing a common-mode voltage of a 5-level ANPC composed of a plurality of switches and a flying capacitor, Width Modulation) inverter to control the neutral point voltage of the DC link and the common mode voltage using the space vector. Therefore, the size of the common mode voltage of the 5-level ANPC can be reduced to 1/12 of the DC link voltage, the neutral point voltage can be controlled according to the selection of the space vector, and the total harmonic distortion THD And the switching loss is not increased as compared with the conventional method, and the advantage of the ANPC can be maintained.

Description

[0001] The present invention relates to a method for reducing common-mode voltage of a five-level ANPC,

The present invention relates to a space vector PWM (SVPWM) method for reducing the common mode voltage of a 5-level ANPC, and more particularly to a method for reducing the common mode voltage of 5-level ANPC used in medium voltage, To an SVPWM method.

A common mode voltage (CMV) is generated by a PWM (Pulse Width Modulation) inverter constituting a power conversion apparatus such as an electric motor drive apparatus. The common-mode voltage is one cause of the leakage current. In the case of inverters used in medium-voltage and large-capacity devices, there is a possibility that a large leakage current flows. This can affect the performance of the system and may cause a failure.

A multi-level inverter capable of power conversion with a larger capacity than a conventional two-level inverter and solving the problem of loss of the switch has been developed. Multilevel inverters can achieve output voltage closer to sinusoidal wave by dividing the output of voltage. Switching losses are also divided among the devices, which can result in higher efficiency power conversion as the switching frequency is increased.

The most commonly used multi-level inverters are neutral-point-clamped (NPC), flying capacitor (FC), and cascaded H-bridge (CHB) type inverters. Among them, NPC type inverters have a merit that they are simpler in configuration than the other topologies and are relatively easy to control. However, there is a difference in loss between the individual switches, resulting in problems such as capacity calculation and heat dissipation design.

Active neutral-point-clamped (ANPC) inverters have been developed to compensate for unbalanced losses between switching devices in conventional NPC topologies. Therefore, the output power and the switching frequency can be increased as compared with the NPC inverter. These advantages are mainly used for driving medium-voltage, large-capacity generators and motors.

In general, the devices used to drive the device include DC sources, PWM inverters, and loads. Switching of the PWM inverter generates a common mode voltage. Common mode voltage is the cause of EMI (Electro Magnetic Interference), dielectric breakdown inside equipment, leakage current of bearing of equipment.

In order to solve the problem of the common mode voltage, development has been progressed by changing the PWM switching pattern to reduce the magnitude of the voltage.

In the case of a two-level inverter, there is a method of reducing the peak amplitude of CMV using a zero vector. In the case of the NPC-type 3-level inverter, four voltage vectors (zero, large, medium, small) exist, and the voltage is generated using only the medium and small vectors to reduce the CMV Methods have been developed.

In addition, a method of reducing the CMV by a factor of 1/6 of the DC link voltage using an optional small and large vector has also been developed. In this method, the neutral point voltage of the DC link can not be controlled, and THD (Total Harmonic Distortion) and switching loss increase.

Although a method for reducing the CMV size of a 5-level NPC inverter has been disclosed, it is difficult to apply the DC link voltage control to the actual system. In the case of the 5-level ANPC, some methods have been proposed, but the size of the CMV is 1/4 of the DC link voltage and the common mode voltage is large.

CMV is removed by using an additional transformer instead of such a software solution, but the size and weight of the system are increased.

Korean Patent Registration No. 10-0300558 (June 18, 2001)

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-described problems of the prior art, and an object of the present invention is to provide an SVPWM method for reducing the common mode voltage of the 5-level ANPC in which the variation of the capacitor voltage due to the switching is reduced, The purpose is to provide.

In order to achieve the above object, the present invention is characterized in that a DC link unit having two DC link capacitors and a three-phase five-level ANPC composed of three legs are provided, and each of the legs comprises a plurality of switches and a flying capacitor The SVPWM method for reducing the common mode voltage of a 5-level ANPC comprises generating a common mode voltage using a PWM (Pulse Width Modulation) inverter, controlling the neutral point voltage of the DC link and the common mode voltage Level ANPC's common-mode voltage reduction.

When using the space vector PWM, a three-phase five-level ANPC inverter can have 125 space vectors according to the outputs of three legs.

A space vector of a triangle is selected according to a position of a voltage to be output, a switching function is indicated at a vertex of each triangle, and a switching state can be determined according to a magnitude of a neutral voltage and a flying capacitor voltage.

Each of the legs may have five different output voltages and eight switching states.

The neutral point voltage and the flying capacitor voltage are charged and discharged according to the switching state, and the current flowing in the neutral point of the flying capacitor and the DC link is determined, and the capacitor voltage can be controlled using the neutral point voltage and the flying capacitor voltage.

The case 1 has 55 space vectors, the case 2 and the case 3 have 52 space vectors, and the case 1 has the CMV voltage And cases 2 and 3 are preferably vectors for controlling the DC link voltage.

Each of the space vectors has a switching function, so that the switches of each leg can operate.

When the variation of the neutral point voltage of the DC link is less than the reference size, the voltage is output using the space vector of Case 1, and CMV can have a size of ± 1/12 of the DC link voltage (Vdc).

A case 3 where the variation of the neutral point voltage is equal to or higher than a predetermined voltage and a case 3 where the variation of the voltage is positive and a case 2 where the variation of the voltage is negative. The CMV of the case 2 is a value of Vdc / 6 , And Case 3 may have a magnitude of 0 to -Vdc / 6.

The case 2 and 3 have six trapezoidal vectors, respectively. In this case, a desired output voltage can be generated by using two switching functions of the opposite trapezoidal vector.

According to the SVPWM method for reducing the common mode voltage of the 5-level ANPC according to the present invention, 1) the size of the common mode voltage of the 5-level ANPC can be reduced to 1/12 of the DC link voltage, 3) the total harmonic distortion (THD) does not increase compared to the conventional method, 4) the switching loss is not increased compared with the conventional method, and 5) the ANPC It is possible to maintain the advantages of the present invention.

FIG. 1A is a block diagram of a three-phase 5-level ANPC inverter for implementing the present invention;
1B is a block diagram showing one leg of the three-phase five-level ANPC inverter of FIG. 1A in more detail;
FIG. 2 is a diagram showing space vectors classified into 125 when general space vector PWM is used,
FIG. 3 is a flow chart illustrating an SVPWM method for reducing a common mode voltage of a 5-level ANPC according to the present invention;
4A is a conceptual diagram showing a case 1 having a minimum CMV,
FIG. 4B is a conceptual view showing a case 2 according to charging of a neutral point voltage,
4C is a conceptual view showing a case 3 according to a neutral-point voltage discharge,
FIG. 5 is a graph of a simulation result of a 5-level ANPC inverter using a new space vector PWM method (case 1) at a modulation index 0.95 condition according to an embodiment of the present invention,
FIG. 6 is a graph of a simulation result of a 5-level ANPC inverter using the performance (case 1, case 2) of a 5-level ANPC inverter using a new space vector PWM method according to an embodiment of the present invention.

The present invention may have various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a block diagram showing a 3-phase 5-level ANPC inverter for implementing the present invention, and FIG. 1B is a block diagram showing one leg of a 3-phase 5-level ANPC inverter of FIG. 1A in more detail.

The PWM method for solving the technical problem of the present invention includes a method and a space vector diagram (cases 1, 2, 3) for controlling the neutral voltage and the common mode voltage.

As shown in FIG. 1A, in order to implement the present invention, a three-phase 5-level ANPC 25 (shown in FIG. 1A) consisting of a DC link portion 14 having two DC link capacitors 19 and three legs 15 . Each leg 15 is composed of eight switches S, S1c, S2, S2c, S3, S3c, S4, S4c and a flying capacitor 22 as shown in FIG. Where n (17) is the neutral point of the DC link.

Using a typical spatial vector PWM, the three-phase five-level ANPC inverter has 125 spatial vectors according to the outputs of three legs (15). This is shown in FIG.

FIG. 2 is a diagram showing a space vector divided into 125 by using a general space vector PWM. As shown in FIG. 2, a triangular space vector is selected according to a position of a voltage to be output. At the vertex 28 of each triangle, a switching function is indicated, and the switching state is determined according to the magnitude of the neutral voltage and the flying capacitor voltage. Each leg 15 has five different output voltages and eight switching states, and the switching states of the double five-level ANPC 1-lag are shown in Table 1 below.

As shown in Table 1, the neutral point voltage and the flying capacitor voltage are charged / discharged according to the switching state.

For example, the switching state of V5 or V6 is a state where a voltage of Vdc / 4 is outputted. Accordingly, the current flowing through the neutral point of the flying capacitor and the DC link is determined, and the capacitor voltage is controlled using the current.

When the general space vector PWM is used, the CMV of the three-phase inverter is defined by the following equation (1).

Where van, vbn, and vcn denote the pole voltages of each phase.

Here, Sa, Sb, and Sc are switching functions having values of 0, 1, 2, 3, and 4 as seen in Table 2.

3 is a flowchart illustrating an SVPWM method for reducing the common mode voltage of the 5-level ANPC according to the present invention. Where vn is the neutral point voltage of the DC link. According to the change of? Vn, one of three spatial vectors 41, 42 is selected and the voltage is output (30, 32, 34).

The new space vector case 1, case 2 and case 3 are shown in Figs. 4A to 4C. Here, FIG. 4A shows case 1 with the minimum CMV, FIG. 4B shows case 2 according to charging of the neutral point voltage, and FIG. 4C shows case 3 according to the neutral point voltage discharge.

Case 1 has 55 space vectors, and Case 2 and Case 3 have 52 space vectors. Case 1 is a vector for minimizing the CMV voltage, and Cases 2 and 3 are vectors for controlling the DC link voltage. Each spatial vector also has a switching function, so that the switches of each leg operate accordingly. vn and? vn are defined by the following equations (3) and (4).

When the neutral point voltage of the DC link is constantly controlled, that is, when the variation of the voltage is equal to or smaller than a certain magnitude, the voltage is output using the space vector of Case 1, and CMV is set to ± 1/12 of the DC link voltage (Vdc) Size.

When the variation of the neutral-point voltage is equal to or higher than a predetermined voltage, the case 3 is used to reduce the voltage variation when the voltage is positive. The case 2 is used when the voltage variation is negative. CMV of Case 2 has a magnitude of 0 to Vdc / 6, and Case 3 has a magnitude of 0 to -Vdc / 6.

Case 2 and Case 3 have six trapezoidal vectors, respectively. In this case, two switching functions are used to generate the desired output voltage. For example, in the case of the VP1 region of FIG. 4B, the switching function 430 of the trapezoidal shape vector facing the innermost switching function 431 is used. The switching function is shown in Table 1.

The new space vector PWM method according to the present invention can be used in the same manner as the general ANPC control method for the flying capacitor voltage, and the switching loss and the THD are also the same.

Therefore, according to the SVPWM method for reducing the common mode voltage of the 5-level ANPC according to the present invention, the size of the common mode voltage of the 5-level ANPC can be reduced to 1/12 of the DC link voltage, The voltage of the neutral point can be controlled according to the selection of the vector, the total harmonic distortion (THD) does not increase as compared with the conventional method, the switching loss is not increased as compared with the conventional method, and the advantage of ANPC can be maintained.

<Examples>

Embodiments of the present invention will be described and the results thereof will be described.

In order to verify the effect of reducing the common mode voltage of the 5-level ANPC inverter using the space vector PWM method proposed by the present invention, a three-phase 5-level ANPC multilevel inverter is applied to the motor drive system as shown in FIG. .

The simulation conditions are shown in Table 2 below.

FIG. 5 is a simulation result of a 5-level ANPC inverter using the space vector PWM method (case 1) of the present invention under a condition of a modulation index of 0.95.

As shown in the figure, the fluctuation of the neutral point of the DC link voltage is controlled to 12V or less, which is 2% of the DC link voltage, and therefore the space vector of Case 1 is applied. 5 (a) is a three-phase current. 5 (b) and 5 (c) show the line voltage and the pole voltage, respectively. 5 (d) shows the common mode voltage (CMV), which is output at 50 V which is 1/12 of the DC link voltage. 5 (e) is a switching signal of S1 and S2 of the a-phase leg varying with the fundamental wave voltage.

6 is a graph showing the performance (case 1, case 2) of the 5-level ANPC inverter using the space vector PWM method of the present invention.

6 is a result of applying Case 1 and Case 2 according to an embodiment of the present invention. Here, FIG. 6 (a) is the voltage of the DC link capacitor. Case 2 is applied because the average value DELTA vn of the voltage difference between the upper capacitor and the lower capacitor of the DC link is negative, and thus the voltage of the DC link capacitor is controlled to be the same. 6 (b) shows the flying capacitor voltage. It can be confirmed that it is controlled constantly. The CMV is shown in Fig. 6 (c). As mentioned above, the spatial vectors used (cases 1, 2, and 3) change as they change. 6 (d) shows the case change according to the change of the DC link voltage.

Therefore, according to the embodiment, the size of the common mode voltage of the 5-level ANPC of the present invention can be reduced to 1/12 of the DC link voltage, the neutral point voltage can be controlled according to the selection of the space vector, The total harmonic distortion (THD) does not increase, and compared with the conventional method, the switching loss is not increased, and it can be confirmed that the advantage of ANPC can be maintained.

The embodiments of the present invention described in the present specification and the configurations shown in the drawings relate to the most preferred embodiments of the present invention and are not intended to encompass all of the technical ideas of the present invention so that various equivalents It should be understood that water and variations may be present. Therefore, it is to be understood that the present invention is not limited to the above-described embodiments, and that various modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. , Such changes shall be within the scope of the claims set forth in the claims.

14: DC link part
15: Leg
19: DC link capacitor
22: Flying capacitor
25: 3-phase 5-level ANPC

Claims (10)

There is provided a three-phase 5-level ANPC composed of a DC link portion having two DC link capacitors and three legs, wherein each leg has a common mode voltage reduction of a 5-level ANPC composed of a plurality of switches and a flying capacitor In the SVPWM method,
A common mode voltage is generated using a PWM (Pulse Width Modulation) inverter,
And the common-mode voltage of the DC link and the common-mode voltage are controlled using a space vector,
In order to control the neutral voltage and the common mode voltage, the space vector includes a case 1 having a minimum CMV (Common Mode Voltage), a case 2 according to the neutral voltage charging, and a case 3 according to a neutral voltage discharging,
When the variation of the neutral point voltage of the DC link is less than the reference size, the voltage is output using the space vector of Case 1. CMV has the size of ± 1/12 of the DC link voltage (Vdc) A case 3 in which the size of the voltage fluctuation is positive or a case 2 in which the voltage fluctuation is negative is used; the CMV of the case 2 has a magnitude of 0 to Vdc / 6; Wherein the output signal has a magnitude of 0 to -Vdc / 6. The method according to claim 1,
Level ANPC inverter has 125 spatial vectors according to the outputs of the three legs 15 when the space vector uses PWM. The SVPWM method for reducing the common mode voltage of the 5-level ANPC . The method according to claim 1,
A space vector of a triangle is selected according to a position of a voltage to be output, a switching function is indicated at a vertex of each triangle, and a switching state is determined according to a magnitude of a neutral voltage and a flying capacitor voltage An SVPWM method for reducing the common mode voltage of 5 - level ANPCs. The method according to claim 1,
Wherein each leg has five different output voltages and eight switching states. &Lt; RTI ID = 0.0 &gt; [100] &lt; / RTI &gt; The method according to claim 1,
The neutral point voltage and the flying capacitor voltage are charged / discharged according to the switching state,
The current flowing through the neutral point of the flying capacitor and the DC link is determined and the capacitor voltage is controlled using the current. The SVPWM method for reducing the common mode voltage of the 5-level ANPC. The method according to claim 1,
The voltage of one of the three spatial vectors is selected according to the change of the neutral point voltage of the DC link, and the voltage is output. Case 1 has 55 space vectors, Case 2 and Case 3 have 52 space vectors,
Wherein the case 1 is a vector for minimizing the CMV voltage, and the cases 2 and 3 are vectors for controlling the DC link voltage. The SVPWM method for reducing the common mode voltage of the 5-level ANPC. The method according to claim 1,
Wherein each of the space vectors is marked with a switching function, whereby the switches of each leg operate. &Lt; RTI ID = 0.0 &gt; 5. The &lt; / RTI &gt; delete delete The method according to claim 1,
The case 2 and 3 have six trapezoidal vectors, respectively. In this case, a desired output voltage is generated by using two switching functions of the opposite trapezoidal vector. The common mode of the 5-level ANPC SVPWM Method for Voltage Reduction.

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