KR101693591B1 - Lightweight cryptographic apparatus using hardware and software co-design - Google Patents

Abstract

The present invention relates to a lightweight encryption device capable of integrated design of hardware and software, and includes a microprocessor according to a block cipher operation method and a GEZEL hardware co-processor communicating with the microprocessor, , The GEZEL hardware co-processor comprises one or more hardware IPs operating in a finite state machine with datapath (FSMD) scheme using GEZEL intellectual property (IP) blocks and datapath.
According to the lightweight cryptographic apparatus capable of integrally designing the hardware and software according to the present invention, the hardware and software of the block cipher and the lightweight cryptographic algorithm are optimized by using the GEZEL of the finite state machine (FSMD) By integrated design, it is free from race condition, so signal timing catch is easy, there is no possibility of falling into deadlock, and the interface between hardware and software is optimized to reduce overall latency and improve speed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light-

The present invention relates to a lightweight encryption apparatus capable of integrating hardware and software, and more particularly, to an integrated design of hardware and software of a block cipher and a lightweight encryption algorithm using GEZEL of a finite state machine (FSMD) To a lightweight encryption apparatus.

The cryptosystem is largely classified into a public key cryptosystem and a symmetric key cryptosystem using the same key for encryption / decryption. In low-power / light-weight environments such as RFID and USN, efficient encryption algorithms are required while ensuring safety. In this environment, a symmetric key lightweight cipher that performs encryption on a plaintext block basis is often used. And, lightweight cryptography is used with various operating modes to encrypt messages of various lengths rather than being used alone.

When designing a cryptographic system, a hardware / software integrated design technique that can maximize the advantages of each design method is applied rather than designing each module as hardware and software. However, there is a problem that the linguistic characteristics of the hardware / software are quite different, and the optimization method is also different.

Patrick R. Schaumont, "A Practical Introduction to Hardware / Software Codesign," Springer, Dec. 2012.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and it is an object of the present invention to provide an encryption method and a lightweight encryption algorithm, And a lightweight cryptographic device that combines hardware and software of a block cipher and a lightweight cipher algorithm using GEZEL of a finite state machine (FSMD) method using a data path. The purpose is to provide.

In order to accomplish the above object, the present invention includes a microprocessor according to a block cipher operating method and a GEZEL hardware co-processor communicating with the microprocessor, wherein the GEZEL hardware co- And one or more hardware IPs operating in a finite state machine with datapath (FSMD) scheme using GEZEL intellectual property (IP) blocks and datapaths, the microprocessor comprising hardware and software integration The key schedule part of the algorithm of each symmetric key cryptosystem at the time of design is implemented in software to calculate each round key value in advance and sends the calculated round key to the hardware to increase the speed by omitting the key schedule calculation process in the hardware , ≪ / RTI > the microprocessor has two The hardware executes the two instructions sequentially or in parallel, and the microprocessor receives one completion command corresponding to the first command transmission from the hardware, Through the communication sent to the hardware, the hardware operation wait time is reduced in the software operation after the first arithmetic cycle, and the interface that sends and receives the message is performed while the software and hardware perform the encryption operation.

A lightweight cryptographic apparatus capable of integrally designing hardware and software according to the present invention, the microprocessor comprising an electronic codebook (ECB), a cipher block chain (CBC), a counter (CTR), a cryptographic feedback (CFB) And the block cipher is operated by selecting one of the methods.

A lightweight encryption device capable of integrating hardware and software according to the present invention, the at least one hardware IP including hardware IP of a lightweight encryption HIGHT scheme, hardware IP of a lightweight encryption PRESENT scheme, and hardware IP of a lightweight encryption PRINTcipher scheme .

The hardware IP of the lightweight cryptographic HIGHT technique includes a HIGHT controller for defining and controlling each data path of the lightweight cryptographic HIGHT technique as a finite state machine, and HIGHT_round_dp datapath that performs an encryption algorithm of a cipher HIGT techniques, the key schedule (key schedule) to perform kEY expand data path, look to-up table (look-up table) F ₀ with an output of the internal function in the form And a delta data path for storing a delta value used for a combination of F ₁ data paths and round subkeys.

In the lightweight encryption apparatus capable of designing the integrated hardware and software according to the present invention, the HIGHT controller performs a key schedule after performing 4 rounds using 16 subkeys, and performs a retiming retiming is applied to reduce the delay of a critical path.

The hardware IP of the lightweight encryption PRESENT scheme includes a PRESENT controller for defining and controlling each data path of the lightweight encryption PRESENT scheme as a finite state machine, A RESENT_round_dp data path for performing the encryption algorithm of the encryption PRESENT scheme, a plurality of S-box data paths for processing input and output in the form of a look-up table, and a key-box data path for use in key scheduling .

The PRESENT controller processes an S-box requiring input and output as one data path using the look-up table, and controls the S-box layer of the S-box layer By delimiting input values into registers, it is possible to reduce the delay that may occur between the PRESENT_round_dp data path and the S-box data path, and to perform an S-box layer, a Permutation Layer, and an AddRoundKey of the next round for each cycle .

The hardware IP of the lightweight cryptographic PRINT cipher technique includes a PRINT cipher controller for defining and controlling each data path of the lightweight cryptographic PRINT cipher technique as a finite state machine, A PRINTcipher_round_dp data path for performing a cryptographic algorithm of the cryptographic PRINT cipher technique, and a plurality of SP-box datapaths for performing permutation and S-box substitution.

In the lightweight encryption apparatus capable of designing the hardware and software integrated according to the present invention, the PRINT cipher controller reduces the amount of computation by setting the preprocessing portion of permutation and S-box substitution according to the PRINT cipher technique in advance as one table, The loop logic of the round operation is reconfigured to increase the number of times of reading and writing data for each loop to apply unfolding to reduce a cycle.

A lightweight cryptographic apparatus capable of integrating hardware and software according to the present invention, the microprocessor comprising: a memory mapped I / O system or a port map input / output (port) system in communication with the GEZEL hardware co- mapped I / O).

In the lightweight encryption apparatus capable of integrating hardware and software according to the present invention, the microprocessor uses a handshake protocol in which encryption and message transmission / reception are simultaneously performed in parallel with the GEZEL hardware co- And transmits and receives a message.

In a lightweight cryptographic apparatus capable of designing an integrated hardware and software according to the present invention, the microprocessor is configured to transmit a first command and a second command to the GEZEL hardware co-processor for communication using the handshake protocol Wherein the GEZEL hardware co-processor receives the first instruction and the second instruction to perform operations sequentially or in parallel at a time, and wherein the first instruction received by the GEZEL hardware co- The microprocessor receiving the first completion signal generates a third instruction and a fourth instruction and stores the third instruction and the fourth instruction in a buffer, and the GEZEL hardware co- And a second completion signal of a later completed operation of the first instruction and the second instruction received by the processor And the microprocessor that has received the second completion signal repeatedly transmits the third instruction and the fourth instruction stored in the buffer to the GEZEL hardware co-processor.

According to the lightweight cryptographic apparatus capable of integrally designing the hardware and software according to the present invention, the hardware and software of the block cipher and the lightweight cryptographic algorithm are optimized by using the GEZEL of the finite state machine (FSMD) By integrally designing, it is free from race condition, and signal timing catch is easy, and there is no possibility of falling into deadlock state.

In addition, the interface between the hardware and the software is optimized to reduce the overall latency and improve the speed.

1 is a block diagram illustrating a structure of a lightweight encryption apparatus capable of designing an integrated hardware and software according to an embodiment of the present invention.
2 is a diagram illustrating an overall flow of a HIGHT finite state machine (FSM) according to an embodiment of the present invention.
3 is a diagram illustrating an overall flow of a PRESENT finite state machine (FSM) according to one embodiment of the present invention.
FIG. 4 is a diagram illustrating the entire flow of a PRINTcipher finite state machine (FSM) according to one embodiment of the present invention.
5 is a flowchart illustrating a communication method using a handshake protocol according to an embodiment of the present invention.

The present invention may have various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, GEZEL for hardware and software integrated design will be described in the present invention. GEZEL is a language and design platform developed to facilitate software and hardware integration design. GEZEL's syntax is intuitive so designers familiar with software design can easily design hardware.

GEZEL, a cycle-based hardware description language, is based on Finite State Machine with Datapath (FSMD). The hardware implementation optimization theory is easy to apply because other hardware design languages are based on finite state machines (FSM), while finite state machines are combined with datapaths.

In particular, GEZEL has been developed not only for hardware-only design, but also for integrated design of hardware and software. In the integrated design, GEZEL supports the IP core block of the ARM, 8051 microprocessor so that it can communicate with the ARM, 8051 microprocessors simply by inserting the IP block code supported by GEZEL without any additional compilation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a structure of a lightweight encryption apparatus capable of designing an integrated hardware and software according to an embodiment of the present invention. Referring to FIG. 1, a lightweight encryption apparatus capable of hardware and software integrated design includes a microprocessor 100 and a GEZEL hardware co-processor 200.

The microprocessor 100 includes an electronic code book (ECB) operating mode 110, a Cipher Block Chaining (CBC) operating mode 120, a counter (CTR) operating mode 130, The integrated design of hardware / software is built up through five operating modes: Cipher FeedBack (CFB) operating mode 140 and Output FeedBack (OFB) operating mode 150.

The electronic codebook operating mode 110 has the simplest structure of the operation method, and is a method of encrypting a message to be encrypted by dividing it into a plurality of blocks.

The cipher block chain operation mode 120 is coupled to the encryption result of the previous block with exclusive or XOR logic before each block is encrypted. In the case of the first block, the initialization vector is used. Since the output result is always the same if the initialization vectors are the same, a different initialization vector should be used for each encryption.

The counter operation mode 130 has a structure for changing the block cipher to a stream cipher. The counter operation mode 130 obtains the value of the current block for each block, combines the number and the nonce, and uses it as an input of the block cipher. Obtain consecutive random numbers from each block cipher and then combine them with the string to be encrypted with XOR logic. The counter operation mode 130 is capable of operating in parallel since the encryption and decryption of each block does not depend on the previous block. It is also possible to decrypt only a desired portion of the encrypted string.

The cipher feedback operating mode 140 converts the block cipher to a self-synchronizing stream cipher. The operation mode of the cipher feedback operation mode 140 is similar to the electronic codebook operation mode 110, and in particular, the decryption mode is very similar to the reverse order of the electronic codebook operation mode 110 encryption.

The output feedback operating mode 150 converts the block cipher into a synchronous stream cipher. Because of the symmetry of the XOR instruction, the encryption and decryption methods are exactly the same.

The microprocessor 100 provides the flexibility to select the operating mode and the password according to the usage platform and situation by using the above five operation modes. In addition, since the master key is input from software, which is not stored in hardware, it has flexibility in terms of safety in that it can be easily corrected and updated when a key is leaked later.

In terms of design, it is also possible to implement the key schedule part of the algorithm of each symmetric key cryptosystem in software and to precompute each round key value in advance and send the calculated round key to the hardware. As a result, the key schedule computation process is deleted in the hardware, so that the area decreases and the speed increase effect can be expected.

Next, the GEZEL hardware co-processor 200 includes a GEZEL IP block 210, a data loader 220, a HIGHT hardware IP 230, a PRESENT hardware IP 240, and a PRINT cipher hardware IP 250.

The GEZEL IP block 210 is an IP block for communication provided by the GEZEL so that communication between the hardware and the software designed using the GEZEL can be easily performed. In the present invention, the microprocessor 100 and the GEZEL hardware co- ) In order to allow communication between them.

The data loader 220 is constituted by a memory inside the GEZEL hardware co-processor 200. The data loader 220 receives commands or data of the microprocessor 100 and stores the commands or data in advance in the data loader 200, So that a fast operation can be performed. Here, the data loader 220 plays an important role in the hardware, considering that the most influential part of latency in the hardware and software integrated design is the read / write data between the software and the hardware.

The HIGHT hardware IP 230 includes a HIGHT controller 231 and a HIGHT datapath 232 as a hardware IP using the HIGHT algorithm.

The HIGHT controller 231 defines each data path as a finite state machine and performs an arithmetic function using each of the data paths.

The HIGHT data path 232 includes a HIGHT_round-dp data path for performing the entire HIGHT encryption algorithm, a KEY expand data path for performing a key schedule, and a look-up table, And a delta data path storing a delta value used in a combination of F ₀ , F ₁ data paths and round subkeys.

In the above configuration, the HIGHT controller 231 performs optimization by considering the fact that the upper 64 bits and the lower 64 bits of the secret key inputted after using the 16 sub keys perform a cyclic left shift by 8 bits, respectively . That is, a key schedule can be performed after 4 rounds using 16 sub keys, and a retiming technique is applied to solve the problem of an increase in a critical path occurring in 4 rounds. Thereby reducing the delay of the critical path.

Here, an optimization method of the HIGHT controller 231 will be described with reference to FIG. FIG. 2 is a view showing the entire flow of a HIGHT finite state machine (FSM) according to an embodiment of the present invention, and is composed of a total of 8 states.

First, in the check start (310) state, it is checked whether communication between the communication module and the software is connected. If the connection is not established, the encryption is not started. If the connection is normally established and the plaintext and key are input from the communication module, the process proceeds to the next state.

Next, INIT (320) receives the plaintext and key from the external communication module and stores it in HIGHT internal register. And a state in which a register to be used during HIGHT encryption is initialized.

Next, in the pre-round (330) state, a whitening key is inserted into the plain text inputted before the beginning of the round.

Next, in Sub_Key (340) state, 8 sub keys are generated from the round key of HIGHT to be used in the second round. The sub key is generated by combining the output value of the delta data path and the current key.

Next, in the state of performing the round (350), 2 rounds are performed using the 8 generated subkeys, and the values are stored in the register. At this time, since the last round is different from the existing round, the final round performs a 32 round algorithm and outputs the value obtained by inserting the final whitening key. In this state, if the first two rounds of the third round are performed before starting the key schedule, the sub key is returned to the sub key (340) state in which the sub key is generated. If all four rounds have been performed, the key schedule is executed.

Next, in the Delta Change (360) state, delta_constant, which is an input value of the delta data path used for the sub key combination of the round, is updated and stored in the register.

Next, in the state of Key Schedule (370), left shift rotation of the upper 64 bits and the lower 64 bits of the current key is performed in the key register do.

Finally, in the FINISH (380) state, the ciphertext performed until the last round is transmitted to the external communication module. Then, reinitialize the register that indicates the start state of HIGHT.

The configuration of the HIGHT hardware IP 230 is confirmed as described above. Next, the PRESENT hardware IP 240 will be described.

The PRESENT hardware IP 240 includes a PRESENT controller 241 and a PRESENT data path 242 as a hardware IP using a PRESENT algorithm.

PRESENT controller 241 defines each data path as a finite state machine and performs operations using the respective data paths.

The PRESENT data path 242 includes a PRESENT_round_dp data path for performing the entire PRESENT cipher algorithm, four S-box data paths for processing input / output of S-boxes 0 to 3 in the form of a look-up table, The PRESENT cryptographic algorithm round function consists of three steps: AddRoundKey, S-box Layer, and Permutation Layer.

Since the PRESENT controller 241 implements the look-up table, which is a module requiring input and output of the S-box layer, as one data path, the PRESENT controller 241 declares the input values of the S-box layer as a register and outputs PRESENT_round_dp data Minimizing the delay between the path and the S-box datapath. Therefore, the S-box layer, the Permutation Layer, and the AddRoundKey of the next round are performed every cycle. This is because the value assigned to the register can be used in the next round, so it is efficient to divide the cycle around the S-box input. Also, since the register is divided into 8 bit units and XOR is performed with the secret key, it is more efficient than performing 64 bit unit XOR. Also, since round key values pre-processed by the key scheduling implemented on the microprocessor 100, which is software, are received and used, the hardware efficiency can be increased.

Here, an optimization method of the PRESENT controller 241 will be described with reference to FIG. FIG. 3 is a view showing the entire flow of a PRESENT finite state machine (FSM) according to one embodiment of the present invention, and is composed of a total of six states.

First, in Check start (410) state, check whether communication between communication module and software is connected. If connection is not established, encryption is not started. If the connection is normally established and the plaintext and the key value are input from the communication module, the procedure proceeds to the next state.

Next, in the INIT (420) state, the plaintext and the key value are input from the external communication module and stored in the PRESENT_round_dp internal register. And initialize the register to be used during encryption. Embodiments of the present invention are preferably configured such that the round-execution algorithm does not perform the first round AddRoundKey process, so it is preferable to perform the AddRoundKey in the initial register beforehand to store the result.

Next, in the round (430) state, the PRESENT round function is performed. The rounding algorithm is performed by storing the S-box layer, the Permutation Layer, and the AddRoundKey of the next round, and then dividing the result into eight 8-bit registers. This state is performed until the final round.

Next, in the Key schedule (440) state, each round key value received from the software is updated and the round constant ctr is increased. At this time, the key is stored in a register storing the key value.

Next, in the state of the S-box 450, a substitution operation suitable for the S-box configuration of the Present encryption algorithm is performed.

Finally, in the Finish (460) state, the ciphertext is transmitted to the external communication module when the final round is performed. Initialize the register that indicates the start state of PRESENT.

The configuration of the PRESENT hardware IP 240 is confirmed as described above. Next, the PRINTcipher hardware IP 250 will be described.

The PRINTcipher hardware IP 250 includes a PRINTcipher controller 251 and a PRINTcipher data path 252 as a hardware IP using the PRINTcipher algorithm.

The PRINTcipher controller 251 defines each data path as a finite state machine and performs operations using the respective data paths.

The PRINTcipher data path 252 is composed of a PRINTcipher_round_dp data path for performing the entire PRINTcipher encryption algorithm and four SP-box data paths for performing permutation and S-box substration in 3-bit units in the form of a look-up table .

In the above configuration, the PRINT cipher controller 251 reduces the total cycle by applying an unfolding technique so that the round function performs two rounds per cycle. Unfolding is a method of loosening the loop logic of a program and performing multiple operations at a time. In this case, since there is space consumption, the speed aspect and space efficiency should be considered.

Also, the PRINT cipher controller 251 does not process permutation and S-box substitution separately in the encryption process, and reduces the amount of computation by presetting the table as a single table. Therefore, Key XOR - Permutation - S - box Substitution, which is an existing structure of PRINTcipher, is composed by Key XOR - SP - box structure. When round operation is performed, register is placed before SP - box to make SP - box of current round, Key Configure XOR as one process. And to perform the process twice per cycle. Thus, the total execution cycle is reduced.

Further, the SP-box data path input value is declared as 16-bit 3-bit registers, and the key XOR process is performed in the SP-box data path. Accordingly, the key XOR process is divided into three bits rather than the 48-bit Key XOR process, thereby achieving efficiency in terms of speed.

Here, an optimization method of the PRINT cipher controller 251 will be described with reference to Fig. FIG. 4 is a diagram showing the entire flow of a PRINTcipher finite state machine (FSM) according to an embodiment of the present invention, and is composed of five states in total.

First, in the check start (510) state, it is checked whether communication of the communication module and the software is connected in the same manner as other encryption. If the connection is not established, encryption is not started. If the connection is normally established and the plaintext and the key value are input from the communication module, the procedure proceeds to the next state.

Next, in the INIT state (520), the plaintext and the key value are input from the external communication module and stored in the PRINTcipher_round_dp internal register. In this embodiment, the rounding algorithm of the PRINT cipher is configured not to perform the first Round Key XOR process, so the Key Round XOR is performed before storing in the initial register.

Next, in the 2R-Round (530) state, the PRINTcipher 2 round function is performed. Permutation - Design a 3-bit SP-box datapath with S-box substitution process in advance and perform Key XOR in the SP-box datapath.

In PRINTcipher_round_dp, the output value of the SP-box data path is received and the above process is performed twice per cycle, and two rounds are performed in one cycle.

Next, in the SP-box 540, a substitution and permutation operation indicating the characteristics of the PRINT cipher is performed.

Finally, in the Finish (550) state, the ciphertext is transmitted to the external communication module. Then initialize the register to indicate the start state of PRINTcipher.

The configuration of the microprocessor 100 and the GEZEL hardware co-processor 200 of the lightweight cryptographic apparatus capable of integrating hardware and software has been confirmed. Next, a communication method between the microprocessor 100 and the GEZEL hardware co-processor 200 will be described.

In the integrated design using GEZEL, the microprocessor 100 uses a memory mapped I / O scheme and a port mapped I / O scheme in communication with hardware input / output devices. The memory map input / output method does not separate input / output and memory address space in communication, and port map input / output method separates input / output circuit and memory address space. If the I / O circuitry is slower than the memory, there is speed and space efficiency when these two spaces are separated. In the embodiment of the present invention, the efficiency of speed and space is improved by using the port map input / output method when connecting the IP blocks. This does not limit the communication method of the present invention to the port map input / output method.

Processor 200 uses an improved handshake protocol between the microprocessor 100 and the GEZEL hardware co-processor 200 to increase reliability in communication between hardware and software. Once the communication is established, a done signal indicating that the communication has been completed is sent to check whether data can be exchanged. A communication method using the improved handshake protocol will be described in detail with reference to FIG.

5 is a flowchart illustrating a communication method using a handshake protocol according to an embodiment of the present invention.

First, the microprocessor 100 sends a first instruction and a second instruction to the GEZEL hardware co-processor 200, and the GEZEL hardware co-processor 200 receives the first instruction and the second instruction, Are performed in parallel at once (S10).

Next, the first complete signal of the first command received by the GEZEL hardware co-processor 200 and the first completed signal of the second command are transmitted to the microprocessor 100 (S20). The microprocessor 100 receiving the first completion signal generates a third instruction and a fourth instruction and stores the third instruction and the fourth instruction in the buffer (S30).

Next, the GEZEL hardware co-processor 200 transmits the first command received and the second completed signal of the second command to the microprocessor 100 (S40). The microprocessor 100 receiving the second completion signal transmits the third command and the fourth command stored in the buffer to the GEZEL hardware co-processor 200 (S50).

Thus, the communication method using the handshake protocol is confirmed. The GEZEL hardware co-processor 200 can exchange messages with the microprocessor 100 during encryption by repeatedly performing the above steps to perform communication.

According to the embodiments of the present invention described above, the present invention can be applied to an efficient encryption operation by being mounted on an IoT product, a RFID / USN, a smart card, etc. in which a lightweight password can be used, and a PRINTcipher lightweight password- And can be applied to various operation modes, so that it can be applied regardless of products and platforms.

The embodiments of the present invention described in the present specification and the configurations shown in the drawings relate to the most preferred embodiments of the present invention and are not intended to encompass all of the technical ideas of the present invention so that various equivalents It should be understood that water and variations may be present. Therefore, it is to be understood that the present invention is not limited to the above-described embodiments, and that various modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. , Such changes shall be within the scope of the claims set forth in the claims.

100: Microprocessor 110: Electronic codebook (ECB) operating mode
120: Cipher block chain (CBC) operation mode 130: Counter (CTR) operation mode
140: Password feedback (CFB) operation mode 150: Output feedback (OFB) operation mode
200: GEZEL hardware co-processor 210: GEZEL IP block
220: Data Loader 230: HIGHT Hardware IP
240: PRESENT hardware IP 250: PRINTcipher hardware IP

Claims (12)

A microprocessor according to a block cipher operation scheme; And
And a GEZEL hardware co-processor communicatively coupled to the microprocessor,
The GEZEL hardware co-
GEZEL intellectual property (IP) block; And
One or more hardware IPs operating in a finite state machine with datapath (FSMD) scheme using a datapath,
In the integrated design of the hardware and the software, the microprocessor calculates the round key value in advance by implementing the key schedule part of the symmetric key cryptographic algorithm in software, and sends the calculated round key to the hardware, By speeding up the process by omitting the process,
The microprocessor performs two instructions sequentially or in parallel when the microprocessor sends two instructions to the hardware in one cycle, the microprocessor receives a single completion instruction corresponding to the first instruction transmission from the hardware And an interface for transmitting and receiving a message during software and hardware operations during a cryptographic operation is implemented by reducing the waiting time of hardware operation during software operation after the first arithmetic cycle through communication for sending two commands back to the hardware in the next cycle A lightweight encryption device capable of integrated design of hardware and software. The method according to claim 1,
The microprocessor,
Characterized in that a block cipher is operated by selecting one of ECB, ECB, CBC, CTR, CFB, and OFB. Lightweight encryption device with integrated design. The method according to claim 1,
The one or more hardware IPs
A hardware IP of a lightweight encryption HIGHT technique, a hardware IP of a lightweight encryption PRESENT technique, and a hardware IP of a lightweight encryption PRINT cipher technique. The method of claim 3,
The hardware IP of the lightweight cryptographic HIGHT technique,
A HIGHT controller for defining and controlling each data path of the lightweight cryptographic HIGHT technique as a finite state machine;
A HIGHT_round_dp data path for performing a cryptographic algorithm of the lightweight cryptographic HIGHT technique;
A KEY expand data path that performs a key schedule;
F ₀ and F ₁ data paths having output values of the inner function in the form of a look-up table; And
And a delta data path for storing a delta value used for a combination of subkeys of the round. 5. The method of claim 4,
The HIGHT controller comprises:
After performing 4 rounds using 16 subkeys, perform key schedule,
Wherein a delay of a critical path is reduced by applying retiming for changing a position of a register in a round of 4 rounds. The method of claim 3,
The hardware IP of the lightweight encryption PRESENT technique,
A PRESENT controller for defining and controlling each data path of the lightweight PRESENT technique as a finite state machine;
A PRESENT_round_dp data path for performing the encryption algorithm of the lightweight encryption PRESENT scheme;
A plurality of S-box data paths for processing input and output in the form of a look-up table; And
And a key-box data path for use in key scheduling. The method according to claim 6,
Wherein the PRESENT controller comprises:
By using the look-up table to process an S-box requiring input and output as one data path and declaring the input values of the S-box layer as a register, it can be generated between the PRESENT_round_dp data path and the S- The delay is reduced,
Wherein the S-box layer, the Permutation Layer, and the AddRoundKey of the next round are performed for each cycle. The method of claim 3,
The hardware IP of the lightweight cryptographic PRINT cipher technique,
A PRINT cipher controller for defining and controlling each data path of the lightweight cryptographic PRINT cipher technique as a finite state machine;
A PRINTcipher_round_dp data path that performs the encryption algorithm of the lightweight cryptographic PRINT cipher technique; And
And a plurality of SP-box data paths for performing permutation and S-box substitution. 9. The method of claim 8,
The PRINT cipher controller includes:
The pre-processing part of permutation and S-box substitution according to PRINTcipher method is set in advance as one table,
Wherein the loop logic of the round operation to be repeatedly performed is reconfigured to apply unfolding to reduce a cycle by increasing the number of times of reading and writing data in each loop. Lightweight encryption device with integrated design. The method according to claim 1,
The microprocessor,
The integrated hardware and software design is connected to the GEZEL hardware co-processor I / O device using a memory mapped I / O scheme or a port mapped I / O scheme. Possible lightweight encryption device. The method according to claim 1,
The microprocessor,
Wherein a message is transmitted and received using a handshake protocol in which encryption and message transmission and reception are simultaneously performed in parallel with each other in communication with the GEZEL hardware co-processor. 12. The method of claim 11,
Wherein the microprocessor, for communication using the handshake protocol,
Wherein the microprocessor transmits a first instruction and a second instruction to the GEZEL hardware co-processor, the GEZEL hardware co-processor receives the first instruction and the second instruction and performs an operation sequentially or at a time in parallel and,
Wherein the first and second instructions received by the GEZEL hardware co-processor and the first completed signal of the first completed operation are transmitted to the microprocessor,
The microprocessor receiving the first completion signal generates a third instruction and a fourth instruction and stores the third instruction and the fourth instruction in a buffer,
The first instruction received by the GEZEL hardware co-processor and the second completed signal of a later completed operation of the second instruction to the microprocessor,
And the microprocessor that has received the second completion signal repeatedly transmits the third instruction and the fourth instruction stored in the buffer to the GEZEL hardware co-processor. Possible lightweight encryption device.

Images