KR101689458B1 - Semiconductor memory device and method for controlling semiconductor memory device - Google Patents

Semiconductor memory device and method for controlling semiconductor memory device Download PDF

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KR101689458B1
KR101689458B1 KR1020150035866A KR20150035866A KR101689458B1 KR 101689458 B1 KR101689458 B1 KR 101689458B1 KR 1020150035866 A KR1020150035866 A KR 1020150035866A KR 20150035866 A KR20150035866 A KR 20150035866A KR 101689458 B1 KR101689458 B1 KR 101689458B1
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semiconductor memory
memory device
memory request
row
request
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KR20160111122A (en
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전동익
정기석
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한양대학교 산학협력단
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

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Abstract

A semiconductor memory device and a semiconductor memory control method for controlling the number of access restrictions to a row buffer are disclosed. The disclosed semiconductor memory device control method includes: comparing a memory request frequency rate for the semiconductor memory device with a first threshold value; Dynamically adjusting the number of access restrictions to the row buffer according to the comparison result; And preferentially processing a memory request for the first row address within the adjusted number of accesses, in a row buffer for the first row address activated in response to the memory request.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a semiconductor memory control method, and more particularly, to a semiconductor memory device and a semiconductor memory control method for controlling the number of access restrictions to a row buffer.

The operation of a DRAM is basically divided into activation, precharge, read / write, and refresh. Prior to performing a read / write operation, the DRAM must first open a corresponding row to perform a read / write operation, and opening the corresponding row is referred to as activation. Activation causes the data of the cells belonging to the selected row to be loaded into a row buffer (or sense amplifier) and the read / write operation is performed through this row buffer. The pre-charge operation means to deactivate the row buffer activated by the activation operation for accessing another row.

Activation is relatively long compared to other DRAM operations and power consumption is also large, so the low buffer is managed as an open page or close page policy depending on the memory locality of the system . The open page policy keeps the open rows intact so that if the next read / write points to the same row, no activation is needed and latency and power consumption due to activation can be avoided. A close page policy is a policy that performs a precharge operation after a read / write operation, and is advantageous when the memory access pattern frequently points to another row.

The refresh operation is to read and rewrite the data at regular intervals in order to prevent the cell charges from leaking over time due to the characteristics of the DRAM.

A number of techniques have been studied to solve the performance bottleneck and large power consumption problems of DRAM, and the most widely used one is the open-page policy using low-buffer. Since the addresses of memory accesses in the real system have high locality, the first ready-first come first (FR-FCFS), which executes the instruction for the active low buffer among the commands queued in the command queue, serve scheduling can greatly improve the performance of the DRAM.

1 is a diagram for explaining a conventional semiconductor memory control method according to an open page policy and FR-FCFS scheduling.

The semiconductor memory device preferentially processes the memory request for the activated row buffer within the access limit number of the predetermined row buffer. The number of access restrictions for the row buffer is fixed at the time of the memory controller design, and may be fixed at 8, for example.

As shown in FIG. 1 (a), a memory request for a first row (row 1) address and a memory request for a second row (row 2) address are stored in a command queue, The semiconductor memory device preferentially processes the memory request for the first row (row 1) address within the access count.

Thus, even if the memory request for the second row (row2) address is located at the 5th and 6th positions, the semiconductor memory device continuously accesses the memory request for the first row (row1) address, as shown in Figure 2 (b) After processing eight times, it processes the memory request for the second row (row2) address. The semiconductor memory device deactivates the row buffer for the first row (row 1) address and activates the row buffer for the second row (row 2) address after processing the memory request for the first row (row 1) address, Processes the memory request for the second row (row2) address.

The present invention is to provide a semiconductor memory device and a semiconductor memory control method capable of optimizing performance and power consumption by dynamically adjusting the number of access restrictions to a row buffer.

According to an aspect of the present invention, there is provided a method of controlling a semiconductor memory device, the method comprising: comparing a memory request frequency rate of the semiconductor memory device with a first threshold value; Dynamically adjusting the number of access restrictions to the row buffer according to the comparison result; And preferentially processing a memory request for the first row address within the controlled access limit number, in a low buffer for a first row address activated in response to the memory request, to provide.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a frequency comparison unit comparing a memory request frequency rate of a semiconductor memory device with a first threshold value; A plurality of row buffers activated in response to the memory request; And an access restriction number adjuster for dynamically adjusting the access restriction count for the row buffer according to a result of the comparison, wherein, among the plurality of row buffers, the row buffer for the first row address is the first row address The memory access request is preferentially processed by the controlled access number.

According to another aspect of the present invention, there is provided a method for controlling a semiconductor memory device, the method comprising the steps of: dynamically adjusting a number of access restrictions to a row buffer using a memory request characteristic of the semiconductor memory device; ; Processing, in a low buffer for a first row address activated in response to the memory request, the memory request within a predetermined number of controlled accesses; And processing a memory request for the second row address in a row buffer for a second row address activated in response to the memory request after a memory request for the first row address has been processed. Control method.

According to the present invention, the performance of the semiconductor memory device can be improved by dynamically adjusting the number of access restrictions to the row buffer according to the memory request characteristic and preferentially processing the memory request within the controlled access count.

1 is a diagram for explaining a conventional semiconductor memory control method according to an open page policy and FR-FCFS scheduling.
2 is a diagram for explaining a semiconductor memory device control method according to the present invention.
3 is a diagram for explaining a semiconductor memory device control method according to an embodiment of the present invention.
4 and 5 are views for explaining a semiconductor memory device control method according to another embodiment of the present invention.
6 is a view for explaining a semiconductor memory device according to an embodiment of the present invention.
7 is a diagram for explaining a result of a semiconductor memory control method according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram for explaining a semiconductor memory device control method according to the present invention.

To prevent the low buffer from being unnecessarily activated, if the memory request for the currently active row buffer is not present in the commit queue, or exceeds the access limit for the row buffer, the memory controller deactivates the row buffer .

At this time, the performance and the power consumption of the semiconductor memory device vary depending on the memory request characteristic of the application. For example, in the case of an application having a large number of memory requests per unit time, since there are many commands in the command queue, the time during which the row buffer is activated becomes long, and accordingly, a large amount of power can be consumed for the improved performance of the semiconductor memory device . On the contrary, in the case of an application having a small memory request per unit time, the command queue is often empty, and the time for which the row buffer is inactivated becomes long, so that the power consumption of the semiconductor memory device can be reduced.

FIG. 2 (a) shows an experimental result of an mcf benchmark with a relatively high memory request frequency among the SPEC CPU2006 benchmarks, and FIG. 2 (b) shows an experimental result of a hmmer benchmark with a low memory request frequency in the same environment do. 2, the PDP represents the performance of the semiconductor memory device as a product of a power consumption value and a latency value. In an environment where the power and speed of the semiconductor memory device must be taken into consideration, it can be judged that the performance of the semiconductor memory device is superior as the PDP value is smaller.

As shown in FIG. 2, when the frequency of the memory request is high, the PDP value tends to decrease as the number of access restrictions decreases. When the frequency of the memory request is low, the PDP value tends to decrease as the access restriction frequency increases.

As a result, when the number of access restrictions is set dynamically according to the memory request characteristics, the performance of the semiconductor memory device can be improved. In the present invention, the memory access request is processed in the low buffer by setting the access restriction number as dynamic Method.

According to the present invention, the performance of the semiconductor memory device can be improved by dynamically adjusting the number of access restrictions to the row buffer according to the memory request characteristic and preferentially processing the memory request within the controlled access count. More specifically, the present invention can dynamically adjust the number of access restrictions according to a memory request rate or a row buffer hit rate for a memory request.

Here, the memory request frequency rate represents the frequency of the memory request for a predetermined time, and may be the frequency of the memory request for one cycle of the operation clock of the semiconductor memory device as an embodiment.

The low buffer hit ratio represents the ratio of the number of consecutive accesses to the active low buffer and the total number of memory requests since the low buffer is activated. For example, if the total memory request is 5 for the first row address, 3 for the second row address, and 2 for the third row address, then the row buffer for the first row address is After activation, four memory requests can be processed consecutively, so the low buffer hit rate in this case is 0.7 ((4 + 2 + 1) / 10). That is, the present invention can control the number of access restrictions according to the frequency of memory requests for the same row address during a memory request.

The semiconductor memory device according to the present invention may be a DRAM, an DDR DRAM, a mobile DRAM, or any type of DRAM. Memory requests also include all memory requests associated with the low buffer, such as activation, read / write, precharge, and refresh.

3 is a flowchart of a semiconductor memory device control method according to an embodiment of the present invention.

The semiconductor memory device according to the present invention dynamically adjusts the number of access restrictions to the row buffer according to a memory request characteristic of the semiconductor memory device (S310). More specifically, the number of access restrictions may be adjusted according to the frequency rate of the memory request or the low buffer hit rate for the memory request. Depending on the embodiment, the semiconductor memory device may adjust the frequency of access requests by the frequency of the memory request or by the low buffer hit rate, or by using both the memory request frequency rate and the low buffer hit rate.

In step S310, the number of access restrictions may be made through a comparison of the frequency of the memory request or the low buffer hit rate with the threshold, which will be described in more detail in FIG.

The semiconductor memory device preferentially processes the memory request within the controlled access count number (S320) in the low buffer for the first row address activated in response to the memory request. Depending on the memory request, the row buffer is activated to receive data from the cell array or to transfer data to the cell array. Alternatively, the stored data can be output to the DQ pad.

After the memory request for the first row address is processed, the semiconductor memory device processes (S330) a memory request for the second row address in the row buffer for the activated second row address according to the memory request.

Here, the first row address and the second row address indicate different row addresses from each other, and do not refer to a specific row address.

4 and 5 are views for explaining a semiconductor memory device control method according to another embodiment of the present invention.

The semiconductor memory device according to the present invention compares the memory request frequency rate with respect to the semiconductor memory device and the first threshold value at step S410 and dynamically adjusts the access frequency limit to the row buffer according to the comparison result at step S420. do.

In step S420, as the memory request frequency rate increases, the access restriction frequency may decrease. More specifically, when the memory request frequency rate is less than the first threshold value, the semiconductor memory device determines the first access frequency limit, When the requested frequency rate is equal to or greater than the first threshold value, the access limit frequency can be determined as the second frequency that is equal to or less than the first frequency.

In this case, the second number of times may be determined by subdivision according to the low buffer hit rate, and more specifically, the semiconductor memory device may determine the second number by comparing the low buffer hit rate with the second threshold value for the memory request. The second number of times can be determined by comparing the second threshold value with the low buffer hit rate.

The number of access restrictions according to the present invention can be adjusted as shown in Table 1 as an embodiment. That is, if the memory request frequency rate is less than 0.05, the first number may be determined as 31. If the memory request frequency rate is 0.05 or more, the second number may be determined between 1 and 31 according to the low buffer hit rate.

Memory request characteristics Number of access restrictions 0.05

Figure 112015025290840-pat00001
Memory request frequency rate 80%
Figure 112015025290840-pat00002
Row buffer hit rate One 60%
Figure 112015025290840-pat00003
Row buffer hit rate <80% 9 40%
Figure 112015025290840-pat00004
Row buffer hit rate <60% 16 20%
Figure 112015025290840-pat00005
Row buffer hit rate <40% 23 Row buffer hit rate <20% 31 Memory request rate <0.05 31

The semiconductor memory device preferentially processes the memory request for the first row address within the controlled access count number (S410) in the row buffer for the first row address activated in response to the memory request. In one embodiment, if the memory request includes a request for a first row address and a request for a second row address, then the semiconductor memory device may, after the memory request for the one row address has been processed, And process the memory request for the second row address in the row buffer.

For example, if the memory request frequency rate is greater than 0.05 and memory requests for the first row address row1 are discontinuously 10 and the second row address row2 is stored in the command queue, If four memory requests are stored discretely, the low buffer hit rate is about 70%, so the number of access restrictions is adjusted to 9. At this time, the semiconductor memory device preferentially processes consecutively the nine memory requests for the first row address (row1) in the row buffer for the activated first row address row1. And processes the four memory requests for the second row address row2 by activating the row buffer for the second row address row2.

If, according to an embodiment, the number of access restrictions is adjusted to 16, the semiconductor memory device may preferentially process all 10 memory requests for the first row address and process the memory request for the second row address.

6 is a view for explaining a semiconductor memory device according to an embodiment of the present invention.

6, the semiconductor memory device according to the present invention includes a frequency ratio comparing unit 610, a plurality of row buffers 620, and an access restriction number adjusting unit 630, The operation can be performed according to the semiconductor memory control method.

The frequency ratio comparing unit 610 compares the memory request frequency rate with respect to the semiconductor memory device and the first threshold value and the access restriction number adjusting unit 630 compares the access request rate with respect to the access request to the low buffer 620 Dynamically adjusts the number of times. That is, the memory controller including the frequency ratio comparing unit 610 and the access restriction number adjusting unit 630 dynamically adjusts the access restriction number according to the memory request characteristic.

The row buffer 620 is activated in response to a memory request. Of the plurality of row buffers, the row buffer 621 for the first row address preferentially processes the memory request for the first row address by a controlled access count.

More specifically, the access-restriction-number adjusting unit 630 includes a first-number determining unit for determining the number of access restrictions as a first number when the memory request frequency rate is less than a first threshold, and a first- A second number of times determining unit for determining the number of times of access restriction as a second number of times equal to or less than the first number of times.

The second number determination unit compares the second threshold value with the low buffer hit rate for the memory request to determine the second number or determines the second number according to the frequency of the memory request for the same row address during the memory request .

In one embodiment, if the memory request includes a request for a first row address and a request for a second row address, the row buffer 622 for the second row address, among the plurality of row buffers, After the memory request for the second row address is processed, the memory request for the second row address can be processed.

According to the embodiment, the frequency ratio comparing unit 610 and the access limitation number adjusting unit 630 may be included in a separate semiconductor memory controller.

7 is a diagram for explaining a result of the semiconductor memory control method according to the present invention. The average PDP value (DRBAL) of the dynamic access restriction number adjustment result for the SPEC CPU2006 benchmark and the fixed access restriction And the average PDP value (conventional) when the number of times is used.

Table 2 shows the average PDP value according to the present invention in the benchmark used and the PDP value according to the fixed access restriction number.

Benchmark conventional DRBAL One 3 5 7 9 11 21 23 25 27 29 31 bzip2 121.6 150.7 159.0 162.5 167.5 170.9 172.8 172.1 174.0 175.2 174.9 173.4 151.8 hmmer 316.6 293.4 286.2 282.3 282.9 284.2 284.3 283.7 283.3 283.3 281.9 281.0 281.3 lbm 13.6 15.4 16.1 16.8 17.2 17.6 17.9 17.9 18.6 18.0 18.1 18.2 16.1 sjeng 17.9 19.9 20.7 21.5 22.1 22.6 23.3 23.8 23.3 23.6 22.9 23.0 20.1 mcf 8.3 9.3 9.7 10.0 10.3 10.6 10.9 11.1 11.0 11.0 10.7 10.7 9.4 gobmk 8.7 9.6 10.0 10.4 10.7 11.0 11.3 11.5 11.4 11.4 11.1 11.2 9.8

As shown in FIG. 7, the average PDP value according to the present invention is about 81.4, which means that the PDP value decreases by about 5% on the average of all access limit times. As a result, according to the present invention, Can be improved and optimized.

The above-described technical features may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and specific embodiments and drawings. However, it should be understood that the present invention is not limited to the above- And various modifications and changes may be made thereto by those skilled in the art to which the present invention pertains. Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (13)

A method for controlling a semiconductor memory device,
Comparing a memory request frequency rate for the semiconductor memory device with a first threshold value;
Dynamically adjusting the number of access restrictions to the row buffer according to the comparison result; And
In a low buffer for a first row address activated in response to a memory request for the semiconductor memory device, preferentially processing a memory request for the first row address within the controlled access count
And controlling the semiconductor memory device.
The method according to claim 1,
The step of dynamically adjusting the access restriction number
Determining the access restriction number as a first number when the memory request frequency rate is less than the first threshold value; And
Determining a second number of times of the access restriction number equal to or less than the first number when the memory request frequency rate is equal to or greater than the first threshold value
And controlling the semiconductor memory device.
3. The method of claim 2,
Wherein the step of determining the access restriction number as the second number
Comparing a low buffer hit rate for the memory request with a second threshold; And
Determining the second number of times according to the comparison result,
And controlling the semiconductor memory device.
3. The method of claim 2,
Wherein the step of determining the access restriction number as the second number
Determining the second number of times of the memory request according to the frequency of memory requests for the same row address
A method of controlling a semiconductor memory device.
The method according to claim 1,
The memory request
A request for the first row address and a request for a second row address,
The semiconductor memory device control method
Processing a memory request for the second row address in a row buffer for the second row address after a memory request for the first row address is processed
Further comprising the steps of:
The method according to claim 1,
The memory request frequency rate
During one cycle of the operating clock of the semiconductor memory device, the frequency of the memory request
A method of controlling a semiconductor memory device.
A semiconductor memory device comprising:
A frequency comparing unit comparing a memory request frequency rate with respect to the semiconductor memory device and a first threshold value;
A plurality of row buffers activated in response to a memory request for the semiconductor memory device; And
And an access restriction number adjusting unit for dynamically adjusting the access restriction number for the row buffer according to the comparison result,
Wherein a row buffer for a first row address among the plurality of row buffers preferentially processes a memory request for the first row address by the adjusted access limit number.
8. The method of claim 7,
The access restriction number adjusting unit
A first number determining unit that determines the access restriction number as a first number when the memory request frequency rate is less than the first threshold value; And
Determining a second number of times of the access restriction number equal to or less than the first number of times when the memory request frequency rate is equal to or greater than the first threshold value,
And a semiconductor memory device.
9. The method of claim 8,
The second number determining unit
Comparing the low buffer hit rate for the memory request with a second threshold, and determining the second number
Semiconductor memory device.
9. The method of claim 8,
The second number determining unit
Determining the second number of times of the memory request according to the frequency of memory requests for the same row address
Semiconductor memory device.
8. The method of claim 7,
The memory request
A request for the first row address and a request for a second row address,
Of the plurality of row buffers, the row buffer for the second row address is
After the memory request for the first row address is processed, a memory request for the second row address is processed
Semiconductor memory device.
A method for controlling a semiconductor memory device,
Dynamically adjusting the number of accesses to the row buffer according to a memory request characteristic of the semiconductor memory device;
Processing, in a low buffer for a first row address activated in response to a memory request for the semiconductor memory device, the memory request within a predetermined number of controlled accesses; And
Processing a memory request for the second row address in a row buffer for a second row address activated in response to the memory request after a memory request for the first row address is processed
And controlling the semiconductor memory device.
13. The method of claim 12,
The step of dynamically adjusting the access restriction number
The number of access restrictions is adjusted by using the frequency rate of the memory request or the low buffer hit rate for the memory request
A method of controlling a semiconductor memory device.
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