KR101688870B1 - Apparatus and method for delay based physically unclonable fuction of semiconductor chip - Google Patents

Abstract

An apparatus for discriminating physical semiconductor chip duplication based on a delay time is provided. The apparatus for discriminating physical semiconductor chip duplication based on a delay time according to an embodiment of the present invention includes a power applying part for outputting an input voltage corresponding to the near threshold voltage of a MOSFET having a predetermined clock; a delay part for receiving the output of the power applying part and arranging a plurality of delay lines of a logic gate, and outputting a plurality of delay output voltages in parallel; a multiplexer for selecting two of the delay output voltages and outputting a selected output voltage; and a comparator for comparing the two selected output voltages of the multiplexer. So, a delay time feature can be more accurately determined.

Description

[0001] APPARATUS AND METHOD FOR DELAY BASED PHYSICALLY UNCLONABLE FUNCTION OF SEMICONDUCTOR CHIP [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for discriminating a duplication of a semiconductor chip, and more particularly, to a delay time-based discrimination apparatus and method using a near threshold voltage of a MOSFET.

Due to the development of the Internet of things, many devices are connected to the Internet, and as the number of personal mobile devices increases, the demand for semiconductor chips increases, and semiconductor chips are illegally copied and used. Therefore, studies are being made to prevent such duplication of semiconductor chips.

Since the physical duplication discriminator implemented using the conventional ring oscillator operates with the normal supply voltage, it is difficult to distinguish the difference between the delay lines where the delay time occurs and the delay time characteristics of the semiconductor chip There is a problem that it is difficult to discriminate the unique bit to be represented. Also, the power consumed due to the high supply voltage is large.

Therefore, a copy discrimination apparatus using a logic gate has been attracting attention to solve such a problem. The replication discrimination device based on the delay time generated when the pseudo threshold voltage is applied to the MOSFET constituting the logic gate has a larger deviation from the delay time between the delay lines and even when the replication discrimination device is disclosed, It is virtually impossible to duplicate the same semiconductor chip. Therefore, a physical duplication discrimination apparatus implemented using a logic gate is more suitable for discrimination and prevention of duplication of a semiconductor chip.

Relevant prior arts include Registered Patent Publication No. 10-0380573 entitled " Delayed Clock Generator & Delay Time Measurement Apparatus ", published on December 26, 2000.

The present invention relates to a semiconductor chip duplication discrimination apparatus and method by constructing a delay line using a pseudo threshold voltage of a MOSFET in order to further increase the inherent delay time of the semiconductor chip, .

 In order to achieve the above object, a delay time-based physical semiconductor chip duplication discrimination device provided in the present invention is a device for discriminating the semiconductor chip duplication based on a delay time, ; A delay unit receiving a plurality of delay lines, each of which is implemented by at least one logic gate, arranged in parallel to receive the output of the power applying unit and output a plurality of delay output voltages; A multiplexer for selecting two of the plurality of delay output voltages and outputting the selected output voltage; And a comparator for comparing the two selected output voltages of the mux.

Preferably, the method further comprises: generating a unique bit that is a delay characteristic inherent to the semiconductor chip based on the output result of the comparator, comparing the generated unique bit with a unique bit corresponding to an ID of the semiconductor chip generated in advance, And a discrimination unit for discriminating whether or not the semiconductor chip is duplicated.

Advantageously, the discriminator may comprise at least one of a memory and a register.

Preferably, the delay output voltage may be output differently for all or a part of the delay lines among the plurality of parallelly arranged delay lines.

Preferably, when the plurality of delayed parallel lines are classified into a first delayed line group and a second delayed line group including at least one delayed line, the muxes are divided into the first delayed line group and the second delayed line group, One delay line can be selected from each of the delay line groups.

Preferably, when the first delay line group and the second delay line group each include sixteen delay lines, a unique bit which is inherent delay characteristic of the semiconductor chip is divided into the first delay line group and the second delay line group, And a 256-bit value generated through 256 combinations of selecting one of the delay lines in each of the two delay line groups.

Advantageously, the logic gate can be implemented using the MOSFET wherein a delay occurs in the output when the pseudo-threshold voltage is applied.

Advantageously, the logic gate may be a NAND gate having four inputs implemented using the MOSFET.

The power applying unit may include a voltage level converting unit that converts a voltage of an input clock signal into an input voltage corresponding to the pseudo threshold voltage.

Advantageously, said comparator can be a D-flip flop.

According to another aspect of the present invention, there is provided a method of discriminating physical duplication based on delay time, comprising: outputting an input voltage corresponding to a near threshold voltage of a MOSFET having a predetermined clock; Outputting a plurality of delayed output voltages by arranging a plurality of delay lines, which are implemented as at least one logic gate, in parallel with the output of the input voltage; Selecting two of the plurality of delay output voltages and outputting the selected output voltage; And comparing the two selected output voltages.

Preferably, the method further comprises the steps of: generating a unique bit that is inherent delay characteristic of the semiconductor chip based on the comparison result; comparing the generated unique bit with a unique bit corresponding to an ID of the semiconductor chip generated in advance, And a step of discriminating whether or not the information is reproduced.

Preferably, the delay output voltage may be output differently for all or a part of the delay lines among the plurality of parallelly arranged delay lines.

Preferably, when the plurality of delay lines arranged in parallel are classified into a first delay line group and a second delay line group including at least one delay line, the step of selecting and outputting the two delay lines includes: The delay line group, and the second delay line group, respectively.

Advantageously, the logic gate can be implemented using the MOSFET wherein a delay occurs in the output when the pseudo-threshold voltage is applied.

Since the present invention uses a pseudo threshold voltage of a MOSFET, a larger delay time deviates while consuming less power than a technology using a conventional ring oscillator, and a unique delay time characteristic for each semiconductor chip can be discriminated more accurately .

In addition, the present invention has an effect of distinguishing a duplicated semiconductor chip by an unjustifiable method using the inherent delay time characteristic of each semiconductor chip.

FIG. 1 is a diagram illustrating a semiconductor chip duplication discriminating apparatus according to an embodiment of the present invention. Referring to FIG.
2 is a diagram illustrating a semiconductor chip duplication discriminating apparatus according to another embodiment of the present invention.
3 is a diagram illustrating a method of discriminating a semiconductor chip duplication according to an embodiment of the present invention.
4 is a diagram for explaining the output of the comparator.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a view for explaining a semiconductor chip duplication discriminating apparatus according to an embodiment of the present invention, and FIG. 2 is a view for explaining a semiconductor chip duplicating discriminating apparatus according to another embodiment of the present invention.

Referring to FIG. 1, the semiconductor chip duplication / discrimination apparatus 100 includes a power application unit 110, a delay unit 120, a mux 130, and a comparator 140. In addition, it may further include a copy discrimination unit (not shown).

The power applying unit 110 outputs an input voltage corresponding to a near threshold voltage of a MOSFET having a predetermined clock.

Referring to FIG. 1, when the clock signal CK_IN is input to the power applying unit 110, the power applying unit 110 outputs the input clock signal as an input voltage. At this time, it is assumed that the clock signal has a voltage magnitude corresponding to the pseudo threshold voltage.

Here, the MOSFET is a metal-oxide-semiconductor field-effect transistor. The threshold voltage of the MOSFET means a minimum voltage for operating the transistor. If a similar threshold voltage that is close to but not equal to the threshold voltage is applied, a delay occurs when the MOSFET operates, The time may vary for each MOSFET.

In another embodiment, the clock signal CK_IN may not have a pseudo threshold voltage. In this case, as shown in FIG. 2, the voltage of the clock signal input to the power applying unit 110 itself may be set to a value corresponding to the pseudo threshold voltage A voltage level converting unit 210 for converting the voltage into a voltage and outputting the voltage may be used.

However, in another embodiment, the voltage level converting unit 210 may be further included in the power applying unit 110. In this case, when the voltage of the clock signal applied to the power applying unit 110 is a pseudo threshold voltage, the power applying unit 110 directly outputs the clock signal as the input voltage, It is possible to convert the voltage of the clock signal into a voltage corresponding to the pseudo threshold voltage through the voltage level converting unit 210 mounted in the power applying unit 110. The delay unit 120 A plurality of delay lines 121, which are implemented as at least one logic gate, are arranged in parallel to receive a plurality of output signals from the power application unit 110 and output a plurality of delay output voltages.

Here, the logic gate is a logic operation circuit mainly implemented by using a MOSFET, and its types include AND, OR, NOT, NAND, NOR, XOR, and XNOR gates.

For example, the delay line 121 may be implemented as a delay line 221 in which six NAND gates are serially connected as shown in FIG. In this case, the NAND gate is a NAND gate implemented using a MOSFET, and when the pseudo threshold voltage mentioned above is applied, a delay time may vary in each NAND gate during operation. 32 delay lines 121 may be arranged in parallel to constitute the delay unit 120. The input of each delay line 121 may be connected to the output of the power application unit 110. [

On the other hand, the delay output voltage refers to a voltage that is delayed and output while passing through the delay line, and there is one delay output voltage per delay line.

In another embodiment, the logic gate used in the delay unit 120 may be a NAND gate with four inputs.

This is because a NAND gate with four inputs has a larger number of stacked MOSFETs in the vertical direction than a NAND gate with two inputs, resulting in a larger deviation in delay time.

The mux 130 selects two delayed output voltages of a plurality of delay lines 121 arranged in parallel and outputs the selected output voltage.

Here, the selective output voltage means two delay output voltages selected from a plurality of delay output voltages.

For example, when the mux 130 is connected to the output of the delay unit 120 including the 32 delay lines 121, the mux 130 is connected to the two selected delay lines 121, Quot; output "

The comparator 140 outputs the result of comparing the two selected output voltages of the mux 130.

Here, the comparator 140 compares the magnitudes of the two output voltages to output a signal for informing what is larger.

For example, the two output voltages of the mux 130 may have different delay times while the same input voltage passes through different delay lines 121. [ Accordingly, when the remaining output value is larger than any of the two selected output voltages, the comparator 140 outputs 1 (high), and when it is smaller, it outputs 0 (low). At this time, the delay line 121 as a reference for comparison may be determined as a delay line 121 having a lower serial number assigned to each of the plurality of delay lines 121 arranged in parallel.

In another embodiment, the comparator 140 may be a D-flip-flop 240 as in FIG.

For example, referring to FIG. 2, the D flip-flop 240 determines whether the value of the other input is 1 (high) or 0 (low) on the rising edge based on any one of the two inputs The output value of the D flip-flop 240 is determined to be either 1 (high) or 0 (low), and the determined value can be maintained until the next comparison.

More specifically, since the two output inputs of the D flip-flop 240 are clock signals having the same frequency but having different delay levels, if the first comparison result is 1 (high) The output of the result can always be 1 (high). This is because the D-flip-flop 240 determines the output value based on one rising edge of the two inputs and maintains the result until the next rising edge.

For example, with reference to FIG. 4, with respect to the rising edge timing (t = t1, t2, t3, t4, ...) of the delay line B among the two input output voltages of the D flip- 1 (high), which is the output of the delay line A at each time, can be determined as the output of the D-flip-flop 240. [

Based on the output of the comparator 140, the duplication distinguishing unit (not shown) generates a unique bit which is inherent delay characteristic of the semiconductor chip, and generates a unique bit corresponding to the ID of the semiconductor chip And discriminates whether or not the semiconductor chip is duplicated.

Here, the inherent bit of the semiconductor chip is a value indicating a unique delay characteristic caused by a difference in delay time between each delay line 121 included in the delay unit 120 of the semiconductor chip, Can be identified.

For example, when a delay unit 120 including 32 delay lines 121 is present, the inherent code of the semiconductor chip has 256 combinations of selecting two delay lines 121 out of the 32 delay lines 121 And 256 bits can be generated using the 256 comparison results of the comparator 140 corresponding to the setting of the mux 130. In this case,

More specifically, when a unique bit generated for a specific semiconductor chip is compared with a unique bit corresponding to an ID of the semiconductor chip generated in advance, the semiconductor chip can be determined as a duplicated semiconductor chip. This is because even if somebody can duplicate the semiconductor chip to have the same function as the genuine semiconductor chip, it is not possible to duplicate the same to the delay line 121 of the delay unit 120 to generate the same unique bit to be.

In addition, unique bits corresponding to the IDs of the semiconductor chips are generated in advance in the production stage of the semiconductor chips, selectively encrypted in the nonvolatile memory, or stored in a separate server connected via a network, It can be configured to be stored and inquired.

In another embodiment, the duplication distinguishing unit (not shown) may include at least one of a memory and a register.

For example, the copy discrimination unit (not shown) may store the output result of the comparator 140 in one of the memory and the register when generating the unique bit of the semiconductor chip, and then generate the unique bit using the result stored later .

In another embodiment, the delay output voltage may be output differently for all or a part of the delay lines among the plurality of delay lines 121 arranged in parallel in the delay unit 120.

For example, if there are thirty-two delay lines 121 in the delay unit 120, a delay for a pseudo threshold voltage of a MOSFET in a logic gate included in each delay line for all or a part of all the delay lines, Different delay output voltages may be output depending on the characteristics.

In another embodiment, when a plurality of delay lines 121 arranged in parallel in the delay unit 120 are classified into a first delay line group and a second delay line group including at least one delay line 121, The second delay line group 130 may select one delay line 121 in each of the first delay line group and the second delay line group.

For example, the delay line 121 may be divided into a first delay line group and a second delay line group, which are divided into upper half and lower half according to the arranged positions of the plurality of delay lines 121 arranged in parallel. When the two delay lines 121 are selected, the mux 130 may select one of the first delay line group and the second delay line group, respectively.

In another embodiment, when the first delay line group and the second delay line group each include sixteen delay lines 121, the inherent bits, which are unique delay characteristics of the semiconductor chip, And a 256-bit value generated through 256 combinations of selecting one delay line 121 in each of the two delay line groups.

For example, when the first delay line group and the second delay line group each include 16 delay lines 121, the first delay line group and the delay line 121 belonging to the second delay line group are overlapped The number of all cases that can be paired is 16 * 16 = 256, so that a 256-bit unique code can be generated.

As described above, the semiconductor chip duplication discrimination apparatus according to an embodiment of the present invention generates a unique code, which is a characteristic of delay time inherent to each semiconductor chip, and compares it with a unique code corresponding to the ID of the semiconductor chip stored in advance, It is possible to discriminate whether or not the semiconductor chip is copied.

3 is a diagram illustrating a method of discriminating a semiconductor chip duplication according to an embodiment of the present invention.

In step S310, the power applying unit 110 outputs an input voltage corresponding to a pseudo threshold voltage of a MOSFET having a predetermined clock.

In step S320, the delay unit 120 having a plurality of delay lines arranged in parallel with at least one logic gate, receiving the input voltage from the power applying unit 110, outputs a plurality of delay output voltages.

In step S330, the MUX 130 selects two of the plurality of delayed output voltages and outputs the selected output voltage.

Finally, in step S340, the comparator 140 compares the two selected output voltages.

In another embodiment, the copy discrimination unit (not shown) can discriminate whether or not the semiconductor chip is copied using the unique bit of the semiconductor chip generated based on the output result of the comparator 140.

That is, the duplication discriminating unit (not shown) generates a unique bit indicating a delay characteristic inherent to the semiconductor chip based on the comparison result of the comparator 140, and generates a unique bit corresponding to the ID of the semiconductor chip It is possible to distinguish whether the semiconductor chip is copied or not by comparing the corresponding unique bit.

In another embodiment, a delay output voltage may be output differently for all or a part of the delay lines 121 among a plurality of delay lines 121 arranged in parallel.

In another embodiment, when a plurality of delay lines 121 arranged in parallel are classified into a first delay line group and a second delay line group including at least one delay line 121, It is possible to select and output one delay line 121 in each of the delay line group and the second delay line group.

In another embodiment, the logic gate may be implemented using the MOSFET where a delay occurs in the output when a pseudo-threshold voltage is applied.

The above-described embodiments of the present invention can be embodied in a general-purpose digital computer that can be embodied as a program that can be executed by a computer and operates the program using a computer-readable recording medium.

The computer readable recording medium includes a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), optical reading medium (e.g., CD ROM, DVD, etc.).

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (15)

A power supply unit for outputting an input voltage corresponding to a near threshold voltage of a MOSFET having a predetermined clock;
A delay unit receiving a plurality of delay lines, each of which is implemented by at least one logic gate, arranged in parallel to receive the output of the power applying unit and output a plurality of delay output voltages;
A multiplexer for selecting two of the plurality of delay output voltages and outputting the selected output voltage;
A comparator for comparing the two selected output voltages of the mux; And
Generating a unique bit which is a delay characteristic inherent to the semiconductor chip based on an output result of the comparator, comparing the generated unique bit with a unique bit corresponding to an ID of the semiconductor chip generated in advance, A duplication discrimination unit
Wherein the delay time-based physical semiconductor chip duplication discrimination apparatus comprises: delete The method according to claim 1,
The copy discrimination unit
Memory, and / or a register. The apparatus of claim 1, The method according to claim 1,
Wherein the delay output voltage is output differently for all or a part of the delay lines among the plurality of delay lines arranged in parallel. The method according to claim 1,
When the plurality of delay lines arranged in parallel are classified into a first delay line group and a second delay line group including at least one delay line,
The mux
Wherein the delay line selection unit selects one delay line in each of the first delay line group and the second delay line group. 5. The method of claim 4,
When the first delay line group and the second delay line group each include 16 delay lines,
The inherent bit, which is the inherent delay characteristic of the semiconductor chip,
Wherein the first delay line group and the second delay line group are 256-bit values generated through 256 combinations of selecting one delay line in each of the first delay line group and the second delay line group. The method according to claim 1,
The logic gate
And a delay occurs in an output when the pseudo threshold voltage is applied to the semiconductor chip. The method according to claim 1,
The logic gate
Wherein the NAND gate is a NAND gate having four inputs implemented using the MOSFET. The method according to claim 1,
The power applying unit
And a voltage level converting unit for converting a voltage of an input clock signal into an input voltage corresponding to the pseudo threshold voltage. The method according to claim 1,
The comparator
D-flip-flop. Outputting an input voltage corresponding to a pseudo threshold voltage of a MOSFET having a predetermined clock;
Outputting a plurality of delay output voltages through a delay unit having a plurality of delay lines arranged in parallel with at least one logic gate and receiving the output voltage;
Selecting two of the plurality of delay output voltages and outputting the selected output voltage;
Comparing the two selected output voltages; And
Generating unique bits that are unique delay characteristics of the semiconductor chip based on the comparison result, comparing the generated unique bits with unique bits corresponding to the IDs of the semiconductor chips generated in advance, Step
And determining whether or not the semiconductor chip is a semiconductor chip. delete 12. The method of claim 11,
Wherein the delay output voltage is output differently for all or a part of the delay lines among the plurality of delay lines arranged in parallel. 12. The method of claim 11,
When the plurality of delay lines arranged in parallel are classified into a first delay line group and a second delay line group including at least one delay line,
The step of selecting and outputting the two
And selecting one of the delay lines in the first delay line group and the second delay line group, respectively. 12. The method of claim 11,
The logic gate
And the output is delayed when the pseudo threshold voltage is applied to the semiconductor chip.

Images