KR101679509B1 - Memory, operation method of memory, power control device and power control method in space radiation environment - Google Patents

Memory, operation method of memory, power control device and power control method in space radiation environment Download PDF

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KR101679509B1
KR101679509B1 KR1020150050136A KR20150050136A KR101679509B1 KR 101679509 B1 KR101679509 B1 KR 101679509B1 KR 1020150050136 A KR1020150050136 A KR 1020150050136A KR 20150050136 A KR20150050136 A KR 20150050136A KR 101679509 B1 KR101679509 B1 KR 101679509B1
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power
node
scrubbing
static ram
bit error
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KR20160120935A (en
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장익준
김진상
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경희대학교 산학협력단
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Abstract

The present invention relates to a method and system for determining a bit error rate (BER) for each node in a memory operating in a standby mode, a second acquiring unit for acquiring a scrubbing rate corresponding to the optimized scrubbing rate and a minimum value of a standby power including leakage power corresponding to a scrubbing power and a leakage current corresponding to the optimized scrubbing rate, A memory, a method of operating a memory, a power control apparatus, and a power control method in a radio environment including a control unit are disclosed.

Description

TECHNICAL FIELD [0001] The present invention relates to a memory, an operation method of a memory, a power control apparatus, and a power control method in a radioactive environment,

The present invention relates to a memory, a method of operating a memory, a power control apparatus, and a power control method suitable for a radioactive environment, for example, a space radiation environment, and more particularly, A method of operating a memory, a power control apparatus, and a power control method in a radioactive environment.

Static random access memory (SRAM) is an arbitrary access storage device having a memory bit-cell of a flip-flop type and continuously stores data stored while power supply is maintained And can be used for small amounts of memory or cache memory that do not require a complicated refresh clock.

In addition, since the static RAM must maintain the power supply, it can operate in the standby mode and the active mode separately, and can operate using the minimum standby power in the standby mode.

The on-chip static RAM occupies a significant portion of the total chip area in a very large scale integration (VLSI) structure, resulting in a soft error induced by collision of energy particles, And tend to be more exposed in a space radiation environment than the ground environment.

Conventional techniques used in terrestrial environments can reduce software errors for static RAMs in view of considerable area of chip, power consumption, performance, and system level radiation curing techniques.

In addition, the prior art techniques used in the ground environment operate the static ram using standby power, including scrubbing power used to scrub leakage power and soft errors for leakage currents in the standby mode And the static RAM can be operated mainly considering the leakage power.

However, conventional techniques used in a ground environment are difficult to apply in a radioactive environment, especially in a space radioactive environment.

For example, there is a difficult problem in determining the scrubbing power used for minimal scrubbing of the static RAM in the standby mode, because conventional techniques in the space radiation environment have a greater variation in radioactivity and temperature than in the ground environment.

More specifically, the conventional technology in the space radiation environment has a problem that it is difficult to adaptively determine the minimum value of the standby power including the leakage power corresponding to the leakage current and the scrubbing power for supplying each node of the static RAM in the standby mode Lt; / RTI >

Korean Patent Publication No. 1020120136674 (2012.12.20). "On-chip data scrubbing apparatus and method with error correction circuit" Korean Patent No. 101215815 (December 18, 2012). "Sense Amplification Method for Low-Voltage SRAM and Register Files"

The present invention relates to a method of operating a memory, a memory, a power supply, and a power supply in a radio environment in which a supply voltage for each node is dynamically optimized by adaptively using a minimum value of scrubbing power and standby power for each node of a static RAM operating in a standby mode. A control device and a power control method are provided.

The present invention provides a memory, a memory operation method, a power control apparatus, and a power control method in a radio environment using a bit error rate for each node using a predetermined error correction code and environment variables for application to a radioactive environment.

A power control apparatus for controlling standby power of a memory in a radio environment according to an embodiment of the present invention includes a first acquiring unit for acquiring a bit error rate (BER) for each node of a memory operating in a standby mode, A second acquiring unit for acquiring an optimized scrubbing rate for each node of the memory with reference to a bit error rate and a second acquiring unit for acquiring a scrubbing rate corresponding to the scrubbing power corresponding to the optimized scrubbing rate and a leakage power corresponding to the leakage current And a controller for adaptively determining a minimum value of the standby power and controlling each node of the memory.

Wherein the first obtaining unit obtains at least one of the error correction code (BCH), a BCH code, a BCH code, and a triple error correction code (TEC) ECC, error correction code) to obtain the bit error rate for each node.

In addition, the first obtaining unit may obtain the bit error rate for each node to which the environmental variable for at least one of the process, radiation, and temperature of each node is applied.

The process includes a fast NMOS and slow PMOS, a slow NMOS and a slow PMOS, a typical NMOS and a typical PMOS, a slow NMOS and a fast PMOS, and a fast NMOS and fast PMOS process corner process corners.

According to an aspect of the present invention, the first obtaining unit may obtain the leakage current, the radiation, and the temperature for each node.

Also, the first obtaining unit may obtain the bit error rate for each node by applying at least one predetermined modeling among silicon measurement and monte carlo simulation.

The control unit controls the scrubbing period, the cache capacity, the read energy, the write energy, the read access energy, and the write access energy, which are reciprocals of the scrubbing rate write access energy to determine the scrubbing power supplied to each node.

Also, the controller may control the supply voltage for each node of the memory to be dynamically scaled by referring to the determined minimum value of the standby power.

The memory according to an embodiment of the present invention may include at least one of a provision unit for providing a power control apparatus with environmental variables for at least one of process, radiation, temperature, and leakage current for each node in a standby mode, and a bit error rate A supply voltage for each node is obtained from the power control device based on a scrubbing rate optimized by the bit error rate, a leakage power corresponding to the leakage current, and a minimum value of the standby power including the scrubbing rate and the leakage power And an acquisition unit.

A power control method for controlling standby power of a memory in a radioactive environment according to an embodiment of the present invention includes obtaining a bit error rate for each node of a memory operating in a standby mode, Comprising: obtaining an optimized scrubbing rate for a node; and adaptively determining a minimum value of standby power including leakage power corresponding to a scrubbing power and a leakage current corresponding to the optimized scrubbing rate to control each node of the memory .

Wherein the step of obtaining the bit error rate obtains the bit error rate for each node using the error correction code of at least one of a Hamming code, a double error correcting BCH code and a triple error correcting BCH code

Also, the step of obtaining the bit error rate may obtain the bit error rate for each node by applying an environmental variable for at least one of process, radiation, and temperature of each node.

In addition, the step of obtaining the bit error rate may obtain the bit error rate for each node by applying at least one selected modeling during the silicon measurement and the Monte Carlo simulation.

Wherein the step of controlling each node of the memory comprises determining the scrubbing power supplied to each node using a scrubbing cycle, a cache capacity, a read energy, a write energy, a read access energy, and a write access energy, .

The method of operating a memory according to an embodiment of the present invention includes the steps of providing an environment variable for at least one of process, radiation, temperature, and leakage current for each node in a standby mode to a power control apparatus, , A supply voltage for each node based on a scrubbing rate optimized by the bit error rate, a leakage power corresponding to the leakage current, and a minimum value of the standby power including the scrubbing rate and the leakage power, .

One embodiment of the present invention can dynamically optimize the supply voltage for each node by adaptively using the minimum values of the scrubbing power and the standby power for each node of the static RAM operating in the standby mode.

An embodiment of the present invention may utilize the bit error rate for each node using a predetermined error correction code and environment variables for application to the space radiation environment.

FIG. 1A is a block diagram illustrating a power control apparatus for controlling standby power of a memory in a space radiation environment according to an embodiment of the present invention. FIG.
1B is a block diagram illustrating a power control apparatus for controlling standby power of a memory in a space radiation environment according to another embodiment of the present invention.
2 shows an example of a 6T static RAM bit-cell structure.
3 is an example of a graph illustrating upset probabilities caused by process and temperature variations at a low bit error rate.
Figure 4 is an example of a graph illustrating the relationship between the raw bit error rate and the supply voltage during various scrubbing cycles at the FS process and a temperature corner of 80 degrees.
5 is an example of a graph showing a relationship between a decoded bit error rate and a supply voltage using a Hamming code, a double error corrected BCH code, and a triple error corrected BCH code.
6 is an example of a graph showing the relationship between the bit error rate and the scrubbing period at which a double error corrected BCH code and a triple error corrected BCH code are applied at a supply voltage of 1V.
7 is an example of a graph showing the relationship between the scrubbing power / leakage power and the supply voltage to which the double error corrected BCH code and the triple error corrected BCH code are applied.
8 is an example of a graph showing the relationship between the optimum standby power and the supply voltage to which the double error corrected BCH code and the triple error corrected BCH code are applied.
9 is a block diagram illustrating a memory according to an embodiment of the present invention.
10 is a flowchart illustrating a power control method for controlling standby power of a memory in a space radiation environment according to an embodiment of the present invention.
11 is a flowchart illustrating an operation method of a memory according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

FIG. 1A is a block diagram illustrating a power control apparatus for controlling standby power of a memory in a space radiation environment according to an embodiment of the present invention. FIG.

Referring to FIG. 1A, a power control apparatus 100a for controlling a standby power of a memory includes an operation unit 120a, an optimum unit 130a, and a determination unit 140a.

The calculation unit 120a calculates a bit error rate (BER) for each node of the memory operating in the standby mode.

According to one aspect of the present invention, the computing unit 120a can calculate the bit error rate for each of the nodes using at least one predetermined modeling of silicon measurement and monte carlo simulation. have.

For example, the operation unit 120a can calculate the bit error rate through Equation (1) to be described later, and a soft error may occur in a specific portion of the memory during the scrubbing period, (2) to calculate the modified bit error rate.

Also, the calculating unit 120a can calculate the upset rate from the calculated bit error rate, calculate the upset rate through Equation (3) described later, calculate at least one of the process, radiation, and temperature of each node Environment variables can be applied to calculate the bit error rate for each node.

The power control apparatus 100a according to the embodiment of the present invention may further include a detection unit 110a for detecting leakage current, radiation, and temperature for each node.

In addition, the detection unit 110a may include a sensor for detecting leakage current, radiation, and temperature for each node.

For example, the detection unit 110a may detect the radioactive neutron flux (velocity) density to calculate the number of particle collisions per unit area, and the calculation unit 120a may calculate the number of particle collisions per unit area through the radioactive neutron flux density .

The optimizing unit 130a optimizes the scrubbing rate for each node of the memory with reference to the bit error rate. Here, the scrubbing rate is the reciprocal of the scrubbing period. The optimizing unit 130a will be described in detail with reference to FIG. 6, which will be described later, to optimize the scrubbing rate.

The determination unit 140a adaptively determines the minimum value of the standby power including the leakage power corresponding to the leakage current and the scrubbing power corresponding to the optimized scrubbing rate to be supplied to each node of the memory.

For example, the determining unit 140a can determine the scrubbing power for each node with reference to Table 1, which will be described later, and determine the scrubbing power for each node with reference to Equation (8) described later.

The power control apparatus 100a according to the embodiment of the present invention further includes an adjustment unit 150a that dynamically scales the supply voltage (for example, V DD in FIG. 2) for each node with reference to the minimum value of the determined standby power .

For example, the adjuster 150a may dynamically scale the supply voltage for each node with reference to the minimum value of the standby power adaptively determined in the universe radiation environment, unlike the ground environment.

Further, the adjusting unit 150a can scale each supply voltage for each node of the plurality of memories in real time with reference to the minimum value of each determined standby power for each node of the plurality of memories.

1B is a block diagram illustrating a power control apparatus for controlling standby power of a memory in a space radiation environment according to another embodiment of the present invention.

Referring to FIG. 1B, the power control apparatus 100b includes a first obtaining unit 110b, a second obtaining unit 120b, and a control unit 130b.

The first obtaining unit 110b obtains a bit error rate (BER) for each node of the memory operating in the idle mode.

The memory may be a static random access memory (SRAM) having a memory bit-cell of a flip-flop type. Static RAM can be used to store small amounts of memory or cache memory that do not require a complicated refresh clock, while still retaining stored data while power is on.

In addition, since the static RAM must maintain the power supply, it can be divided into the standby mode and the active mode, and the standby mode can be operated with a minimum standby power.

The memory can be a very large scale integration (VLSI) structure, can occupy a significant portion of the total chip area, and can be a complementary metal oxide semiconductor (CMOS). Hereinafter, the static RAM bit-cell structure will be described in detail with reference to FIG.

2 shows an example of a 6T static RAM bit-cell structure.

2, the static RAM includes two N-type access devices, two N-type pull down transistors N1 and P1 and two P-type pull-up transistors P1 and P2 .

The access transistor may be connected to a word line that may pass through a bit line or a pull-down pull-up transistor, and may be a pass device.

Each of the N-type pull-down transistor, the N-type access transistor, and the P-type pull-up transistor may include a single-fin tri-gate transistor having a source-drain section.

Nodes (the 'A' node for the n + drain with reverse bias and the 'B' node for the p + drain with reverse bias) can be formed through a mutual connection of each transistor.

The N-type pull-down transistor may be an NMOS, the P-type pull-up transistor may be a PMOS, and the NMOS and CMOS may be connected to nodes and fabricated through various processes.

For example, the process may be performed using a fast NMOS and a fast PMOS, a slow NMOS and a slow PMOS, a typical NMOS and a typical PMOS, a slow NMOS and a fast PMOS, And may include process corners.

Referring again to FIG. 1B, the first acquiring unit 110b applies at least one selected modeling of silicon measurement and monte carlo simulation to calculate the bit error rate for each node Can be obtained.

For example, the first obtaining unit 110b may obtain the bit error rate through Equation (1) below.

[Equation 1]

Figure 112015034672855-pat00001

here,

Figure 112015034672855-pat00002
Is the bit error rate,
Figure 112015034672855-pat00003
Is an upset rate,
Figure 112015034672855-pat00004
Is a scrubbing period.

As shown in Equation (1), the first obtaining unit 110b can obtain the bit error rate during the scrubbing period.

Also, since the first acquiring unit 110b can generate a soft error in a specific portion of the memory during the scrubbing period, it can obtain the modified bit error rate through Equation (2).

[Equation 2]

Figure 112015034672855-pat00005

The first acquiring unit 110b can apply the silicon measurement modeling during the scrubbing period of the specific section to obtain the bit error rate.

More specifically, since the first acquiring unit 110b can generate a system overload when computing the bit error rate during every scrubbing period of various specific intervals, it is possible to use silicon measurement modeling for bit error rate computation , Silicon measurement modeling can be applied to obtain the computed bit error rate for the scrubbing period of a particular section.

Also, the first acquiring unit 110b can acquire an upset rate from the obtained bit error rate, and can obtain an upset rate through Equation (3) below.

[Equation 3]

Figure 112015034672855-pat00006

Further, the first obtaining unit 110b can obtain the bit error rate for another scrubbing cycle by the equation (2).

According to one aspect of the present invention, the first obtaining unit 110b may apply an environment variable for at least one of the process, radiation, and temperature of each node to obtain a bit error rate for each node.

For example, the first obtaining unit 110b can obtain the bit error rate by applying the worst case process and environment variables for the worst process and temperature corner in consideration of the process and the temperature fluctuation.

In addition, the first obtaining unit 110b can obtain the bit error rate using Monte Carlo simulation modeling. In this case, the first obtaining unit 110b may obtain the upset rate included in Equation (2) through Equation (4) to which Monte Carlo simulation modeling is applied.

[Equation 4]

Figure 112015034672855-pat00007

here,

Figure 112015034672855-pat00008
Is an upset probability for one collision,
Figure 112015034672855-pat00009
Is the number of particle collisions per unit of a particular memory bit-cell.

Equation (5) below represents the number of unit particle collisions of a particular memory bit-cell.

[Equation 5]

Figure 112015034672855-pat00010

here,

Figure 112015034672855-pat00011
Is the number of particle collisions per unit area,
Figure 112015034672855-pat00012
Is the area of the memory bit-cell.

According to one aspect of the present invention, the first obtaining unit 110b may obtain leakage current, radiation, and temperature for each node. More specifically, the first obtaining unit 110b can obtain leakage current, radiation, and temperature for each node through a sensor that detects leakage current, radiation, and temperature.

For example, the first acquiring unit 110b may acquire the radioactive neutron flux (velocity) density to obtain the number of particle impacts per unit area, and obtain the number of particle impacts per unit area through the radioactive neutron flux density .

Soft errors can be generated by radioactivity, such as particle collisions, and can occur in a variety of ways depending on process and temperature variations.

As shown in FIG. 2, when the memory bit-cell collides with radioactive-related particles in the n + drain and the p + drain to which the reverse bias is applied in the standby mode, a soft error may occur.

For example, an n + drain (or p + drain) with a reverse bias can collect charges by a particle collision, and the collected charges can be N2 (or P1 ) The transistor can be turned on.

On the other hand, if the P2 (or N1) transistor supplies the stored current but the P2 (or N1) transistor does not supply a sufficient stored current, then the switching threshold voltage of the driven inverter drops (or rises) It can fall. Thus, the data in the memory bit-cell may be flipped.

Here, the pull-down NMOS transistor can be made in a stronger environment than the pull-up PMOS in order to obtain reliable read and write operations, and in this environment, the reverse bias is applied to the n + drain ('A' May be vulnerable to soft errors than the p + drain (of the 'B' node) to which the reverse bias is applied.

Also, the pull-down PMOS transistor may have a lower stored current than the pull-down NMOS transistor, and the upset probability is given by Equation (6) below.

[Equation 6]

Figure 112015034672855-pat00013

here,

Figure 112015034672855-pat00014
and
Figure 112015034672855-pat00015
May be the area of the drain connection point of n + and p +
Figure 112015034672855-pat00016
Wow
Figure 112015034672855-pat00017
May be the upset probability of the drain junction of n + and p + for a single particle collision.

Figure 112015034672855-pat00018
and
Figure 112015034672855-pat00019
Can be obtained from the memory bit-cell layout,
Figure 112015034672855-pat00020
Wow
Figure 112015034672855-pat00021
Can not be easily modeled because it can be affected by many factors such as single particle, process and probabilistic variation of the collected charge caused by temperature fluctuations.

Thus, the first acquiring unit 110b may acquire a particle collision producing a double exponential current profile of a constantly collected charge, and the process and temperature variation may be, for example, a 65nm process Can be modeled using a PDK (process development kit). Hereinafter, the bit error rate modeling for the process and the temperature fluctuation will be described in detail with reference to FIG.

3 is an example of a graph illustrating upset probabilities caused by process and temperature variations at a low bit error rate.

Referring to FIG. 3, the first obtaining unit 110b can obtain a bit error rate for each node by applying Monte Carlo simulation modeling, which performs upset probabilities for various processes and temperature corners at a voltage of 1.2V .

For example, the first acquiring unit 110b can obtain the highest upset probability for a single collision at a temperature corner of 80 degrees with the FS process, as shown in Fig.

Further, the first acquiring unit 110b acquires, at the temperature corner of 80 degrees,

Figure 112015034672855-pat00022
Wow
Figure 112015034672855-pat00023
And can calculate the raw bit error rate during various scrubbing cycles through equations (2), (4), (5) and (6) described above. Hereinafter, a process of obtaining a low bit error rate during various scrubbing cycles will be described in detail.

Figure 4 is an example of a graph illustrating the relationship between the raw bit error rate and the supply voltage during various scrubbing cycles at the FS process and a temperature corner of 80 degrees.

Referring to FIG. 4, the first acquiring unit 110b may acquire a low bit error rate for various scrubbing cycles at an 80 degree temperature corner and an FS process before performing error correction.

As shown in Fig. 4, when the scrubbing period is increased, the low bit error rate can also gradually increase. Therefore, if the scrubbing period is increased, the probability of error correction failure can also be increased.

Also, when the voltage is scaled, the low bit error rate can be significantly increased. For example, scaling below 0.8V can increase the low bit error rate.

Accordingly, the first obtaining unit 110b can obtain the bit error rate for each node operating in the standby mode of the space radiation environment simultaneously considering the process, the voltage and the temperature variation, and the lower bound voltage To obtain a bit error rate for each node.

Further, the first obtaining unit 110b can obtain the bit error rate generated by the lower limit voltage using the error correction code.

According to one aspect of the present invention, the first obtaining unit 110b can calculate a bit error rate for each node by a hamming code.

Hamming codes can be used in a terrestrial environment to correct single bit errors in memory, but they may be unsuitable in a space radiation environment and the scrubbing rate for meeting the target's decoded bit error rate may be very high.

Equation (7) is a formula for calculating a decoded bit error rate using a Hamming code.

[Equation 7]

Figure 112015034672855-pat00024

Here, the bit error rate can be obtained through the above-described equation (2), t is the number of errors, and 127 is the length (n) of the codeword indicating the number of bits. The length of the codeword may be applied according to various embodiments.

The first obtaining unit 110b can obtain a decoded bit error rate lower than the target's decoded bit error rate to determine the minimum value of the standby power.

More specifically, the first obtaining unit 110b obtains at least one of a Hamming code, a double error correction (BEC) code, and a triple error correction (TEC) code An error correction code can be used to obtain the bit error rate for each node. Hereinafter, a process of obtaining a bit error rate using various error correction codes will be described in detail with reference to FIG.

5 is an example of a graph showing a relationship between a decoded bit error rate and a supply voltage using a Hamming code, a double error corrected BCH code, and a triple error corrected BCH code.

Referring to FIG. 5, when the supply voltage obtains the bit error rate of the memory operating in the standby mode using the Hamming code at 1.2 V, the first obtaining unit 110b does not satisfy the decoded bit error rate of the target .

On the other hand, the first acquiring unit 110b can meet the decoded bit error rate of the target when the supply voltage acquires the bit error rate of the memory operating in the standby mode using the double error correcting BCH code at 970 mV .

Further, the first obtaining unit 110b can satisfy the target decoded bit error rate when the supply voltage obtains the bit error rate of the memory operating in the standby mode using the triple error correcting BCH code at 780 mV .

Accordingly, the first obtaining unit 110b can obtain the bit error rate using at least one of the Hamming code, the double error correcting BCH code, and the triple error correcting BCH code adaptively according to the supply voltage.

Here, the high soft error means an increase in the supply voltage, and the first obtaining unit 110b can select the various error correction codes adaptively according to the supply voltage to obtain the bit error rate.

According to the embodiment, the first obtaining unit 110b can obtain the bit error rate through the operations of the equations (1) to (7) and obtain the bit error rate through the table to which the operations of the equations (1) An error rate can be obtained.

The second obtaining unit 120b obtains an optimized scrubbing rate for each node of the memory with reference to the bit error rate. Here, the scrubbing rate is the reciprocal of the scrubbing period. Hereinafter, the process of optimizing the scrubbing rate will be described in detail with reference to FIG.

6 is an example of a graph showing the relationship between the bit error rate and the scrubbing period at which a double error corrected BCH code and a triple error corrected BCH code are applied at a supply voltage of 1V.

Referring to FIG. 6, the second obtaining unit 120b may calculate a range of scrubbing cycles that satisfy the target's decoded bit error rate for each node of the memory to obtain an optimized scrubbing rate.

For example, the second obtaining unit 120b may calculate a range of the scrubbing period from 10 seconds to 95 seconds, as shown in FIG. 6, to optimize the scrubbing rate to satisfy the target's decoded bit error rate .

Table 1 is a table showing the scrubbing cycles to which double error corrected BCH codes and triple error corrected BCH codes are applied corresponding to various supply voltages.

[Table 1]

Figure 112015034672855-pat00025

According to an embodiment, the second obtaining unit 120b may obtain an optimized scrubbing rate through a range operation of the scrubbing period that satisfies the target's decoded bit error rate for each node of the memory, and the bit error rate An optimized scrubbing rate for each node can be obtained through the applied table.

The controller 130b adaptively determines the minimum value of the standby power including the scrubbing power corresponding to the optimized scrubbing rate and the leakage power corresponding to the leakage current to control each node of the memory.

For example, the controller 130b may control the scrubbing power for each node to be determined with reference to Table 1, and may control the scrubbing power for each node to be determined with reference to Equation (8).

[Equation 8]

Figure 112015034672855-pat00026

Where m is the cache capacity of the bit.

Figure 112015034672855-pat00027
,
Figure 112015034672855-pat00028
,
Figure 112015034672855-pat00029
And
Figure 112015034672855-pat00030
Write energy, read access energy, and write access energy used during a write access, a memory bit-cell read, write, read access, to be.

According to one aspect of the present invention, the controller 130b may use CACTI simulation to adaptively determine the scrubbing power.

Table 2 shows the main parameters of the CATCTI simulation.

[Table 2]

Figure 112015034672855-pat00031

Referring to Table 2, the CATCTI simulation

Figure 112015034672855-pat00032
Wow
Figure 112015034672855-pat00033
While
Figure 112015034672855-pat00034
Wow
Figure 112015034672855-pat00035
Can not be obtained,
Figure 112015034672855-pat00036
Wow
Figure 112015034672855-pat00037
And
Figure 112015034672855-pat00038
Wow
Figure 112015034672855-pat00039
Because the energy of the non-uniform cache access (NUCA) cache model is not exactly the same, the correct parameters can be set using the NUCA (non-uniform cache access) cache model.

According to the embodiment, the first acquiring unit 110b can acquire the leakage power corresponding to the leakage current for each node of the memory, and can obtain the leakage power through the sensor for detecting the leakage current.

For example, the first obtaining unit 110b can detect leakage current and leakage power for each node in a predetermined environment (for example, at a temperature corner of 80 degrees with the FF process).

Also, the controller 130b can use the detected leakage current as an input parameter of the CATCTI simulation to control the leakage power to be determined. Hereinafter, an example of adaptively determining the minimum value of the standby power including the scrubbing power and the leakage power through the CATCTI simulation will be described in detail.

FIG. 7 is an example of a graph showing the relationship between the scrubbing power / leakage power and the supply voltage to which the double error corrected BCH code and the triple error corrected BCH code are applied, and FIG. 8 is a graph showing the relationship between the double error corrected BCH code and the triple error corrected BCH code This is an example of a graph showing the relationship between optimal standby power and supply voltage.

7 and 8, the controller 130b increases the scrubbing power while exponentially decreasing the leakage power, so that the optimal standby power (for example, the minimum value of the standby power), which is the sum of the leakage power and the scrubbing power, To control each node of the memory.

For example, the minimum value of the standby power to which the double error correction BCH code is applied may be 0.97V, and the minimum value of the standby power to which the triple error correction BCH code is applied may be 0.8V.

Accordingly, the controller 130b can control each node of the memory by determining the minimum value of the standby power (0.97 V, 0.8 V) through the FF process and the CATCTI simulation operating at the temperature corner of 80 degrees.

According to the embodiment, the control unit 130b can control each node of the memory by adaptively determining the minimum value of the standby power by applying environmental variables including various processes and temperature fluctuations, Can be referred to.

Also, the controller 130b can control the supply voltage for each node to be dynamically scaled by referring to the minimum value of the determined standby power.

More specifically, the control unit 130b can control the supply voltage for each node to be dynamically scaled by referring to the minimum value of the standby power adaptively determined in the space radiation environment different from the ground environment.

According to the embodiment, the power control apparatus 100b can control the standby power for each node of the plurality of memories operating in the standby mode.

For example, the first obtaining unit 110b may obtain the bit error rate for each node of the plurality of memories operating in the standby mode, and the second obtaining unit 120b may obtain the bit error rate for each node of the plurality of memories The control unit 130b may adaptively determine the minimum value of the standby power including the scrubbing power corresponding to the optimized scrubbing rate and the leakage power corresponding to the leakage current A plurality of memory nodes can be controlled.

9 is a block diagram illustrating a memory according to an embodiment of the present invention.

Referring to FIG. 9, a memory 900 operating in a space radiation environment includes a providing unit 910 and an acquiring unit 920.

The providing unit 910 provides environment variables for at least one of the process, radiation, temperature, and leakage current for each node in the standby mode to the power control device.

For example, it is possible to provide the power control device with environmental variables for at least one of process, radiation, temperature, and leakage current for each node through a sensor for detecting leak current, radiation, and temperature, To the power control apparatus through the identification information associated with the power control apparatus.

The acquiring unit 920 is configured to acquire, based on the bit error rate to which the environment variable is applied, the scrubbing rate optimized by the bit error rate, the leakage power corresponding to the leakage current, and the minimum value of the standby power including the scrubbing rate and leakage power, And obtains a supply voltage for the power supply from the power control device.

Accordingly, the memory 900 can operate the standby mode operation using the supply voltage obtained from the power control apparatus.

10 is a flowchart illustrating a power control method for controlling standby power of a memory in a space radiation environment according to an embodiment of the present invention.

Referring to FIG. 9, in step 910, the power control apparatus obtains a bit error rate for each node of the memory operating in a standby mode using an error correction code.

The memory may be a static random access memory (SRAM) having a memory bit-cell of a flip-flop type. Static RAM can be used to store small amounts of memory or cache memory that do not require a complicated refresh clock, while still retaining stored data while power is on.

In addition, since the static RAM must maintain the power supply, it can operate in the standby mode and the active mode separately, and can operate using the minimum standby power in the standby mode.

In step 1010, the power control apparatus that controls the standby power of the memory may apply the environmental variable for at least one of the process, radiation, and temperature of each node to obtain the bit error rate for each node. The process may include FS, SS, TT, SF and FF process corners.

Further, at step 1010, the power control apparatus may obtain leakage current, radiation, and temperature for each node. More specifically, in step 910, the power control apparatus can obtain leakage current, radiation, and temperature for each node through a sensor that detects leakage current, radiation, and temperature.

According to an embodiment, at step 1010, the power control apparatus may apply at least one selected modeling during silicon measurement and Monte Carlo simulation to obtain a bit error rate for each node. The selected modeling can refer to equations (1) to (7) described above.

More specifically, at step 1010, the power control apparatus may obtain a bit error rate during a scrubbing period, may obtain a modified bit error rate to reflect a soft error occurring in a particular portion of memory, The upset rate can be obtained from the bit error rate.

According to an embodiment, in step 1010, the power control apparatus may obtain a bit error rate for each node using at least one error correction code of a Hamming code, a double error correction BCH code, and a triple error correction BCH code.

More specifically, in step 1010, the power control apparatus may obtain a decoded bit error rate that is lower than the target decoded bit error rate to determine a minimum value of the standby power.

In step 1020, the power control apparatus obtains an optimized scrubbing rate for each node of the memory with reference to the bit error rate. Here, the scrubbing rate is the reciprocal of the scrubbing period.

The power control apparatus also controls each node of the memory by adaptively determining the minimum value of the standby power including the leakage power corresponding to the scrubbing power and the leakage current corresponding to the optimized scrubbing rate in step 1030.

According to an embodiment, in step 1030, the power control apparatus for controlling the standby power of the memory may be configured to determine, using a scrubbing period, a cache capacity, a read energy, a write energy, a read access energy and a write access energy, It is possible to control the scrubbing power supplied to be determined.

According to the embodiment, the power control apparatus can control the standby power for each node of the plurality of memories operating in the standby mode.

For example, in step 1010, the power control apparatus may obtain a bit error rate for each node of a plurality of memories operating in a standby mode, and for each node of the plurality of memories, referring to the bit error rate in step 1020, The optimized scrubbing rate can be obtained and the minimum value of the standby power including the leakage power corresponding to the scrubbing power and the leakage current corresponding to the optimized scrubbing rate can be adaptively determined in step 1030, can do.

11 is a flowchart illustrating an operation method of a memory according to an embodiment of the present invention.

Referring to FIG. 11, in step 1110, the memory provides environment variables for at least one of process, radiation, temperature, and leakage current for each node in the standby mode to the power control device.

For example, in step 1110, environmental variables for at least one of process, radiation, temperature, and leakage current for each node can be provided to the power control device through sensors that detect leakage current, radiation, and temperature, Can be provided to the power control apparatus through the related identification information.

The memory determines in step 1120 that the environmental variable is applied to each node based on the bit error rate applied, the scrubbing rate optimized by the bit error rate, the leakage power corresponding to the leakage current, and the minimum value of the standby power including the scrubbing rate and leakage power And obtains a supply voltage for the power supply from the power control device.

Thus, the memory can operate the operation of the standby mode using the supply voltage obtained from the power control device.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

100a, 100b: Power control device
110a:
120a:
130a:
140a:
150a:
110b:
120b:
130b:
900: Memory
910: Offering
920:

Claims (15)

1. An apparatus for controlling standby power of a static random access memory (SRAM) operating in a standby mode and an active mode in a radioactive environment,
A first obtaining unit obtaining a bit error rate (BER) in a standby mode for each node of a static RAM to which an environment variable including a radiation effect is applied;
A second acquiring unit for acquiring an optimized scrubbing rate in a standby mode for each node of the static RAM with reference to the bit error rate; And
Determining a minimum value of the standby power defined by a sum of the scrubbing power corresponding to the optimized scrubbing rate and the leakage power corresponding to the leakage current and controlling each node of the static RAM based on the minimum value of the standby power
Wherein the control unit controls the standby power of the static RAM in the radioactive environment. The method according to claim 1,
The first obtaining unit
Applying Monte Carlo simulation modeling to obtain the bit error rate for each node comprising the radiation effect
Power control device for controlling standby power of static RAM in radioactive environment. delete 3. The method of claim 2,
Wherein the first obtaining unit comprises:
Calculating an upset rate based on Equation (4) to which Monte Carlo simulation modeling is applied, applying the upset rate to the environment variable,
[Equation 4]
Figure 112016054311498-pat00052

here,
Figure 112016054311498-pat00053
Is an upset probability for one collision,
Figure 112016054311498-pat00054
Is the number of particle collisions per unit of a particular memory bit-cell,
Calculating a number of particle impacts per unit of memory bit-cell based on Equation 5 and obtaining an environmental variable including the radiation impact based on the number of particle impacts,
[Equation 5]
Figure 112016054311498-pat00055

here,
Figure 112016054311498-pat00056
Is the number of particle collisions per unit area,
Figure 112016054311498-pat00057
Is the area of the memory bit-cell,
Power control device for controlling standby power of static RAM in radioactive environment. 3. The method of claim 2,
The first obtaining unit
Obtaining the leakage current, the radioactivity and the temperature for each node
Power control device for controlling standby power of static RAM in radioactive environment. The method according to claim 1,
The first obtaining unit
At least one selected modeling of silicon measurement and monte carlo simulation is applied to obtain the bit error rate for each node
Power control device for controlling standby power of static RAM in radioactive environment. The method according to claim 1,
The control unit
A scrubbing period, a cache capacity, a read energy, a write energy, a read access energy and a write access energy, which are reciprocals of the scrubbing rate, ) So that the scrubbing power supplied to each node is determined
Power control device for controlling standby power of static RAM in radioactive environment. The method according to claim 1,
The control unit
And controls the supply voltage for each node of the static RAM to be dynamically scaled by referring to the determined minimum value of the standby power
Power control device for controlling standby power of static RAM in radioactive environment. delete 1. A method for controlling standby power supplied to a static RAM in a standby mode of a static random access memory (SRAM) operating in a standby mode and an active mode in a radioactive environment,
Obtaining a bit error rate in a standby mode for each node of a static RAM to which an environment variable including a radiation effect is applied;
Obtaining an optimized scrubbing rate in a standby mode for each node of the static RAM with reference to the bit error rate; And
Determining a minimum value of the standby power defined by a sum of the scrubbing power corresponding to the optimized scrubbing rate and the leakage power corresponding to the leakage current and controlling each node of the static RAM based on the minimum value of the standby power
Wherein the standby power of the static RAM is controlled in a radioactive environment including the sleep mode. 11. The method of claim 10,
Wherein obtaining the bit error rate comprises:
And applying Monte Carlo simulation modeling to obtain the bit error rate for each node comprising the radiation effect
A power control method for controlling the standby power of static RAM in a radioactive environment. delete 12. The method of claim 11,
Wherein obtaining the bit error rate comprises:
Calculating an upset rate based on Equation (4) to which Monte Carlo simulation modeling is applied, applying the upset rate to the environment variable,
[Equation 4]
Figure 112016054311498-pat00058

here,
Figure 112016054311498-pat00059
Is an upset probability for one collision,
Figure 112016054311498-pat00060
Is the number of particle collisions per unit of a particular memory bit-cell,
Calculating a number of particle impacts per unit of memory bit-cell based on Equation 5 and obtaining an environmental variable including the radiation impact based on the number of particle impacts,
[Equation 5]
Figure 112016054311498-pat00061

here,
Figure 112016054311498-pat00062
Is the number of particle collisions per unit area,
Figure 112016054311498-pat00063
Is the area of the memory bit-cell,
A power control method for controlling the standby power of static RAM in a radioactive environment. 11. The method of claim 10,
Wherein the step of controlling each node of the static RAM
The scrubbing power supplied to each node is determined using a scrubbing cycle, a cache capacity, a read energy, a write energy, a read access energy, and a write access energy, which are reciprocals of the scrubbing rates
A power control method for controlling the standby power of static RAM in a radioactive environment. delete
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