KR101679508B1 - Sad calculation device and method - Google Patents

Sad calculation device and method Download PDF

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KR101679508B1
KR101679508B1 KR1020150050135A KR20150050135A KR101679508B1 KR 101679508 B1 KR101679508 B1 KR 101679508B1 KR 1020150050135 A KR1020150050135 A KR 1020150050135A KR 20150050135 A KR20150050135 A KR 20150050135A KR 101679508 B1 KR101679508 B1 KR 101679508B1
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absolute difference
sum
absolute
bits
minimum
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KR1020150050135A
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KR20160120934A (en
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장익준
김진상
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경희대학교 산학협력단
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]

Abstract

The present invention includes a first calculation unit for calculating an absolute difference (AD) between pixels of a current macroblock and a reference macroblock having a size of M * N within a search window range, (SAD) with respect to each of the absolute differences, and a minimum absolute difference sum (min SAD) having a minimum value among the respective calculated absolute differences And a third arithmetic operation unit for performing the arithmetic operation on the first arithmetic operation unit.

Description

[0001] SAD CALCULATION DEVICE AND METHOD [0002]

The present invention relates to an apparatus and method for computing an absolute sum, and more particularly, to an apparatus and method for computing an absolute difference by approximating upper bits to one higher bit.

In recent years, as the technology related to digital signal processing, storage media and transmission method has developed, the voice service limited to voice has evolved into a multimedia service including digital video.

A digital image is composed of consecutive frames, each of which consists of macroblocks (MBs) having a predetermined size, and each macroblock includes pixels of a predetermined size. Therefore, a digital image may include a large amount of data as compared with a voice.

The multimedia service can provide a compressed digital image using a compression technique for efficiently compressing a digital image. The compression technique is a technique for eliminating temporal redundancy between consecutive frames of a digital image, and a motion estimation technique may be included to eliminate temporal redundancy.

The conventional motion estimation technique can perform a sum of absolute difference (SAD) operation on all pixels in macroblock units. More specifically, the conventional motion estimation technique can calculate the absolute difference (AD) between the pixels of the current macroblock and the reference macroblock, and calculate the sum for each absolute difference.

Here, the pixels may be represented by a bit string, and the bit string may include least significant bits (LSB's) and most significant bits (MSB's). The lower bits are located in the significant digits near the right in the bit stream and the upper bits are located in the significant digits near the left in the bit stream.

In the conventional motion estimation technique, upper bits including a correction bit and an inverter bit can be added by an absolute difference operation. Therefore, there is a problem that the conventional motion estimation technique undergoes a carry-propagation delay with the addition of the upper bits.

In addition, in the conventional motion estimation technique, there is a problem that power consumption is increased due to addition of logic elements for performing operations on additional higher bits.

Vanne, J., Aho, E., Hamalainen, T.D. and Kuusilinna, K. "A High-Performance Sum of Absolute Difference Implementation for Motion Estimation ". IEEE Trans. Circ. Syst. Video Tech. vol. 16, issue 7, July.2006 Kaul, H., Anders, M. A., Mathew, S. K., Hsu, S. K., Agarwal, A., Krishnamurthy, R.K. and Borkar, S. A 320 mV 56 μW 411

The present invention uses an approximation rule that approximates the upper bits of the number of higher-order added higher bits to one higher bit, thereby reducing the carry propagation delay and performing an absolute difference calculation Apparatus and method.

The present invention provides an absolute difference arithmetic operation apparatus and method for reducing power consumption of a system by using a logic element to which an approximation rule is applied.

The present invention provides an apparatus and method for absolute difference arithmetic operation that improves the performance of motion compression by adaptively changing an approximation rule.

 The absolute difference calculation apparatus according to an embodiment of the present invention includes a first calculation unit for calculating an absolute difference (AD) between pixels of a current macroblock having a size of M * N and a reference macroblock within a search window range, A second arithmetic unit for calculating a sum of absolute difference (SAD) for each of the absolute differences by considering the upper bits added by the absolute difference arithmetic operation; And a third arithmetic unit for determining a minimum absolute difference sum (min SAD).

The second calculation unit may calculate the absolute difference for each absolute difference based on an approximation rule for approximating the number of the added upper bits in the highest order to one higher bit.

The approximation rule may be applied to an OR gate carry method.

The absolute difference calculator according to an embodiment of the present invention calculates a difference between a minimum absolute difference sum and a discrete cosine transform (DCT) value smaller than the predetermined number And re-selecting the approximation rules to change the approximation rule.

And the second calculation unit may recalculate the absolute difference sum for each absolute difference by applying the modified approximation rule.

The absolute difference calculation method according to an embodiment of the present invention includes: calculating an absolute difference between pixels of a current macroblock and a reference macroblock having a size of M * N within a search window range; Calculating an absolute difference sum for each absolute difference in consideration of upper bits, and determining a minimum absolute difference sum having a minimum value among the respective calculated absolute difference differences.

The calculating of the absolute difference sum may calculate the absolute difference sum for each absolute difference based on an approximation rule for approximating the number of higher-order added higher bits to one higher bit.

The absolute difference calculation method according to an embodiment of the present invention is characterized in that when the discrete cosine transform value for the minimum absolute difference sum is equal to or larger than a predetermined threshold value, The method comprising the steps of:

In one embodiment of the present invention, by using an approximation rule that approximates a number of higher-order added bits of the higher order bits by one higher bit, it is possible to reduce a carry propagation delay, .

The present invention can reduce the power consumption of the system by using the logic element to which the approximation rule is applied.

The present invention can adaptively change the approximation rule to improve the performance of motion compression.

1 shows an example of an absolute difference arithmetic operation apparatus having an input of 16 pairs of pixels.
2 shows an example of an absolute difference arithmetic unit having input of 16 pairs of pixels based on a carry store adder.
FIG. 3 shows an example of an absolute difference arithmetic unit having inputs of 16 pairs of pixels based on a ripple carry adder.
FIG. 4 shows an example of the carry adder structure of FIG.
FIG. 5 shows an example of approximating upper bits to one upper bit.
FIG. 6A is an example showing a distribution of the absolute difference sum in a state in which the upper bits are not approximated to FIG.
FIG. 6B shows an example of the distribution of the absolute difference in the state approximated to the upper bits of FIG.
FIG. 7 shows an example of an absolute difference calculation apparatus for approximating four higher bits to one higher bit.
FIG. 8 shows an example of a structure of a logic element for performing the operation of approximating the four upper bits of FIG. 7 to one higher bit.
FIG. 9 is a block diagram illustrating an absolute difference calculation apparatus according to an embodiment of the present invention.
10 is a flowchart illustrating an absolute difference calculation method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

1 shows an example of an absolute difference arithmetic operation apparatus having an input of 16 pairs of pixels.

Referring to FIG. 1, the absolute difference calculation apparatus 100 performs a sum of absolute difference (SAD) operation 120 on all macroblocks within a searching window range (SWR) And can determine the minimum absolute difference sum having the minimum value among the respective calculated difference averages.

More specifically, in order to reduce temporal redundancy of a digital image, the absolute difference calculation apparatus 100 calculates an absolute difference (AD) between pixels of a current macroblock and a reference macroblock within a search window range, ), Calculate an absolute difference sum for each absolute difference, and determine a minimum absolute difference sum having a minimum value among the respective calculated difference averages.

As shown in FIG. 1, the absolute difference value calculation apparatus 100 can accumulate the absolute differences for each absolute difference in four steps (S1, S2, S3, and S4) The minimum absolute difference sum having the minimum value among the calculated absolute difference sum can be determined.

Here, the pixels may be represented by a bit string, and the bit string may include least significant bits (LSB's) and most significant bits (MSB's). The lower bits are located in the significant digits near the right in the bit stream and the upper bits are located in the significant digits near the left in the bit stream.

One macroblock may be pixels with an M * N size and may be 16 pixels with a 4 * 4 size in the H.264 video standard.

According to the embodiment, the absolute difference value calculation apparatus 100 includes a current macro having a size of 4x4, 4x8, 8x4, 8x8, 8x16, 16x8, 16x16, or MxN It is possible to calculate the absolute difference between the pixels of the block and the reference macroblock, and to calculate the absolute difference sum with respect to each absolute difference.

For example, the absolute difference value calculation apparatus 100 can perform an absolute difference calculation through the following equation (1).

[Equation 1]

Figure 112015034672710-pat00001

Here, M * N denotes a size of a macroblock, Ci denotes a luma value or a chroma value of an i-th pixel of the current macroblock, Ri denotes a luma value of an i-th pixel of a reference macroblock, Or a chroma value.

Referring to FIG. 1, the absolute difference calculation apparatus 100 can calculate absolute differences of 16 pairs of pixels of a current macroblock having a size of 4 * 4 and a reference macroblock.

Also, the absolute difference calculation apparatus 100 can process 16 pairs of pixels in parallel, and calculate an absolute difference between the bits of 16 pairs of pixels through the following equation (2).

[Equation 2]

Figure 112015034672710-pat00002

Referring to Equation (2), the absolute difference calculation device can add upper bits including the correction bits and the inverter bits by an absolute difference operation.

For example, if a is greater than b, a correction bit can be added, and if a is less than or equal to b, an inverter bit can be added.

According to an aspect of the present invention, the absolute difference calculation apparatus 100 undergoes a carry-propagation delay (or critical path delay) while adding the upper bits in the absolute difference calculation .

According to another aspect of the present invention, the absolute difference value calculation apparatus 100 may experience a carry-up propagation delay when an upper bit is added at the time of minimum absolute difference sum determination.

Also, the absolute difference calculation device 100 may use a carry-save adder (CSA) to reduce the carry propagation delay. Hereinafter, the absolute difference value calculator 200 using the carry store adder will be described in detail with reference to FIG.

2 shows an example of an absolute difference arithmetic unit having input of 16 pairs of pixels based on a carry store adder.

Referring to FIG. 2, the absolute difference calculation apparatus 200 calculates an absolute difference of 16 pairs of pixels of a current macroblock having a size of 4 * 4 and a reference macroblock within a search window range, Can be used to calculate the absolute difference sum for each absolute difference, and the minimum absolute difference sum having the minimum value among the respective calculated difference differences can be determined.

Here, sixteen pairs of pixels may be represented by a bit string, and the bit string may include lower bits and upper bits.

Also, the carry store adder may perform an add operation on at least three or more bits, may be a structure of a full adder, and may be a Sklansky adder.

As shown in FIG. 2, the absolute difference calculation apparatus 200 may include 52 timing units when computing an absolute difference sum and a minimum absolute difference sum using a carry accumulation adder . The timing unit means the time of the carry propagation delay.

According to an aspect of the present invention, the absolute difference calculation device 200 may use a ripple-carry adder (RCA) to reduce the number of timing units shown in FIG. Hereinafter, the absolute difference arithmetic unit 300 using the ripple carry adder will be described in detail with reference to FIG. 3 and FIG.

FIG. 3 shows an example of an absolute difference arithmetic unit having inputs of 16 pairs of pixels based on a ripple carry adder, and FIG. 4 shows an example of a carry adder structure of FIG.

Referring to FIG. 3, the absolute difference calculator 300 calculates an absolute difference of 16 pairs of pixels of a current macroblock having a size of 4 * 4 and a reference macroblock within a search window range, Can be used to calculate the absolute difference sum for each absolute difference, and the minimum absolute difference sum having the minimum value among the respective calculated difference differences can be determined.

Here, sixteen pairs of pixels may be represented by a bit string, and the bit string may include lower bits and upper bits.

As shown in FIG. 4, the ripple carry adder may include a full adder 410 and a half adder 420. More specifically, the ripple carry adder may include logic elements such as a NAND / NOR gate and an inverter for two inputs.

The absolute difference value calculator 300 can calculate the absolute difference sum for each absolute difference in four steps and determine the minimum absolute difference sum having the smallest value among the respective calculated difference absolute differences.

At this time, the absolute difference calculator 300 can add the upper bits at the time of the absolute difference calculation and the determination of the minimum absolute difference, and the logic element for performing the operation for the added upper bits 310 is added .

For example, when the upper order bits are cumulatively operated, the absolute sum calculating apparatus 300 may need to operate six full adders and calculate a minimum absolute difference sum having a minimum value among the absolute differences for the upper bits Operation of three full adders may be required.

More specifically, the absolute difference calculation device 300 may include 108 logic gates when determining an absolute difference calculation and a minimum absolute difference sum for the upper bits. At this time, one full adder may include 12 logic gates.

As shown in FIG. 3, when calculating an absolute difference sum and a minimum absolute difference sum for 16 pairs of pixels using the ripple carry adder, .

According to an aspect of the present invention, the absolute difference calculation apparatus 300 may experience a carry propagation delay while adding the upper bits in the absolute difference calculation. Hereinafter, an absolute difference calculator 700 capable of reducing the carry propagation delay by approximating upper bits to one higher bit will be described in detail with reference to FIGS. 5 to 8. FIG.

5A and 5B show an example of approximating upper bits to one upper bit, FIG. 6A is an example showing a distribution of absolute difference sum in a state where the upper bits are not approximated to upper bits of FIG. 5, FIG. This is an example showing the distribution of the absolute difference in a state approximated by bits.

Referring to FIG. 5, the absolute difference calculator can select two or more higher order bits in the highest order and approximate them to one higher order bit.

As shown in FIG. 5, the absolute difference calculator can select four higher bits in descending order, and approximate selected upper bits to one higher bit.

According to an aspect of the present invention, the absolute difference calculation apparatus can maintain the compression performance of a digital image even when the selected upper bits are approximated to one higher bit, and reduce the carry propagation delay.

For example, as shown in FIGS. 6A and 6B, the difference in the distribution of the absolute difference in the state in which the upper bits are not approximated to one upper bit and in the approximated state is as large as not affecting digital image compression Can exist.

Table 1 shows the transmission speed of the compressed digital image. More specifically, Table 1 shows a transmission rate of each compressed digital image when 3 to 5 upper bits are selected and approximated to one upper bit.

[Table 1]

Figure 112015034672710-pat00003

Table 1 shows the transmission rate calculated by applying a digital image having a resolution of 640 * 460 and a search algorithm for calculating various search window ranges.

The search algorithm may include a full search (FS), a fast full search (FFS), and a umh-exagon search (UHS) algorithm.

Referring to Table 1, the absolute difference arithmetic unit can provide a compressed digital image with a higher transmission rate than when it is not approximated by one upper bit, when approximating to one higher bit.

In addition, when the number of high order bits is selected and approximated to one higher bit, the absolute difference sum calculator calculates a compressed digital image having a higher transmission rate than a case where the number of upper bits is selected and approximated to one higher bit .

Accordingly, the absolute difference arithmetic unit can improve the transmission efficiency of the compressed digital image by selecting at least two higher order bits in the descending order and approximating them to one higher order bit.

7 shows an example of an absolute difference arithmetic unit for approximating four upper bits to one upper bit, and FIG. 8 shows a structure of a logic element for performing the operation of approximating the four upper bits of FIG. 7 to one upper bit Here is an example.

Referring to FIG. 7, the absolute difference calculation device 700 can calculate the absolute difference between the current macroblock having a size of 4 * 4 and 16 pairs of reference macroblocks within the search window range.

Here, the 16-bit pixel may be represented by a bit string, and the bit string may include lower bits and upper bits, and the absolute difference arithmetic operation unit may correct the upper bits including the correction bits and the inverter bits (710) can be added.

According to the embodiment, the absolute difference arithmetic unit 700 performs an approximation rule (for example, an approximation rule is implemented as a logic element) that approximates a predetermined number of higher-order added bits to one upper bit The absolute difference sum for each absolute difference can be computed, and the minimum absolute difference sum having the minimum value among the respective computed absolute differences can be determined.

In addition, the absolute difference calculation device 700 can accumulate and calculate the absolute difference sum for each absolute difference in four stages, and can determine the minimum absolute difference sum having the smallest value among the respective calculated difference absolute differences have.

As an example of approximating the number of additional upper bits in the highest order to one higher bit, the circuit included in reference numeral 720 in Fig. 7 may be replaced by the logic element shown in Fig.

Referring to FIG. 8, a logic element that performs an operation of approximating four higher bits to one higher bit can operate in an OR gate carry method, and a NAND gate and an inverter for two inputs .

For example, when determining the absolute difference sum and the minimum absolute difference for an approximated one higher bit, the absolute difference calculator calculates the difference between the two inputs, And a logic gate.

Thus, according to the example shown in FIG. 8, the most significant output bit of the Accumulator can be output as an approximated upper bit " 36 " through the OR gate.

As shown in FIG. 7, in the case of calculating the absolute difference sum and the minimum absolute difference for 16 pairs of pixels by approximating four upper bits to one upper bit, ≪ / RTI > timing units may be included.

Referring to FIGS. 2, 3 and 7, the absolute difference arithmetic and logic unit is composed of a carry store adder, a ripple carry adder, and a logic element for approximating the four upper bits to one higher bit, 52, 48, and 42 timing units may be included in the computation of the absolute and minimum absolute differences.

Therefore, the absolute difference calculator can reduce the carry propagation delay when the four higher order bits are approximated to one higher order bit.

Referring to FIGS. 2, 3 and 7, the absolute difference arithmetic and logic unit calculates a sum of absolute values for 16 pairs of pixels by using a ripple carry adder and a logic element for approximating four upper bits to one upper bit. 108 and 42 logic gates may be included when computing a sum sum operation and a minimum absolute sum sum.

Table 2 shows the power simulation results.

[Table 2]

Figure 112015034672710-pat00004

Referring to Table 2, the absolute difference arithmetic and logic unit includes J.Vanne's SAD, a RCA-based SAD, and a logic element for performing an approximation operation of four upper bits to one upper bit (4-MSB a-SAD), the logic element performing the approximation operation may have the lowest power consumption.

Therefore, the absolute difference calculation device can reduce the power consumption of the logic element when approximating the four upper bits to one higher bit.

The absolute difference arithmetic unit can calculate an absolute difference sum for each absolute difference based on an approximation rule that approximates a number of the added upper bits in the highest order to one higher bit, The minimum absolute difference sum having the minimum value among the calculated absolute difference sum can be determined.

The approximation rule may be a rule that selects 2, 3, 4, or N in ascending order among the added upper bits and approximates to one upper bit.

According to an aspect of the present invention, as the number of added upper bits increases, the absolute difference arithmetic unit can improve the transmission efficiency of the compressed digital image, but can reduce the performance of motion compression.

For example, the absolute difference arithmetic unit can convert a discrete cosine transform (DCT) value based on a high frequency into a discrete cosine transform (DCT) value using a minimum absolute difference sum, and implement motion compression using the transformed discrete cosine transform .

In this case, if the discrete cosine transform value for the minimum absolute difference sum computed within the search window range is equal to or larger than the predetermined threshold value, the performance of the motion compression may be reduced.

Therefore, if the DCT (discrete cosine transform) value for the minimum absolute difference sum is equal to or larger than the predetermined threshold value, the absolute difference arithmetic operation apparatus re-determines the approximation rule to a smaller number than the predetermined number Can be changed.

Also, the absolute difference arithmetic operation apparatus re-computes the absolute difference sum for each absolute difference by applying the modified approximation rule, and recalculates the minimum absolute difference sum having the minimum value among each re-computed absolute difference sum, Performance can be improved.

In addition, the absolute summing calculator can implement motion compression based on wide dynamic voltage scaling. Thus, the absolute difference arithmetic unit can improve the energy efficiency.

Hereinafter, specific embodiments of the absolute difference calculation apparatus and method will be described. 1 to 8 can be applied to all of the descriptions of the absolute difference calculation apparatus and method described later.

FIG. 9 is a block diagram illustrating an absolute difference calculation apparatus according to an embodiment of the present invention.

9, the absolute difference value calculation apparatus 900 includes a first calculation unit 910, a second calculation unit 920, and a third calculation unit 930.

The first computing unit 910 computes the absolute difference between the pixels of the current macroblock and the reference macroblock having the M * N size within the search window range.

The pixels may be represented by bit strings, and the bit string may include lower bits and upper bits. The lower bits are located in the significant digits near the right in the bit stream and the upper bits are located in the significant digits near the left in the bit stream.

One macroblock may be pixels with an M * N size and may be 16 pixels with a 4 * 4 size in the H.264 video standard.

According to one aspect of the present invention, the first calculation unit 910 can process the absolute difference between the pixels of the current macroblock and the reference macroblock having the M * N size within the search window range in parallel, Lt; RTI ID = 0.0 > bit < / RTI > and inverter bits.

The second calculation unit 920 calculates an absolute difference sum with respect to each absolute difference in consideration of the upper bits added by the absolute difference calculation.

More specifically, the second calculator 920 can calculate the absolute difference of each absolute difference based on an approximation rule for approximating the number of higher-order added higher bits to one higher bit. The approximation rules can be applied to the logical sum gate carry method and can be implemented as logic elements.

In addition, the second calculator 920 can accumulate the absolute differences for each absolute difference in a multistage manner.

The third computing unit 930 determines a minimum absolute difference sum having a minimum value among the respective computed absolute differences.

Accordingly, the absolute difference calculator 900 can obtain a motion vector indicating a correlation or similarity between the current macroblock and the reference macroblock through the determined minimum absolute difference sum.

Also, the absolute difference calculator 900 can obtain the compressed digital moving image by reducing temporal redundancy of the digital image using the obtained motion vector.

According to an aspect of the present invention, the absolute difference value calculator 900 can improve the transmission efficiency of a compressed digital image by approximating at least two higher order bits to one higher bit in descending order.

According to another aspect of the present invention, the absolute difference value calculator 900 can improve the transmission efficiency of the compressed digital image as the number of added upper bits increases, but may reduce the performance of the motion compression.

For example, the absolute difference calculator 900 can convert a high frequency-based discrete cosine transform (DCT) value using a minimum absolute difference sum, and use the transformed discrete cosine transform Compression can be implemented.

In this case, if the discrete cosine transform value for the minimum absolute difference sum computed within the search window range is equal to or larger than the predetermined threshold value, the performance of the motion compression may be reduced.

When the discrete cosine transform value for the minimum absolute difference sum is equal to or greater than the predetermined threshold value, the absolute difference value calculator 900 according to the embodiment of the present invention changes the approximation rule to a smaller number than the predetermined number And a control unit 940 for controlling the display unit 940. [

The second computing unit 920 may re-calculate the absolute difference sum for each absolute difference by applying the modified approximation rule, and the third computing unit 930 may update the updated difference sum with the minimum value among the respective re- It is possible to improve the performance of the motion compression by determining the minimum absolute difference sum.

10 is a flowchart illustrating an absolute difference calculation method according to an embodiment of the present invention.

Referring to FIG. 10, in step 1010, the absolute difference calculation apparatus calculates an absolute difference between pixels of a current macroblock and a reference macroblock having an M * N size within a search window range.

The pixels may be represented by bit strings, and the bit string may include lower bits and upper bits. The lower bits are located in the significant digits near the right in the bit stream and the upper bits are located in the significant digits near the left in the bit stream.

One macroblock may be pixels with an M * N size and may be 16 pixels with a 4 * 4 size in the H.264 video standard.

In step 1010, the absolute difference calculation device can process the absolute difference between the pixels of the current macroblock and the reference macroblock having the M * N size within the search window range in parallel, And the upper bits including the inverter bits.

In step 1020, the absolute difference calculation apparatus calculates an absolute difference sum with respect to each absolute difference in consideration of the upper bits added by the absolute difference calculation.

More specifically, in step 1020, an absolute difference sum for each absolute difference can be computed based on an approximation rule that approximates the number of higher-order added higher bits to one higher bit. The approximation rules can be applied to the logical sum gate carry method and can be implemented as logic elements.

In step 1030, the absolute difference calculation apparatus determines a minimum absolute difference sum having a minimum value among each calculated difference sum.

The absolute difference arithmetic operation apparatus according to the embodiment of the present invention changes the approximation rule to a smaller number than the predetermined number when the discrete cosine transform value for the minimum absolute difference sum is equal to or larger than the predetermined threshold value .

Accordingly, in step 1020, the modified approximation rule may be applied to re-compute the absolute difference sum for each absolute difference, and in step 1030, the updated minimum absolute difference having the minimum value among the respective re- The sum can be determined to improve the performance of the motion compression.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

100, 200, 300, 700, 900: Absolute difference arithmetic unit
910:
920:
930:
940:

Claims (8)

A first arithmetic unit for calculating an absolute difference (AD) between pixels of a current macroblock and a reference macroblock having an M * N size within a search window range;
A second operation unit for calculating a sum of absolute difference (SAD) for each of the absolute differences by considering the upper bits added by the absolute difference operation;
A third arithmetic unit for determining a minimum absolute difference (min SAD) having a minimum value among the respective computed absolute differences; And
And a control unit,
The second arithmetic unit selects two or more higher order bits in the highest order among the added higher order bits considering the performance of motion compression, and based on an approximation rule for approximating the selected upper order bits to one bit, Calculating the absolute difference sum with respect to each absolute difference,
The control unit
If the discrete cosine transform (DCT) value for the minimum absolute difference sum is greater than or equal to a predetermined threshold value, the upper bits are re-ordered by a smaller number than the predetermined number to change the approximation rule
Absolute summing calculator. delete The method according to claim 1,
The approximation rule
The OR gate is applied to the carry method.
Absolute summing calculator. delete The method according to claim 1,
The second calculation unit
And applying the modified approximation rule to re-perform the absolute difference sum for each absolute difference
Absolute summing calculator. Calculating an absolute difference between pixels of a current macroblock and a reference macroblock having an M * N size within a search window range;
Calculating an absolute difference sum with respect to each absolute difference by considering the upper bits added by the absolute difference operation; And
Determining a minimum absolute difference sum having a minimum value among the respective calculated absolute difference sums,
The calculating of the absolute difference sum may be performed by selecting two or more higher order bits in the highest order among the added higher order bits considering the performance of the motion compression and using an approximation rule And calculates the absolute difference sum with respect to each absolute difference,
Wherein the approximation rule includes re-ordering the upper bits with a smaller number than the predetermined number if the discrete cosine transform value for the minimum absolute difference sum is greater than or equal to a predetermined threshold value
Absolute difference sum calculation method. delete delete
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