KR101678405B1 - Nanowire transistor devices and forming techniques - Google Patents

Abstract

Techniques for customization of nanowire transistor devices to provide a wide range of channel configurations and / or materials systems within the same integrated circuit die are disclosed. According to one exemplary embodiment, the sacrificial fin is removed and replaced with a custom material stack of any composition and strain suitable for a given application. In one such case, each first sacrificial pin set is recessed or otherwise removed to replace the p-type layer stack, and each second sacrificial pin set is either recessed or otherwise removed and replaced with an n-type layer stack . The p-type layer stack may be completely independent of the process for the n-type layer stack, and vice versa. Various other circuit configurations and device variations are possible using the techniques provided herein.

Description

[0001] NANOIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES [0002]

Maintaining mobility improvement and short channel control as microelectronic device dimensions continue to change presents a challenge in device fabrication. Nanowire transistor devices can be used to provide improved short channel control. For example, silicon germanium (Si _x Ge _{1 -x} , where x <0.2) nanowire channel structures provide improved mobility, which is suitable for use in many conventional products.

Figures 1 to 15B illustrate various exemplary result structures with a process for forming nanowire or nanoribbon transistor devices in accordance with an embodiment of the present invention.
Figure 16 illustrates various exemplary result structures with a process for forming nanowire or nanoribbon transistor devices in accordance with another embodiment of the present invention.
Figure 17 illustrates various exemplary result structures with a process for forming a nanowire or nanoribbon transistor device in accordance with another embodiment of the present invention.
18A-18F illustrate a process for forming a bi-layer source / drain structure according to an exemplary embodiment.
19A and 19B illustrate a process for forming a bi-layer source / drain structure according to an exemplary embodiment.
Figure 20 illustrates a computing system implemented using one or more integrated circuit structures constructed in accordance with an exemplary embodiment of the present invention.
As will be appreciated, the drawings are not necessarily drawn to scale and are not intended to limit the claimed invention to the particular arrangements shown. For example, some drawings typically show straight, perpendicular, and smooth surfaces, but the actual implementation of the integrated circuit structure may have a less complete straight line, a right angle, and some features may be limited by the actual limitations It may have a surface topology or otherwise not smooth. Briefly, the drawings are provided merely to illustrate exemplary structures.

Techniques for customization of nanowire transistor devices to provide a wide range of channel configurations and / or materials systems within the same integrated circuit die are disclosed. According to one embodiment of the present invention, the sacrificial fin is removed and replaced with a custom material stack of any composition and strain suitable for a given application. In one such embodiment, each first sacrificial pin set is recessed or otherwise removed to be replaced with a p-type layer stack, and each second sacrificial pin set is recessed or otherwise And is replaced with an n-type layer stack. The p-type layer stack may be completely independent of the process for the n-type layer stack, and vice versa. Various other circuit configurations and device variations are possible using the techniques provided herein.

General Overview

Multi-gate transistors have evolved from a planar (single gate) to a fin (double or triple gate) for a gate-all-around or so-called nanowire / nanoribbon device. The 'wire' and 'ribbon' are distinguished by the fact that nanowires generally have a height-to-width ratio of 1: 1 whereas nano-ribbons are asymmetric in their height-to-width ratio, Other distinctions may be possible. In any case, both terms are used interchangeably herein, and the concepts and techniques described herein are equally applicable to two geometric features, as will be understood in light of this disclosure. Nanowire devices are typically fabricated from a two-dimensional planar stack of, for example, a silicon germanium (SiGe) alloy and a silicon layer. The use of a common layer stack for p-type and n-type transistors in the context of complementary metal oxide semiconductor (CMOS) processes using p-type and n-type metal oxide semiconductor transistors (PMOS and NMOS, respectively) Generates many non-trivial constraints. For example, in p-type and n-type regions, the composition of the layer stack should be the same. Also, the thickness of the layer stack in the p-type and n-type regions should be the same. In another known approach, a multi-epitaxial layer structure (superlattice) is fabricated and then decomposed / segmented using a first portion for the NMOS nanowire device and a second portion for the PMOS nanowire device. However, growing thickly strained layers is difficult due to the strain relaxation problem, especially as the pin geometry becomes larger. Strain relaxation can lead to, for example, excessive defects in the epi layer and reduce device performance, yield, and reliability.

Thus, according to one embodiment of the present invention, the initial structure has a patterned sacrificial fin in a shallow trench element isolation matrix. After the trench device isolation process, the sacrificial fin (or a subset of the sacrificial fin) is removed and replaced with an epitaxial material stack of any suitable composition and strain for a given application. In one such embodiment, each first sacrificial pin set is recessed or otherwise removed and replaced with a p-type layer stack, each second sacrificial pin set being recessed or otherwise removed to form an n-type layer stack Is replaced. As will be appreciated in light of this disclosure, the p-type layer stack may be completely independent of the process for the n-type layer stack, and vice versa.

Various other circuit configurations and device modifications are possible using the techniques provided herein as understood in light of this disclosure. For example, another exemplary circuit may be implemented using custom thickness tuning for an active wire component as opposed to a sacrificial inter-wire component. have. The various wire / ribbon dimensions may be adjusted to provide the desired effect (e.g., transistor density, channel strain, current density, contrasting wire, etc.). Another embodiment is to use a customized number of wires per transistor for the p-type and / or n-type portions (e.g., an n-type transistor having three or five wires and a p- And a given circuit design having a &lt; / RTI &gt; In a more general sense, another embodiment may be constructed using a customized number of wires per transistor for the first circuit type and the second circuit type. For example, a given configuration may include a transistor having one, two, and / or four nanowires per transistor, or a plurality of transistors, such as transistors having a common number of nanowires per transistor, but with different channel materials in some transistors (Or &lt; / RTI &gt; PMOS) transistors of the type shown in FIG. Still other embodiments may be configured using customized layer dimensions and / or compositions within the circuit die (e.g., using appropriate masking or selective deposition).

Still other embodiments may be constructed using different pin and / or material layer stacks. For example, one such embodiment may be configured using a pin for one device type and a wire for another device type. One such particular exemplary circuit may be constructed using a Si _x Ge _{1 -x} pin (x = 0.25) as well as a multi-layer stack of Si _x Ge _{1 -x} and silicon (x = 0.4) Circuit may be constructed using a column IV material pin and a III-V material multilayer stack (or III-V pin and IV multilayer stack). Still another embodiment can be configured using a plurality of pin types. For example, one exemplary circuit may be constructed using gallium arsenide pins for NMOS as well as SiGe pins for PMOS. The diversity of device polarity and / or channel composition is not substantially limited when using the various techniques provided herein.

Such techniques, such as those provided herein, enable meaningful customization of the nanowire stack to provide a wide range of configuration and / or material systems. A scanning electron microscope or transmission electron microscope cross-section perpendicular to the gate line or pin may be used to illustrate a custom nanowire stack in a non-planar transistor structure in accordance with some embodiments of the present invention. For example, in some such embodiments, the SEM / TEM cross section will show a p-type channel wire having a first configuration and an n-type channel wire having a second configuration different from the first configuration.

Methodology and architecture

Figures 1 through 15B illustrate various exemplary result structures with a process for forming nanowire transistor devices in accordance with an embodiment of the present invention. As can be seen, this exemplary process utilizes recesses and alternate techniques to form the nanowires, which recesses and alternate techniques result in a pre-fabricated two-dimensional plane consisting of a plurality of layers patterned into the fin And a structure distinguished from the structure formed from the stack is calculated. For example, a structure implemented in accordance with an embodiment of the present invention may reveal various channel materials and / or configurations, which are formed in the context of a self-aligned process by recess provided upon removal of the sacrificial fin material .

Figure 1 illustrates a structure resulting from the patterning of a sacrificial fin and a shallow trench isolation (STI) process. As can be seen, a substrate is provided. The substrate is a blank substrate that must be prepared for the next semiconductor process, for example, by forming a plurality of sacrificial fin structures therein. Alternatively, the substrate may be a partially formed semiconductor structure having a sacrificial fin structure formed on top of it. In another embodiment, the substrate may be a partially formed semiconductor structure that has been sacrificed fin structure formed thereon and later recessed or otherwise removed to provide a pin recess after the STI process. Thus, the substrate may be a blank, have preformed fins, have preformed fins and STI, or have preformed STI and pin recesses. In one such exemplary embodiment, the substrate has a preformed fin and an STI, the top of which is the same height as the top surface of the STI, and the top of at least some of the remaining pins, Lt; RTI ID = 0.0 &gt; STI &lt; / RTI &gt; In this sense, it is noted that the operation of fin recessing is not necessarily required as long as a pin with an upper portion located under the STI is provided.

A bulk substrate, a semiconductor on insulator substrate (XOI), X is a semiconductor material such as Si, Ge or Ge-enriched Si), and any number of suitable substrates Configurations may be used herein. In a more general sense, any substrate on which a sacrificial fin can be formed on top of the next transistor forming process can be used. In one particular illustrative case, the substrate is a silicon bulk substrate. In other implementations, the semiconductor substrate may be formed of an alternative material, including, but not limited to, germanium, indium antimonide, lead tellurium, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony, The material may or may not be combined with silicon. Additional semiconductor materials classified as Group III-V or Group IV materials may also be used to form the substrate. Although some examples of materials on which a substrate can be formed are described herein, all materials that can be provided as a base upon which a semiconductor device can be mounted are within the spirit and scope of the claimed invention.

The sacrificial pin may be formed using any number of suitable processes. Some embodiments may utilize, for example, deposition and patterning of a hard mask on a substrate. This may be accomplished by depositing one or more hardmask materials (e.g., silicon dioxide, silicon nitride, and / or other suitable hardmask material) and temporarily depositing a lower region of the fin (such as a diffusion or active region of the transistor device) Patterning a resist on a portion of the remaining hard mask to protect it, and removing the unmasked (unresisted) portion of the hard mask (e.g., using a dry etch or other suitable hard mask removal process) Etch, and then leaving the patterned mask by stripping the patterned resist material. &Lt; RTI ID = 0.0 &gt; [0050] &lt; / RTI &gt; In some such embodiments, the resulting hardmask may include a two-layer hardmask (not shown) comprised of a bottom oxide (e.g., a native oxide such as silicon dioxide resulting from oxidation of the silicon substrate) (two-layer hardmask). As is evident, any number of suitable mask configurations may be used in forming the sacrificial fin. Although the illustrated embodiment illustrates a pin having a width that does not depend on the distance from the substrate, the pin may be narrower at the top than the bottom in another embodiment, or may be wider at the top than the bottom in another embodiment , Or all other width variations and uniformity (or non-uniformity). It should also be noted that in some embodiments the width variation may be symmetrical or asymmetric. Further, although the pins are all shown to have the same width, some pins may be wider than other pins and / or may be shaped differently from the other pins. For example, in one embodiment, the pin that should be used in the generation of the NMOS transistor may be narrower than the pin that should be used in the generation of the PMOS transistor. Other arrangements are possible, as will be appreciated.

As further seen in Fig. 1, a shallow trench is provided in the substrate to provide a shallow trench isolation (STI) around the plurality of fins in accordance with one embodiment of the present invention, followed by filling with an insulating material. Any number of pins may be provided in any desired pattern or configuration suitable for a given application. Shallow trench etching can be achieved using standard photolithography, for example when it is desired to do so in combination with wet or dry etching or etching. The geometric characteristics (width, depth, shape, etc.) of the trenches may vary from embodiment to example as will be understood, and the claimed invention is not intended to be limited to any particular trench geometric feature. In one particular exemplary embodiment having a two-layer hard mask implemented with a bulk silicon substrate and a bottom silicon dioxide (SiO ₂ ) layer and a top silicon nitride layer, a trench having a thickness of, for example, about 100 A to 5000 A Dry etching is used. As is evident, any number of trench configurations, depending on the required pin height, may be used. Later, the trenches can be filled using any number of suitable deposition processes. In one particular exemplary embodiment having a silicon substrate, the insulating STI filling material is SiO _2, but any number of suitable insulating dielectric materials may be used to form a shallow trench isolation (STI) structure thereon. Generally, a deposited or otherwise grown insulating dielectric material for filling the trench can be selected based on, for example, compatibility with the native oxide of the substrate material. Note that the STI trenches may be circular or polygonal in nature and that all references to the trench "side" are intended to refer to all such configurations and should not be construed to imply any particular geometry. Figure 1 further demonstrates how an STI insulating material can be planarized using, for example, chemical-physical planarization (CMP) or other suitable process that can planarize the structure. In the illustrated exemplary embodiment, the mask on top of the sacrificial fin is completely removed. Other embodiments may utilize selective planarization configured to leave a portion of the mask in place, and a portion of the mask left in place may be used in subsequent processing, as shown in FIG.

Figure 2 illustrates a process and resulting structure in which some pins are masked and other pins are recessed in accordance with one embodiment of the present invention. In this exemplary case, four pins are shown in which two pins are masked alternately and two pins are recessed (e. G., Recessed, masked, recessed, and masked) . The mask may be provided, for example, as already described, or may be left out of the STI process. In any case, the mask may be any suitable material that will resist recess etching of unmasked fins and subsequent processing (e. G., Epitaxial processing) to fill these recesses. Any suitable etch process (e.g., wet and / or dry etch with masking and / or etch selectivity) may be used. In one exemplary embodiment, the recess etch is a selective etch that removes the unmasked fin material but does not remove the STI or mask material. In this case, it is noted that the mask material may also be implemented using an STI material (e.g., silicon dioxide) or any other material that is resistant to pin recess etching (e.g., silicon nitride) . In one particular exemplary embodiment, the sacrificial fin is silicon and the mask is silicon dioxide and / or silicon nitride, and the recess etch is a wet etch (e.g., etching a potassium hydroxide or unmasked silicon pin, Gt; etchant &lt; / RTI &gt; that does not etch the etchant). The depth of the sacrificial fin etch may vary from one embodiment to the next, and may include recesses (as shown in Figure 2), or recesses into the substrate through the bottom of the original pin Mirror image of the pedestal pedestal), or may be the same height as the bottom of the STI trench. As will be appreciated in light of this disclosure, the depth of the pin recess will vary depending on factors such as the number of wires and / or ribbons per transistor, substrate thickness, and / or pin height. In some embodiments, the etching process may change the width of the recess, and in some cases, the top of the trench may be wider than the bottom of the trench. In another embodiment where the original sacrificial pin is wider at the bottom than at the top, the top may be widened closer to the width at the bottom or may exceed the width at the bottom. In another embodiment, the recess eventually has a slight hourglass shape and may be wider at the top and bottom than the middle. In yet another embodiment, the width may be substantially unchanged by the etching process. In a more general sense, the shape of the recess / pin may be modified by the etching process, but this is not necessary.

Figure 3 illustrates a process comprising selectively growing or otherwise forming a multi-layer stack in each recessed fin, according to one embodiment of the present invention, and then optionally planarizing. As can be seen in this exemplary case, the recessed fin was filled with a specific multilayer stack configuration comprising five layers (L1-A to L5-A). Each of the layers L1-A through L5-A may be fabricated according to any of the number of parameters of interest, such as layer thickness, polarity, doping, composition and / . Each stack typically includes one or more layers that form nanowires or nanoribbons (depending on the width to height ratio) and one or more layers that are sacrificial inter-wire materials (or spacer materials). The resulting multi-layer fin structure is generally referred to as multi-layer stack A in Fig. 3 and may also be referred to as a type A multi-layer stack. Note that in some embodiments a planarization process for the multilayer stack A to facilitate subsequent processing may also be used to remove the mask from the residual sacrificial fin.

Figure 4 illustrates a process and resulting structure in which some completed pins (type A multi-layer stack) of finished pins are masked and the remaining residual pins are recessed according to one embodiment of the present invention. The previous discussion of masking and recessing the fins with reference to Fig. 2 can be equally applied here. Any number of suitable masking and / or selective etching processes may be used, and the claimed invention is not intended to be limited to any particular process.

Figure 5 illustrates a process for selectively growing or otherwise forming a multi-layer stack in each recessed pin formed in Figure 4 in accordance with an embodiment of the present invention, and then optionally including a planarization step do. As can be seen in this exemplary case, this second set of recessed fins was accidentally filled with a specific multilayer stack that also includes five layers (L1-B to L5-B). Each layer L1-B through L5-B may be configured as required according to any number of parameters of interest, such as layer thickness, composition, polarity, doping, and / or strain. The resultant multi-layer fin structure in accordance with this process is generally referred to as multi-layer stack B in Fig. 5 and may also be referred to as a type B multi-layer stack. As with the Type A stack, each Type B stack typically includes one or more layers that form nanowires or nanoribbons (depending on the width to height ratio) and one or more layers that are sacrificial inter-wire materials (or spacer materials) . It should be noted that the type A layer stack may be completely independent of the process for the type B layer stack, and vice versa. Thus, according to another embodiment, the number of stack layers in one type of stack may differ from the number of layers in another type of stack.

Figure 6 illustrates the resultant structure after a process of removing the masking layer is performed and after all required planarization in accordance with an embodiment of the present invention. Note that planarization can be localized to the required area and the top of the unmasked pin with the STI layer can be used as an effective etch stop. As will be appreciated in light of the present disclosure, the resulting structure constructed using a multi-layer stack of types A and B may be used for a variety of applications. In a CMOS application, the Type A multi-layer stack can be composed of NMOS transistors, and the Type B multi-layer stack can be composed of PMOS transistors. Alternatively, the Type A multilayer stack may be comprised of a first type NMOS transistor, and the Type B multilayer stack may be comprised of a second type NMOS transistor. Alternatively, the Type A multi-layer stack can be composed of PMOS transistors of the first type and the Type B multi-layer stack can be composed of PMOS transistors of the second type. It is also noted that other embodiments may have any number of various multilayer stacks and that the claimed invention is not intended to be limited to two types as shown. For example, one embodiment may include four distinct multilayer stack types A, B, C, and D, the type A multi-layer stack is comprised of a first type NMOS transistor, and the type B multi- One type of PMOS transistor, the type C multilayer stack consists of a second type NMOS transistor, and the type D multilayer stack consists of a second type PMOS transistor. Yet another exemplary embodiment provides a combination of a recess-and-replace based transistor and an original pin-based transistor in the same integrated circuit in addition to all of the provided multilayer stacks as described herein Lt; RTI ID = 0.0 &gt; non-recessed &lt; / RTI &gt; In a more general sense, any arbitrary number of permutations of the stack type may be implemented (with or without the original pin) as will be understood in light of this disclosure.

Figure 7 illustrates a process and resulting structure in which the trench oxide (or other STI material) of the structure shown in Figure 6 has been recessed in accordance with one embodiment of the present invention. This can be done, for example, by masking the finished multilayer stacks A and B and etching the STI to an appropriate depth or by using a selective etch scheme without a mask. Any suitable etch process (e.g., wet and / or dry etch) may be used. For example, in one particular exemplary embodiment, where the STI is implemented using silicon dioxide and each top layer of the multi-layer stacks A and B is implemented using silicon, the STI recess process is performed using hydrofluoric acid ) Or other suitable etchant that is selective to non-STI material (non-STI material). As will be appreciated, masks that are impervious to the STI etchant or otherwise resistant to the STI etchant can be patterned to protect the multi-layer stacks A and B when needed. The depth of the STI recess may vary from one embodiment to the next, and in this exemplary embodiment is the same height as the top of the remaining sacrificial fin material (or pedestal). As will be further understood in light of this disclosure, the depth of the STI recess will depend on factors such as the number of wires and / or ribbons per transistor, the STI thickness and required isolation, and / or the pin height. In various embodiments, this partial removal of the STI may change the width of one or more of the multi-layer stacks A and B, and in one embodiment the top of the stack may be consequently relatively narrower than the bottom of the stack . In another embodiment, the relative width along the height of the stack can be maintained relatively unchanged. In some embodiments, stacks A and B may comprise different materials, and the width of one stack may be more than the width of the other stack. This width variation as described herein with reference to FIG. 2 may be applicable to all of the etching processes described in this disclosure.

Figure 8 illustrates a process and resulting structure in which a dummy gate electrode material is deposited on top of multilayer stacks A and B followed by a plurality of sacrificial gates in accordance with one embodiment of the present invention. As further shown, a dummy gate dielectric may be provided prior to deposition of the dummy gate electrode material. In some embodiments, such a gate dielectric is referred to as a dummy gate dielectric in the sense that such a gate dielectric can be removed and replaced in the next process. It is noted, however, that in other embodiments a gate dielectric intended for the final structure may be used. Exemplary dummy gate dielectric materials include, for example, silicon dioxide, and exemplary dummy gate electrode materials include polysilicon, but any suitable dummy / sacrificial gate dielectric and / or electrode material may be used. As will be appreciated, the dimensions of the gate material will vary from one embodiment to the next and may be configured as desired, depending on factors such as required device performance attributes, device size, and gate insulation.

Figure 9 illustrates a process and resulting structure in which an additional insulator layer is deposited and planarized over the dummy gate electrode material in accordance with one embodiment of the present invention. Any suitable deposition process (e.g., CVD, PVD, ALD, etc.) may be used and the deposited insulator material may be the same material as, for example, an STI fill material (e.g., silicon dioxide) But may be any suitable material having insulating / dielectric properties. Planarization of the additional insulator material can be performed, for example, using CMP using the dummy gate electrode material as an etch stop. Alternatively, the CMP process may proceed into the dummy gate electrode to provide a dummy gate electrode having a particular height higher than the top of the multilayer stacks A and B.

10 illustrates a process and resulting structure in which the Type A multi-layer stack and the corresponding dummy gate electrode material are masked, and FIG. 11 illustrates a non-masked dummy gate electrode material (e. G. , Polysilicon) is etched to expose the channel region of the multilayer stack B, and the resulting structure. Any suitable mask material and patterning followed by etching may be used. For example, it is further assumed that the mask can be implemented using silicon oxide to protect the gate electrode material over the multi-layer stack A, the additional insulator material is silicon dioxide, and the dummy gate electrode material is polysilicon. In this exemplary case, the unmasked dummy gate electrode material can be selectively etched using, for example, chlorine (Cl ₂ ) and hydrogen bromide (HBr), and chlorine (Cl ₂ ) and hydrogen bromide It will remove the polysilicon but will not remove the silicon dioxide. A variety of different masks and selective etching schemes may be used.

Figure 12 illustrates a process and resulting structure in which a sacrificial inter-wire material is etched away or otherwise removed from a first channel type in accordance with an embodiment of the present invention. In some embodiments, this process may be referred to as ribboning the channel differently depending on the dimensions of the remaining layers (L2-B and L4-B) of the stack. All suitable etching techniques can be used. In one exemplary embodiment, the sacrificial layers (L1-B, L3-B and L5-B) are implemented using silicon and the channel nanowires (L2-B and L4-B) . In this case, the sacrificial silicon layers (L1-B, L3-B and L5-B) selectively remove silicon but do not remove the SiGe nanowire / nanoribbon structures (L2-B and L4-B) As shown in FIG. Etching chemistries such as aqueous hydroxide chemistries including, for example, ammonium hydroxide and potassium hydroxide, may be used to selectively etch silicon but leave SiGe in place. As will be understood and practically speaking, the terms 'wire' and 'ribbon' and their derivatives, as used herein, are functionally identical and can be used interchangeably in general. However, as will be further understood, with reference to the height-to-width ratio, the ribbon is structurally different from the wire. For example, a wire may have a height-to-width ratio of 1: 1, but the ribbons may have an asymmetrical height-to-width ratio (e.g., 1: 2, etc.).

Figure 13 illustrates a process in which the exposed channel regions of a Type B multi-layer stack are refilled using a different dummy material than the dummy gate electrode material to act substantially as a mask on top of these Type B multi-layer stacks in accordance with an embodiment of the present invention; and The resulting structure is shown. This process may further include a planarization step of removing all excess dummy fill material and / or all mask material above the type A multi-layer stack to be used for the first transistor device type in some exemplary embodiments.

14 illustrates a process and resulting structure in which a non-masked residual dummy gate electrode material is etched to expose a channel region of the multilayer stack A, in accordance with an embodiment of the present invention. Any suitable material may be used to refill the dummy gate region of a Type B multi-layer stack, such as silicon dioxide or other material, which may be easily removed but is resistant to the etch plan to remove the remaining dummy gate electrode material on top of the multi- Can be used. For example, it is further assumed that the refill material for the dummy gate region of the Type B multilayer stack may be silicon dioxide, the additional insulator material is silicon dioxide, and the remaining dummy gate electrode material is polysilicon. In this exemplary case, the residual dummy gate electrode material may be selectively etched using, for example, chlorine (Cl ₂ ) and hydrogen bromide (HBr), chlorine (Cl ₂ ) and hydrogen bromide (HBr) But will not remove silicon dioxide. As will be understood in light of the present disclosure, various other selective etching schemes may be used.

15A illustrates a process and resulting structure in which a sacrificial inter-wire material from a second channel type is etched away or otherwise removed in accordance with one embodiment of the present invention. As already indicated for the first channel type discussed with reference to Fig. 12, this process is to ribbon the channel differently depending on the dimensions of the remaining layers (L1-A, L3-A and L5- . All suitable etching techniques can be used again. In one exemplary embodiment, the sacrificial layers L2-A and L4-A are implemented using SiGe and the channel nanowires L1-A, L3-A and L5-A are implemented using silicon . In this case, the sacrificial silicon layers (L2-A and L4-A) are selectively removed using wet etching that selectively removes SiGe but does not remove the silicon nanowire structures (L1-A, L3-A and L5-A) Lt; / RTI &gt; For example, a carboxylic acid / nitric acid / hydrogen fluoride chemistry and an etching chemistry such as citric acid / nitric acid / hydrogen fluoride may be used to selectively etch SiGe but leave the silicon in place. Thus, in embodiments in which the multilayer structures A and B are embodied as alternating layers of silicon and SiGe, the silicon layer may be removed from the multilayered pin structure to form SiGe nanowires, or may be removed from the multilayered pin structure The SiGe layer can be removed.

15A, as well as the exposed layers of the L-A, L3-A and L5-A layers of the Type A multilayer stack and the L2-A and L4-A layers of the Type B multilayer stack also shown in the partially alternating view of FIG. The channel portion eventually becomes the channel region in the nanowire-based structure, according to one embodiment of the present invention. In some such embodiments, channel engineering or tuning may be performed in the process steps depicted in Figures 15A and 15B. For example, in one embodiment, the exposed channel portions of the L2-A and L4-A layers of the Type B multilayer stack and / or the L1-A, L3-A and L5- And / or may be thinned using an etching process. This thinning process may be performed, for example, at the same time as the wire leaves the adjacent sacrificial layer (e.g., through selective etching or other suitable removal process) as described herein. Thus, the initial wire formed may have an initial thickness that is thinned to an appropriate size in the channel region within the nanowire device, regardless of the size setting of the source and drain regions of the nanowire device.

Vary in the same horizontal plane wire / Ribbon material

Various alternative embodiments and modifications will be apparent in light of the present disclosure. For example, in the illustrated embodiment, the nanowires L1-A, L3-A, and L5-A of the multilayer stack A are on the same horizontal plane as the nanowires L2-B and L4-B of the multilayer stack B does not exist. In another exemplary embodiment, one multi-layer stack type nanowire is on the same horizontal plane as another multi-layer stack type nanowire. 16 shows a structure having four different multi-layer stack types A, B, C and D, wherein the nanowires / nanoribbons of the multi-layer stack types A and C are the same And the nanowires / nanoribbons of multilayer stack types B and D are on the same horizontal plane. In one such special case, the nanowire / nanoribbon of the multi-layer stack type A may be silicon, the nanowire / nanoribbon of the multi-layer stack type C may be SiGe, and the nanowire / Gallium arsenide, and the nanowire / nanoribbons of the multilayer stack type D may be indium arsenide. As used herein, being in the same horizontal plane means that there is at least some overlap between the nanowire / nanoribbon of the first multi-layer stack type and the second multi-layer stack type, and thus at least one common plane Means passing through the first multi-layer stack type and the second multi-layer stack type nanowire / nano ribbon. It should be noted, however, that this overlap is not necessary, as will be appreciated in light of the present disclosure. In a more general sense, each multi-layer stack type may be implemented independently of other multi-layer stack types and may be implemented using a common plane and / or material composition for another multi-layer stack type, or without such common plane and / Lt; / RTI &gt; A full range of pin / multilayer stack diversity for homogeneity may be enabled by the techniques provided herein.

Pin and multilayer stack hybrid

Figure 17 shows another process and resulting structure in which the nanowire device is constructed using a combination of a fin and a multi-layer stack. The two pins shown can be implemented using the same or different materials as the two illustrated multi-layer stack A / B. For example, in one embodiment, the fins may be implemented using a first alloy composition of SiGe, and the multi-layer stack may be implemented using a silicon / SiGe stack having a second SiGe composition. Alternatively, the fin can be implemented using, for example, a column IV material, and the multi-layer stack can be implemented using a III-V material. For example, the fins may be silicon and / or SiGe alloys, and the multilayer stack may be an alternating layer of gallium arsenide and aluminum gallium arsenide.

Various pin / stack materials and configurations will be apparent in light of this disclosure, and the claimed invention is not intended to be limited to any particular invention. Factors such as required circuit performance, available materials, fab capability, and application specific details required to customize the nanowire stack and / or pin as described herein may be taken into consideration . This customization can be performed, for example, for n-type or p-type polarity, or for all transistor performance factors such as operating frequency, current density, power capability, gain, bandwidth,

Gate and source / drain  formation

After formation of the discrete channel regions, such as in the various exemplary embodiments described in FIGS. 15A, 15B, 16 and 17, in some exemplary embodiments, gate dielectric and gate electrode processing may be performed, And a drain contact may be added. This post-channel processing may be performed, for example, as is normally done. Complete fabrication of transistor-based integrated circuits, such as intermediate planarization and cleaning processes, silicidation processes, contact and interconnect forming processes, and deposition-masking-etch processes Lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt; In addition, some embodiments may be used where it is desired to do a remove-and-replace process (without using an intact pin or multilayer stack) to form the source / drain regions . In light of the present disclosure, various subsequent arrangements will be apparent.

In some exemplary embodiments, the gate dielectric may, for example, be any suitable oxide or high -k (high-k) gate dielectric materials such as SiO _2. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide , Yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric layer to improve quality when a high-k material is used. Generally, the thickness of the gate dielectric should be sufficient to electrically isolate the gate electrode from the source and drain contacts. The gate electrode material may be, for example, polysilicon, silicon nitride, silicon carbide, or a metal layer (e.g., tungsten, titanium nitride, tantalum, tantalum nitride), but other suitable gate electrode materials may also be used. The gate electrode then formed may be covered with a mask to be protected during the next processing. The gate dielectric, the gate electrode, and any optional mask material may generally be referred to as a gate stack.

Once the gate stack is fabricated, the source / drain regions can be processed. This process can include exposing the source / drain regions, for example, by etching or otherwise removing additional insulator material from around the pin or multi-layer stack, so that a source drain contact can be provided, . &Lt; / RTI &gt; Typical source drain contact materials include, for example, tungsten, titanium, silver, gold, aluminum, and alloys thereof.

As already explained, some embodiments may be used where it is desired to do so (without using an intact pin or multilayer stack) for a removal-and-replacement process to form the source / drain regions. Figures 18A-18F illustrate this exemplary process for providing a transistor structure having a bi-layer source / drain structure in accordance with an exemplary embodiment. As will be appreciated, although only one pin / multilayer stack is shown for simplicity of discussion, the same concept applies to structures having all the number of pin / multilayer stacks and to any number of configurations as described herein The same can be applied. Figure 18A illustrates one or more nanowires that provide gate electrodes, or gate-all-around devices, formed on three surfaces of the fins to form three gates (i.e., triple gate devices). A gate dielectric material is provided between the pin / multilayer stack and the gate electrode, and a hard mask is formed over the gate electrode. 18B shows the resultant structure after etching following deposition of an insulating material leaving a coating of insulator material on all vertical surfaces to provide a spacer on the sidewalls of the gate electrode and the fin / multilayer stack. Figure 18c shows the resultant structure after an additional etch treatment to leave spacers only on opposite sidewalls of the gate electrode by removing excess insulating / spacer material from the sidewalls of the pin / multilayer stack. 18D shows the resultant structure after recess etch to form a recess so that the recessed fin / multilayer stack has a top surface located below the STI by removing the pin / multi-layer stack in the source / drain region of the substrate. do. Note that other embodiments may not be recessed (e.g., the source / drain regions are at the same height as the STI layer or over the STI layer). 18E shows the resultant structure after growth of the epitaxial liner, which in some embodiments includes a thin p-type and substantial amount of silicon (e.g., SiGe with silicon or 70 atom percent silicon) Or may be pure germanium (e.g., a separate germanium layer, or a non-detectable layer integrated or otherwise included in the resulting cap composition). Figure 18f shows the resultant structure after growth of the epitaxial source / drain cap, which may be p-type in some exemplary embodiments and includes mainly germanium but less than 20 atomic percent Tin or other suitable alloy material. As will be further appreciated, it is noted that an alternative to the triple gate configuration is a double gate architecture, and the double gate architecture will include a dielectric / insulator layer on top of the pin. Further, the exemplary shapes of the liner and cap forming the source / drain regions shown in Figs. 18e and 18f are not intended to limit the claimed invention to any particular source / drain type or formation process, Note that the source / drain geometry will be apparent (e.g., a source / drain region that is round, square, or rectangular may be implemented).

19A illustrates a nanowire transistor structure having a bi-layer source / drain structure according to another exemplary embodiment. Some nanowire transistors that depend on a particular design have, for example, four effective gates. 19A shows a nanowire channel architecture with two nanowires, while another embodiment may have any number of wires. The nanowire may be implemented using, for example, p-type silicon or germanium or SiGe nanowires. As can be seen, one nanowire may be formed or otherwise provided in the recess of the substrate, and the remaining nanowires may float substantially in a source / drain material dual layer configuration comprising a liner and a cap layer. As with the pin configuration, the nanowire can be replaced in the source / drain regions using a dual layer configuration of source / drain material (e.g., relatively thin silicon or germanium or SiGe liner and relatively thick high density germanium cap) . Alternatively, a bi-layer configuration may be provided around the originally formed nanowire as shown (the liner is provided around the nanowire and then the cap is provided around the liner). Figure 19b also shows a nanowire configuration with a plurality of nanowires, but in this example case the non-channel-material (NCM) is not removed from between the individual nanowires during the nanowire forming process , Which can be performed as already described. Thus, one nanowire is provided in the recess of the substrate, and the remaining nanowires are positioned substantially over the non-channel material. It is noted that the nanowires are active through the channel, but the non-channel material is not. As can be seen, the bilayer source / drain configuration of the liner and cap can be provided around all other exposed surfaces of the nanowire.

As will be appreciated, the depicted methodology may be used in lithography, chemical vapor deposition (ALD), atomic layer deposition (ALD), spin-on deposition (SOD), physical vapor deposition (PVD) May be performed using any suitable standard semiconductor process including dry and wet etching (e.g., isotropic and / or anisotropic). Alternative deposition techniques can also be used, for example, various material layers can be thermally grown. As will be further appreciated in light of this disclosure, any number of suitable materials, layer geometry characteristics, and formations may be used to implement an embodiment of the present invention to provide a custom nanowire device or structure as described herein. Process can be used.

An exemplary system

Figure 20 illustrates a computing system implemented using one or more integrated circuit structures constructed in accordance with an exemplary embodiment of the present invention. As can be seen, the computing system 1000 houses the motherboard 1002. The motherboard 1002 can include a plurality of components including but not limited to a processor 1004 and at least one communication chip 1006 (two communication chips 1006 are shown in this example) A plurality of components may be physically and electrically coupled to the motherboard 1002, respectively, or may be integrated therein. As will be appreciated, the motherboard 1002 can be any printed circuit board, for example a mainboard or a daughterboard mounted on a mainboard or a unique board of the computing system 1000 . The computing system 1000 may include one or more other components that may be physically and electrically coupled to the motherboard 1002 or may not be coupled differently depending on the application. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processor, digital signal processor, crypto processor, chipset, antenna, (Hard disk drives, compact discs (CD), DVD (compact discs), DVD players, DVD players, digital versatile disks, and the like) mass storage devices. One of the components included within the computing system 1000 may include one or more integrated circuit structures constructed using nanowire transistors with customized channels. Note that in some embodiments, a plurality of functions may be integrated into one or more chips (e.g., the communications chip 1006 may be part of the processor 1004 or otherwise integrated into the processor 1004) ).

Communication chip 1006 enables wireless communication for delivery of data to and from computing system 1000. The term "wireless" and its derivatives, refers to circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data using modulated electromagnetic radiation through a non- Can be used to illustrate. The term "wireless" and its derivatives do not imply that the associated device does not contain any wires, but in some embodiments the associated device may not include any wires at all. The communication chip 1006 may be a wireless communication device such as Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA +, HSDPA +, HSUPA +, EDGE, But not limited to, TDMA, DECT, Bluetooth, and derivatives thereof, as well as all other wireless protocols designated as 3G, 4G, 5G or higher. The computing system 1000 may include a plurality of communication chips 1006. For example, the first communication chip 1006 may be dedicated to a shorter range of wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 may be GPS, EDGE, GPRS, CDMA, WiMAX, May be dedicated to longer range wireless communications such as Ev-DO.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments of the invention, the integrated circuit die of processor 1004 includes one or more nanowire transistors having customized channels as described herein. The term "processor" refers to any device that processes electronic data from a register and / or memory to, for example, convert registers and / or electronic data from memory to other electronic data that may be stored in registers and / May refer to a portion of the device.

The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. According to some such exemplary embodiments, the integrated circuit die of communication chip 1006 includes one or more nanowire transistors with customized channels as described herein. As will be understood in light of the present disclosure, multi-standard wireless capability can be integrated directly into the processor 1004 (e.g., the functionality of all communication chips 1006 may be implemented in separate communications Integrated into the processor 1004 without a chip). It is also noted that the processor 1004 may be a chipset with such wireless capability. Briefly, any number of processors 1004 and / or communication chips 1006 may be used. Likewise, one chip or chipset may have a plurality of functions integrated therein.

In various embodiments, the computing system 1000 may be a computing device such as a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, An entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In a further embodiment, the computing system 1000 may be any other electronic device that processes data or utilizes nanowire transistor devices as described herein (e.g., p Type device and a CMOS device having both n-type devices). As will be appreciated in light of the present disclosure, various embodiments of the present invention allow for the use of nanowire transistors custom made on the same die to have various channel configurations (e.g., Si, SiGe, or Si / SiGe) Can be used to improve performance for products fabricated at process nodes (e.g., in the micrometer range, or above the submicrometer range).

Various embodiments will be apparent, and the features described herein may be combined in any number of configurations. One exemplary embodiment of the present invention provides a method for forming a nanowire transistor structure. The method includes forming a plurality of fins on a substrate, and forming shallow trench isolation portions on opposite sides of each fin, wherein each fin extends from the substrate. The method includes masking a first set of pins to leave a first set of non-masking sacrificial pins, recessing a first set of non-masking sacrificial pins to provide a first set of recesses, Wherein each of the first type of multilayer stacks comprises at least two different layers, and at least one of the at least two different layers comprises at least two different layers, Lt; RTI ID = 0.0 &gt; nanowire &lt; / RTI &gt; In some such cases, the method may include planarizing each multilayer stack of the first type. In some cases, planarizing each of the first type of multi-layer stacks includes removing masking material on top of the first set of pins. In some cases, the method may include masking each of the first type of multi-layer stacks to leave a second set of non-masking sacrificial pins, and recessing a second set of non-masking sacrificial pins to provide a second set of recesses And forming a second type of multilayer stack in each recess of the second set of recesses, each of the second type of multilayer stacks including at least two different layers. In some such cases, each of the first type of multilayer stack and the second type of multilayer stack is comprised of a layer formed of nanowires and a sacrificial layer, and at least one common plane selected along a single axis comprises at least one Layer stack and the nanowire layer of each of the at least one multi-layer stack of the second type. In other such cases, each of the first type of multi-layer stack and the second type of multi-layer stack is composed of a layer formed of nanowires and a sacrificial layer, and each of the nano- There is no selected common plane along a single axis through the wire layer. In some cases, a multi-layer stack of a first type is configured differently (e.g., with respect to composition and / or strain) than a multi-layer stack of a second type. For example, in one exemplary case, a first type of multi-layer stack is configured for one of PMOS or NMOS (e.g., PMOS) and a second type of multi-layer stack is configured for the other of PMOS or NMOS For example, NMOS). In some cases, the method may include planarizing each of the multi-layer stacks of the second type. In one such case, the step of planarizing each of the second type of multilayer stacks comprises removing masking material on top of the multilayer stack of the first type. In some cases, the method includes recessing the shallow trench isolation on the substrate to expose the sidewalls of the first type of multi-layer stack, forming a dummy gate structure over the multi-layer stack of the first type, Forming an additional insulator layer on the first type of multilayer stacks on either side of the structure and planarizing the additional insulator layer over the dummy gate structure. In some such cases, the method may include forming a pin and / or multilayer stack set formed on the substrate and used for the first type of transistor device to leave a non-masking multilayer stack set to be used for the second type of transistor device, Etching an unmasked portion of the dummy gate structure to expose a first channel region of a respective multi-layer stack of a non-masking multilayer stack set to be used for a second type of transistor device; Etch and remove the sacrificial inter-wire material from each first channel region to provide one or more channel nanowires for each of the transistor devices. In one such case, the method further comprises refilling the dummy gate structure to cover the first channel region, removing the first pin and / or the masking material over the multilayer stack set to be used for the first transistor device type, And planarizing the filled dummy gate structure. In some cases, the method may include etching the remaining dummy gate structure to expose a second channel region of each of the pins and / or multi-layer stacks formed on the substrate and to be used for the first type of transistor device. In one such case, the second channel region consists of a multilayer stack, and the method removes the sacrificial inter-wire material from each second channel region by etching to provide one or more channel nanowires of the first type of transistor device . In yet another such case, the second channel region is made up of fins and not a multilayer stack. In some cases, the method includes forming a gate stack for each of a first type of transistor device and a second type of transistor device, and forming a source / drain region for each of the first type of transistor device and the second type of transistor device, . Various modifications will be apparent. For example, another embodiment provides an integrated circuit formed by a method as variously defined in this paragraph.

Yet another embodiment of the present invention provides a nanowire transistor device. The nanowire transistor device includes a first plurality of pins on a substrate, and each of the first plurality of pins extends from the substrate. The nanowire transistor device further includes a multi-layer stack of a first type on each of the first plurality of pins, wherein each of the multi-layer stacks of the first type comprises a channel region having one or more nanowires. The nanowire transistor device further comprises a second plurality of pins on the substrate, wherein each of the pins of the second type extend from the substrate. The nanowire transistor device further comprises a multi-layer stack of a second type on each pin of the first plurality of pins, and each of the multi-layer stacks of the second type comprises a channel region having one or more nanowires. One or more nanowires of a first type of multilayer stack are configured differently (e.g., with respect to composition and / or strain) with one or more nanowires of a second type of multilayer stack. In some cases, the nanowire transistor device includes shallow trench isolation portions on opposite sides of respective fins of the first plurality of pins and the second plurality of pins. In some cases, at least one common plane selected along a single axis passes through at least one multilayer stack of a first type and each nanowire layer of at least one multilayer stack of a second type. In other cases, there is no selected common plane along a single axis through each nanowire of both the first type of multilayer stack and the second type of multilayer stack. In some cases, a multi-layer stack of the first type is configured for one of the PMOS or NMOS, and a multi-layer stack of the second type is configured for the other one of the PMOS or NMOS. In some cases, the first type of multilayer stack and the second type of multilayer stack each comprise a nanowire layer in which nanowires are formed and a sacrificial layer that is removed in the channel region. In some cases, the nanowire transistor device may include a gate stack and a source / drain region. Yet another embodiment of the present invention provides an integrated circuit comprising nanowire transistor devices as defined in this paragraph. Yet another embodiment provides a system including such an integrated circuit.

Yet another embodiment of the present invention provides a nanowire transistor device. In this exemplary case, the nanowire transistor device comprises a plurality of first pins on a substrate and extends from each first pin substrate. The nanowire transistor device further comprises a multi-layer stack of a first type on each first pin, and each of the multi-layer stacks of the first type comprises a channel region having one or more nanowires. The nanowire transistor device further comprises a plurality of second pins on the substrate, each second pin extending from the substrate higher than the first pin and comprising a channel region. The one or more nanowires of the first type of multilayer stack are configured to be different from the second pin. In some cases, the nanowire transistor device may include shallow trench isolation portions on opposite sides of respective fins of the first plurality of pins and the second plurality of pins. In some cases, a multi-layer stack of the first type is configured for one of the PMOS or NMOS, and a multi-layer stack of the second type is configured for the other one of the PMOS or NMOS. In some cases, the nanowire transistor device may include a gate stack and a source / drain region. Yet another embodiment of the present invention provides an integrated circuit comprising nanowire transistor devices as defined in this paragraph. Yet another embodiment provides a system including such an integrated circuit.

The foregoing description of exemplary embodiments of the present invention has been presented for purposes of illustration and description. And is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many variations and modifications are possible in light of the present disclosure. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims (28)

A method for forming a nanowire transistor structure,
Forming a plurality of fins on a substrate, each fin extending from the substrate;
Forming shallow trench isolation on opposite sides of each fin,
Masking the first set of pins of the pin to leave a first set of unmasked sacrificial fins,
Recessing the first set of non-masking sacrificial pins to provide a first set of recesses,
Forming a multi-layer stack of a first type in each recess of the first set of recesses, wherein each of the multi-layer stacks of the first type comprises a first material layer and a second material layer, Layer is in a first horizontal plane and the second material layer is formed in a channel nanowire of the transistor structure,
Masking each of the first type of multi-layer stacks to leave a second set of non-masking sacrificial pins,
Masking the second set of non-masking sacrifices to provide a second set of recesses,
Forming a second type of multi-layer stack in each recess of the second set of recesses, each of the multi-layer stacks of the second type comprising a first material layer and a second material layer, Layer is in the first horizontal plane and the second material layer is formed in the channel nanowire of the transistor structure,
Wherein the first material layer of the first type of multilayer stack is of a different thickness than the first material layer of the second type of multilayer stack
A method for forming a nanowire transistor structure.
The method according to claim 1,
Further comprising planarizing each of the first type of multi-layer stacks
A method for forming a nanowire transistor structure.
3. The method of claim 2,
Wherein planarizing each of the first type of multi-layer stacks comprises removing masking material on the first set of pins
A method for forming a nanowire transistor structure.
The method according to claim 1,
Wherein the first type of multilayer stack and the second type of multilayer stack each comprise a layer formed of nanowires and a sacrificial layer, and at least one common horizontal plane is formed of at least one multilayer stack of the first type and the second Layer through the nanowire layer of each of the at least one multi-layer stack of type &lt; RTI ID = 0.0 &gt;
A method for forming a nanowire transistor structure.
The method according to claim 1,
Wherein the first type of multilayer stack and the second type of multilayer stack each comprise a layer formed of a nanowire and a sacrificial layer, each of the nanowires of the first type of multilayer stack and the second type of multilayer stack, There is no common horizontal plane passing through the layer
A method for forming a nanowire transistor structure.
The method according to claim 1,
Wherein the first type of multilayer stack is configured for one of PMOS or NMOS and the second type of multilayer stack is configured for the other of PMOS or NMOS
A method for forming a nanowire transistor structure.
The method according to claim 1,
Further comprising planarizing each of the second type multi-layer stacks
A method for forming a nanowire transistor structure.
8. The method of claim 7,
Wherein planarizing each of the second type of multilayer stacks comprises removing masking material on the multilayer stack of the first type
A method for forming a nanowire transistor structure.
The method according to claim 1,
Recessing a shallow trench isolation portion on the substrate to expose side walls of the first type of multi-layer stack,
Forming a dummy gate structure over the multi-layer stack of the first type;
Forming an additional insulator layer on either side of the dummy gate structure over the multi-layer stack of the first type;
Planarizing the additional insulator layer with respect to an upper portion of the dummy gate structure
Lt; RTI ID = 0.0 &gt;
A method for forming a nanowire transistor structure.
10. The method of claim 9,
Masking a pin and / or multi-layer stack set formed on the substrate and used for the first type of transistor device to leave a non-masking multilayer stack set formed on the substrate and to be used for a second type of transistor device Wow,
Etching an unmasked portion of the dummy gate structure to expose a first channel region of each multilayer stack of the non-masking multilayer stack set to be used for the second type of transistor device;
Further comprising etching and removing the sacrificial inter-wire material from each first channel region to provide one or more channel nanowires for each of the second type of transistor devices
A method for forming a nanowire transistor structure.
11. The method of claim 10,
Refilling the dummy gate structure to cover the first channel region;
Planarizing the refilled dummy gate structure to remove masking material on the first pin and / or the multi-layer stack set to be used for the first type of transistor device
Lt; RTI ID = 0.0 &gt;
A method for forming a nanowire transistor structure.
11. The method of claim 10,
Etching the remaining dummy gate structure to expose a second channel region of each of the pins and / or multilayer stacks formed on the substrate and to be used for the first type of transistor device
A method for forming a nanowire transistor structure.
13. The method of claim 12,
Wherein the second channel region comprises a multilayer stack,
The method
Further comprising etching and removing the sacrificial inter-wire material from each second channel region to provide one or more channel nanowires of the first type of transistor device
A method for forming a nanowire transistor structure.
13. The method of claim 12,
Wherein the second channel region comprises a fin and is not a multilayer stack
A method for forming a nanowire transistor structure.
11. The method of claim 10,
Forming a gate stack for each of the first type transistor device and the second type transistor device,
Further comprising forming a source / drain region for each of the first type of transistor device and the second type of transistor device
A method for forming a nanowire transistor structure.
An integrated circuit formed by a method for forming a nanowire transistor structure according to claim 1.
As a nanowire transistor device,
A first plurality of pins on the substrate, each of the first plurality of pins extending from the substrate;
A multi-layer stack of a first type on each pin of the first plurality of pins, each of the multi-layer stacks of the first type comprising a first material layer and a second material layer, And wherein the second material layer comprises channel nanowires,
A second plurality of pins on the substrate, each pin of the second plurality of pins extending from the substrate;
A second type multi-layer stack on each pin of the second plurality of pins, each of the multi-layer stacks of the second type comprising a first material layer and a second material layer, Wherein the first material layer is in a horizontal plane and the second material layer comprises channel nanowires,
Wherein the first material layer of the first type of multilayer stack is of a different thickness than the first material layer of the second type of multilayer stack
Nanowire transistor devices.
18. The method of claim 17,
Further comprising a shallow trench isolation portion on opposite sides of each of the first plurality of pins and the second plurality of fins
Nanowire transistor devices.
18. The method of claim 17,
At least one common horizontal plane passing through at least one multilayer stack of the first type and each nanowire of the at least one multilayer stack of the second type
Nanowire transistor devices.
18. The method of claim 17,
Wherein a common horizontal plane through each nanowire of both the first type of multilayer stack and the second type of multilayer stack is absent
Nanowire transistor devices.
18. The method of claim 17,
Wherein the first type of multilayer stack is configured for one of PMOS or NMOS and the second type of multilayer stack is configured for the other of PMOS or NMOS
Nanowire transistor devices.
18. The method of claim 17,
Wherein the first material layer of each of the first type of multi-layer stack and the second type of multi-layer stack is a sacrificial layer removed from a channel region of the channel nanowire
Nanowire transistor devices.
18. The method of claim 17,
A gate stack,
Further comprising a source / drain region
Nanowire transistor devices.
17. An integrated circuit comprising the nanowire transistor device of claim 17.
24. A system comprising the integrated circuit of claim 24.
As a nanowire transistor device,
A plurality of first pins on the substrate, each first pin extending from the substrate;
A multi-layer stack of a first type on each first pin, each of the multi-layer stacks of the first type comprising a channel region having one or more nanowires;
A plurality of second fins on the substrate each second pin extending from the substrate higher than the first pin and comprising a channel region;
A gate stack,
Source / drain regions,
Wherein at least one of the nanowires of the first type of multilayer stack is configured to differ from the second pin in at least one of layer thickness, polarity, doping, composition, and strain configure
Nanowire transistor devices.
27. The method of claim 26,
Further comprising a shallow trench isolation on opposite sides of each first and second fin
Nanowire transistor devices.
27. The method of claim 26,
Wherein the first type of multilayer stack is configured for one of PMOS or NMOS and the second pin is configured for the other of PMOS or NMOS
Nanowire transistor devices.

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