KR101661993B1 - Apparatus and method for estimation of sram performance margin using worst case sampling - Google Patents

Abstract

The present invention relates to an SRAM performance margin evaluating apparatus and method for sampling a worst case, wherein at least one of pull-down transistors, pull-up transistors and pass-gate transistors of an SRAM cell, I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT values, a sample generator for generating samples for Monte Carlo simulation including V _TSAT values, a power exponent for power-converting the generated I _DLIN , I _DSAT , I _HIGH , I _LOW and I _OFF values into a Gaussian distribution converting section, the V _TLIN, V _TSAT value and a power-converted I _DLIN, I _DSAT, I _HIGH, I _LOW, the word line write trip voltage, holding voltage word line read out for the sample on the basis of the I _OFF value, read out the static And a write enable current based on at least one of the calculated word line write trip voltage, the word line read retention voltage, the read static noise margin, and the write enable current based on the calculated word line write trip voltage, And a margin evaluator for analyzing at least one of the read and write margins of the sample to estimate the effect of the random variable on the SRAM performance using Monte Carlo simulation by sampling the worst case, And can quickly and accurately evaluate the effect of process random variables on the performance of the actual SRAM.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an SRAM performance margin evaluation apparatus and method for sampling a worst case,

The present invention relates to an SRAM performance margin evaluation apparatus and method for sampling a worst case, and more particularly, to an SRAM performance margin evaluation apparatus and method for estimating the worst case SRAM performance in evaluating the influence of a random variable on SRAM performance using Monte Carlo simulation And a margin evaluating apparatus and method.

The impact of changes in the manufacturing process on devices has become a major concern in CMOS devices including static RAM (SRAM). In particular, random variation has a significant effect on device performance over system changes, and system changes can be controlled through fab process and layout optimization. Any change in the performance of a semiconductor device is difficult to predict but can be characterized by a statistical distribution. In particular, a random change of a semiconductor device constituting an SRAM bit cell may cause a mismatch between neighboring devices at a level that can seriously affect the SRAM operation. This is because the SRAM reading and writing margin (Read / Write Margins). In order to quantitatively predict and evaluate the effect of any change in semiconductor CMOS devices on SRAM bit cells, traditionally, read and write margins have been used in simulation programs that focus on integrated circuits, or in TCAD (Technology Computer Aided Design) (Monte-Carlo simulation) using the Mixed Mode simulations included in the simulation. However, the number of simulations required to generate data exceeding 6 sigma (σ) exceeds 500 million times, and thus excessive cost and time are required.

Korean Patent Application No. 10-2006-0062034 (published on June 6, 2006, entitled: SYSTEM USE, METHOD, AND COMPUTER-READABLE MEDIUM USING THE FIRST PRINCIPLE SIMULATION ENABLING SEMICONDUCTOR MANUFACTURING PROCESS, ).

It is an object of the present invention to provide an SRAM performance margin evaluation apparatus and method for sampling the worst case in evaluating the influence of random variables on SRAM performance using Monte Carlo simulation.

SRAM performance margins for sampling the worst case, in accordance with one aspect of the invention the evaluation device is the target point of the component sample in at least one of pull-down transistor, the pull-up transistors and the pass-gate transistors of the SRAM bit cells I _DLIN, I _DSAT, I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT values, and at least one of I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values to a Gaussian distribution, a target point and the power law and of the converted value based on at least one of a power converter for generating the component sample, the resulting device based on a sample by sample generator for generating the SRAM bit cell sample, the V _TLIN, V _TSAT value and A scale calculation unit for calculating at least one of WWTV and WRRV of the SRAM bit cell sample based on the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values; and a scale calculation unit for calculating, based on the calculated WWTV and WRRV, NM, and I _{W. In the present embodiment} ,

Preferably, the power conversion unit generates the device sample so that each value included in the device sample is selected outside the predetermined area on the probability distribution.

Preferably, the predetermined region is within a range of 3 or more from the target point of the device sample.

Preferably, the power conversion unit _expands the device samples made up of the V _TLIN and V _TSAT values and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values according to the Gaussian distribution.

Preferably, the sample generator generates the SRAM bit cell samples by selecting the element samples corresponding to the pull-down transistor, the pull-up transistor, and the pass gate transistor among the element samples generated by the power converter.

SRAM performance margin evaluation method for sampling a worst-case according to another aspect of the invention I _DLIN input unit of the target point of the element sample with respect to the pull-down transistor, at least one of pull-up transistors and the pass-gate transistors of the SRAM bit cell, I _DSAT, I _HIGH, I _LOW, I _OFF, V _TLIN, and V step of receiving the _TSAT value, a power converting part I _DLIN, I _DSAT, I _HIGH, and at least one of the I _LOW, and I _OFF value of a power conversion by the Gaussian distribution the method comprising steps of: based on at least one of the target point and values of the power law transformation on the device sample generating the component sample, the sample generation unit generating a SRAM bit cell sample on the basis of the component sample, measure calculating portion V _TLIN, V _TSAT value and a power-converted I _DLIN, I _DSAT, I _{HIGH, LOW} I, I _OFF value to the SRAM bit cells of the sample WWTV and calculating at least one of the acid addition WRRV and margin assessment based on Based on the WWTV WRRV and a step of analyzing at least one of RSNM and I _W.

According to the present invention, the worst case semiconductor CMOS device is generated and sampled by using Monte Carlo simulation to evaluate the influence of the random variable on the SRAM performance, thereby statistically increasing the 6-sigma or more Reducing the cost and time required to evaluate the impact on SRAM performance, which requires significant quantitative evaluation, greatly reducing the computational complexity of the simulation, and the effect of random performance changes in semiconductor CMOS devices on the performance of real SRAM Can be evaluated quickly and accurately.

1 is a block diagram of an SRAM performance margin evaluation apparatus for sampling a worst case according to an embodiment of the present invention.
Figure 2 is a probability graph of seven IV target points obtained from a simplified model according to one embodiment of the present invention and TCAD simulation.
Figure 3 is a drain current versus gate voltage curve of a simplified model according to a TCAD simulation and an embodiment of the present invention.
4 is a graph showing on and off currents of data extended according to a TCAD simulation and a simplified model according to an embodiment of the present invention.
5 is a graph showing a circuit diagram of an SRAM cell and a read and write scale and a probability distribution thereof according to an embodiment of the present invention.
6 is a graph showing the correlation between the _W and I and RSNM and WRRV WWTV.
Figure 7 is a graph comparing worst case and random sampling in accordance with an embodiment of the present invention.
8 is a flowchart illustrating an operation of the SRAM performance margin evaluation method for sampling the worst case according to another embodiment of the present invention.

Hereinafter, an SRAM performance margin evaluation apparatus and method for sampling the worst case according to the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of the lines and the sizes of the components shown in the drawings may be exaggerated for clarity and convenience of explanation. In addition, the terms described below are defined in consideration of the functions of the present invention, which may vary depending on the intention or custom of the user, the operator. Therefore, definitions of these terms should be made based on the contents throughout this specification.

1 is a block diagram of an SRAM performance margin evaluation apparatus for sampling a worst case according to an embodiment of the present invention.

As shown in FIG. 1, the SRAM performance margin evaluation apparatus for sampling the worst case according to an embodiment of the present invention includes a sample generation unit 100, a power conversion unit 200, a scale calculation unit 300, a margin evaluation (400), an input unit (500), and an output unit (600).

Input unit 500 is an I _DLIN, I _DSAT, I _HIGH, I _LOW, I _OFF, V _TLIN target point of the component sample (Target Point) for at least one of pull-down transistor, the pull-up transistors and the pass-gate transistors of the SRAM bit cells, And a V _TSAT value. Also, the input unit may receive the channel length and width of the CMOS device used in the pull-down transistor, the pull-up transistor, and the pass gate transistor of the SRAM cell. The devices constituting the SRAM cell can be composed of CMOS transistors. Current-versus-voltage (IV) curves of CMOS transistors include I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT may exist as target points. Where I _DLAT is the linear drain current, I _DSAT is the saturation drain current, I _HIGH is the drain current when the gate voltage is the supply voltage and the drain voltage is half of the supply voltage, I _LOW is the drain current when the gate voltage is Drain current when the drain voltage is half of the supply voltage and the drain voltage is the supply voltage, I _OFF is the off current, V _TLIN is the linear threshold voltage, and V _TSAT is the saturation threshold voltage. It is known to those skilled in the art that a simplified model of the device can be constructed by simplifying and reconfiguring the characteristic curve of the device by using these seven target points as input variables. The result of calculating the IV curve by this simplified model is TCAD It is known that this is consistent with the simulation. Therefore, a device sample in which I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT values are distributed according to a certain probability distribution from the value of the target point input through the input unit 100 is generated and the Monte Carlo simulation The performance margin of the SRAM can be evaluated.

Figure 3 is a drain current versus gate voltage curve of a simplified model according to a TCAD simulation and an embodiment of the present invention. Referring to FIG. 3, in the IV curve of the 22-nm fin-shaped field-effect transistor (FinFET) device, the data by the TCAD simulation and the data by the simplified model are consistent within a margin of 5% have. The I-V curve of each SRAM device plays a key role in solving the Kirchhoff current law equation for each storage node of the SRAM cell to calculate the read and write margins of the SRAM. If a random change occurs in an SRAM device, the I-V curve of the SRAM device may change and thus the seven target points may change, which may result in a change in the SRAM read and write margins. However, if the number of device samples is limited, an extension of the sample size may be required to evaluate the yield of the SRAM. In order to expand the device sample size, the statistical characteristics of the seven target points constituting the sample for the above-mentioned Monte Carlo simulation are used.

Figure 2 is a probability graph of seven IV target points obtained from a simplified model according to one embodiment of the present invention and TCAD simulation. Referring to FIG. 2, line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation obtained from 500 different IV curves obtained through TCAD simulation Variation, WFV) can be seen from the distribution of the seven target points resulting from the random variable. The five target points except V _TSAT and V _TLIN do not follow the Gaussian distribution. The sample size must be extended to allow reliable SRAM yield analysis without distorting the intrinsic nature of the non-Gaussian distribution. For this purpose, a power transform can be applied to expand the number of sets of the five target points. It is known to those skilled in the art that non-Gaussian distributions can be replaced by Gaussian distributions by power conversion.

The power conversion unit 200 performs a power conversion on at least one of the I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values to a Gaussian distribution, and based on at least one of the target point and the power- Thereby generating the device sample. In this case, the power conversion unit 200 can generate the device sample so that each value included in the device sample is selected outside the predetermined region on the probability distribution, and the predetermined region has a range of 3? (Standard deviation) Lt; / RTI > At this time, the power conversion unit 200 _expands the device samples consisting of V _TSAT , V _TLIN value and power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values according to the Gaussian distribution to increase the number . That is, a power conversion unit 200 increases the total number by using a Gaussian distribution is a Gaussian distribution V _TSAT and V _TLIN to follow and the non-conforming to Gaussian distribution I _DLIN, I _DSAT, I _HIGH, I _LOW, and I _OFF can increase the total number by first expanding the total number of samples using the power conversion and then inversely converting the total number of samples to the original data.

That is, referring to FIG. 2, which shows a probability graph of each IV target, the simplified model data can be expanded without distorting the original distribution using the power transformation. At this time, data representing five target points other than V _TSAT and V _TLIN contained in the element sample generated based on the target point of the element sample received by the input unit 500 or input to the power conversion unit 200 are _subjected to the power conversion To be converted into a Gaussian distribution and used to generate device sample data of an extended size according to the Gaussian distribution. Referring to FIG. 2, the extended data graph corresponds well to the original data, and the extended data range exceeds 3σ (standard deviation). That is, as described above, the predetermined region in which each value included in the element sample is selected can be set within a range of 3σ from the target point.

4 is a graph showing on and off currents of the data according to the TCAD simulation and the extended sample data according to the simplified model according to an embodiment of the present invention. FIG. 4 is a graph showing the on and off currents of the expanded data and the original data, showing that such expanded data fits the original data.

5 is a graph showing a circuit diagram of an SRAM cell and a read and write scale and a probability distribution thereof according to an embodiment of the present invention. As shown in FIG. 5A, pull-down transistors PD1 and PD2, pass-gate and PG transistors PG3 and PG4, and pull- , PU) transistors PU5 and PU6 may be included as SRAM elements. In an embodiment of the present invention, the sample generator 300 generates 10000000 sets of I-V target points of a 22 nm FinFET-based SRAM cell, and analyzes SRAM read and write margins. Figure 5 (b) compares the butterfly curves generated according to the TCAD simulation and the simplified model, Figure 5 (c) shows the TCAD simulation and the Write-N curve generated according to the simplified model -Curve). In each case, the SRAM margin metric was consistent with the TCAD simulation and the simplified model. The sample generator 400 generates SRAM bit cell samples based on the generated device samples. At this time, the sample generator 400 may generate a SRAM bit cell sample by selecting a device sample corresponding to a pull-down transistor, a pull-up transistor, and a pass gate transistor among the device samples generated by the power converter 200.

The scale calculation unit 300 calculates at least one of WWTV and WRRV of the SRAM bit cell sample based on the V _TLIN , the V _TSAT value, and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values. (WRRV), Read Static Noise Margin (RSNM), and the like, as a measure for analyzing the degree of SRAM reading and writing. And a write current (I _W ) can be used. WRRV refers to the highest word line voltage that the SRAM cell can withstand when performing a read operation, and WWTV refers to the minimum word line voltage that can reverse the cell state during a write operation. These two parameters can be measured from the Bit line current transfer curve. Of Figure 5 (d), (e) , (f) and (g) is RSNM, I _W, WRRV, normal probability graph (normal probability plot) of WWTV of 10,000 SRAM cells that are undergoing any change (random variation) / RTI > In addition, Figure 6 illustrates the correlation between the _W and I and RSNM and WRRV WWTV. According to FIG. 6, it can be seen that the conventional read and write scales RSNM and I _W are closely correlated with WRRV and WWTV obtained by directly measuring the bit line. In the same conditions, WWTV is closer to the value of 0, so it is more pessimistic in terms of margin than the traditional scale I _W. Thus, WWTV and WRRV can be used to estimate the read and write margins of the SRAM. That is, the scale calculation unit 400 can calculate WWTV and WRRV for the sample of the SRAM cell generated by the sample generation unit 300, and the margin evaluation and output unit 500 can calculate the WWTV and WRRV based on the calculated WWTV and WRRV The read and write performance of the SRAM cell can be evaluated.

As described above, the power conversion unit 200 can extend the samples based on the five power-converted target points. At this time, the characteristic values (e.g., I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF ) can be arbitrarily sampled according to the Gaussian distribution obtained through the power conversion. However, when arbitrarily sampling the device characteristic value, there is a high possibility that the values are included in a certain region on the probability distribution. In other words, a semiconductor CMOS device sample having a device characteristic value within 97% of the normal distribution (corresponding to a statistically about 2 sigma level) is more likely to be selected. This means that the same characteristics Meaning that a significant level of mismatch between values is less likely to occur. Particularly, this causes the possibility of failure or error of the SRAM reading and writing scale and the observability to be very low. Therefore, it may be necessary to generate millions of data in order to observe read and write errors (especially when the SRAM capacity is more than 500 Mbit). The power conversion unit 200 may generate a sample such that each value included in the sample is selected outside the predetermined region on the probability distribution. In this case, the predetermined region may be within 3 sigma. That is, the power converter 200 generates data points by assuming the worst case such that the generated SRAM device characteristics are located outside the 3 sigma range, and generates a sample composed of target points for analyzing the read and write margins of the SRAM Can be generated. When the method of sampling the worst case is used, the computational complexity required for the occurrence of the failure and error event of the SRAM arising from the 6 sigma significance can be remarkably reduced. At this time, if the predetermined area is less than 3 sigma from the target point, even if the SRAM device characteristic generated by the power converter 200 is selected outside the preset area, it can be selected within a range of 3 sigma, The device sample may not be a sufficiently good sample to indicate the worst case, and in this case by forming a SRAM bit cell sample from the device sample showing the worst case, the effect of reducing the computational complexity needed to evaluate the read and write margins of the SRAM is sufficient It can be difficult to achieve.

Table 1 summarizes the significance level of the SRAM scale including WWTV and WRRV that can be calculated according to the statistical sample level of the semiconductor CMOS device characteristic value indicated by?. 7 is a graph comparing the worst case sampling and the random sampling according to an embodiment of the present invention.

Significance level of devices ± 1σ ± 1.5σ ± 2σ ± 2.5σ ± 3σ SRAM Scale: WRRV > 4.5σ > 5.1σ > 5.8σ > 6.4σ > 8σ SRAM Scale: WWTV > 4.5σ > 4.8σ > 5.1σ > 6.3σ > 8σ

As shown in Table 1 and FIG. 7, the worst case WRRV and WWTV values obtained by the virtual experiment can exceed 8σ, and the WRRV and WWTV values shown in FIG. 7 indicate that the SRAM cell of 8σ level is sufficiently stable Represents the word line voltage value required for operation.

The margin evaluating unit 400 calculates at least one of RSNM and I _W based on the calculated WWTV and WRRV. Also, the margin evaluating unit 400 can analyze the read and write margins of the SRAM based on RSNM and I _W. That is, the margin evaluating unit 400 determines whether a failure or an error occurs according to the read and write margin scale of each SRAM bit cell sample according to the calculated RSNM and I _W , and reads and writes the SRAM, The margin can be evaluated. The output unit 600 outputs an analysis result of the read and write margins analyzed by the margin evaluation unit 400. [

8 is a flowchart illustrating an operation of the SRAM performance margin evaluation method for sampling the worst case according to another embodiment of the present invention.

According to the SRAM performance margin evaluation method for sampling the worst case according to another embodiment of the present invention, first, the input unit 500 determines whether or not a target point of the device sample is at least one of pull-down transistors, pull- I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT are input (S110). The power converter 200 then performs a power conversion of at least one of the I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values to a Gaussian distribution, and based on at least one of the target point and the power- And the device sample is generated (S120). At this time, the power conversion unit 200 may increase the total number of samples of the semiconductor CMOS device used in the input unit to support the proper execution of the Monte Carlo simulation using the data received from the input unit 500. [ That is, a power conversion unit 200 increases the total number by using a Gaussian distribution is a Gaussian distribution V _TSAT and V _TLIN to follow and the non-conforming to Gaussian distribution I _DLIN, I _DSAT, I _HIGH, I _LOW, and I _OFF can increase the total number by first expanding the total number of samples using the power conversion and then inversely converting the total number of samples to the original data.

Thereafter, the sample generator 100 generates an SRAM bit cell sample based on the device sample (S130). At this time, the sample generating unit 100 to the calculated V _TSAT and V _TLIN, I _DLIN, I _DSAT, I _HIGH, I _LOW, I _OFF value SRAM bit cells from the semiconductor CMOS device samples produced on the basis of the SRAM bit cell samples can be generated by selecting a combination of device samples corresponding to the included pull-down transistor, pull-up transistor and pass-gate transistor.

Subsequently, the scale calculating unit 300 calculates at least one of WWTV and WRRV of the SRAM bit cell sample based on the V _TLIN , the V _TSAT value and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values (S140) The margin evaluating unit 400 calculates at least one of RSNM and I _W based on the calculated WWTV and WRRV (S150). Then, the margin evaluating unit 400 determines whether a failure or an error occurs according to the read and write margin scale of each SRAM bit cell sample according to the calculated RSNM and I _W (S160). Then, the output unit 600 outputs the evaluation result of the SRAM read and write margin and ends the process. At this time, it is needless to say that such a scale calculation and analysis can be performed not only on one data point but also on a large number of data points as described above, thereby observing read and write errors of SRAM cells.

As described above, according to the present invention, by sampling the worst case in evaluating the influence of the random variable on the SRAM performance by using the Monte Carlo simulation, the calculation complexity of the simulation can be greatly reduced, Can be quickly and accurately evaluated. It is possible to quickly and accurately evaluate the influence of any change in the semiconductor CMOS device on the performance of the actual SRAM.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. I will understand. Accordingly, the technical scope of the present invention should be defined by the following claims.

100: sample generation unit 200: power conversion unit
300: scale calculation unit 400: margin evaluation unit
500: input unit 600: output unit

Claims (10)

An input section for inputting I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT , which are target points of a device sample, to at least one of a pull-down transistor, a pull-up transistor and a pass gate transistor of an SRAM bit cell;
A non-Gaussian distribution by power conversion and a V _TLIN for at least one of the I _DLIN , I _DSAT , I _HIGH , I _LOW and I _OFF values, and a device constituted by a simplified model of a device with a Gaussian distribution with respect to V _TSAT A power conversion unit for generating a device sample in which the input points I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT are present through the model of the input _terminal ;
A sample generator for generating an SRAM bit cell sample based on the generated device sample;
A scale calculating unit for calculating at least one of WWTV and WRRV of the SRAM bit cell sample based on the V _TLIN , the V _TSAT value and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values; And
SRAM performance margin evaluation device comprising margin evaluated for calculating at least one of RSNM and I _W on the basis of the calculated WWTV and WRRV parts.
The method according to claim 1,
Wherein the power conversion unit generates the device sample so that each value included in the device sample is selected outside a predetermined region on a probability distribution.
3. The method of claim 2,
Wherein the predetermined area is within a range of 3? Or more from a target point of the device sample.
The method according to claim 1,
_Wherein the power conversion unit expands the number of element samples made up of the V _TLIN and V _TSAT values and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values according to a Gaussian distribution to increase the number. Performance margin evaluation device.
The method according to claim 1,
Wherein the sample generator selects the element samples corresponding to the pull-down transistor, the pull-up transistor and the pass gate transistor among the element samples generated by the power conversion unit to generate the SRAM bit cell samples.
I _DSIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT are input to at least one of the pull-up transistor, the pull-up transistor and the pass gate transistor of the SRAM bit cell of the input unit step;
A simplified model of the device as the Gaussian distribution for the conversion unit powers the _{I DLIN, I DSAT, I HIGH} , I LOW, and non-Gaussian distribution and the V _TLIN, and V _TSAT by a power conversion for at least one of I _OFF value Generating a device sample in which the input target points I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF , V _TLIN , and V _TSAT are present through a model of the constructed and configured device ;
The sample generator generating an SRAM bit cell sample based on the device sample;
Calculating at least one of a WWTV and a WRRV of the SRAM bit cell sample based on the scale output unit V _TLIN , the V _TSAT value and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , I _OFF values; And
And the margin evaluating unit calculates at least one of RSNM and I _W based on the calculated WWTV and WRRV.
The method according to claim 6,
In the step of generating the device sample,
Wherein the power conversion unit generates the device sample so that each value included in the device sample is selected outside a predetermined region on a probability distribution.
8. The method of claim 7,
Wherein the predetermined area is within a range of 3? Or more from a target point of the device sample.
The method according to claim 6,
In the step of generating the device sample,
_Wherein the power conversion unit expands the number of element samples made up of the V _TLIN and V _TSAT values and the power-converted I _DLIN , I _DSAT , I _HIGH , I _LOW , and I _OFF values according to a Gaussian distribution to increase the number. Performance margin evaluation method.

The method according to claim 6,
In the step of generating the SRAM bit cell samples,
Wherein the sample generator selects the element samples corresponding to the pull-down transistor, the pull-up transistor, and the pass gate transistor among the element samples generated by the power conversion unit to generate the SRAM bit cell samples.

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