KR101655008B1 - Apparatus and method for real-time multi-chip flash storage - Google Patents

Abstract

A real-time multi-chip flash storage device and method thereof are disclosed.
The real-time multi-chip flash storage consists of a flash translation layer and flash control hardware. The flash translation layer has a flash control scheduler. The flash control scheduler schedules the real service time for each input / A virtual time which is a request expected processing time for each input / output stream is calculated using an arbitrary nominal service time, and scheduling is performed by using the calculated virtual time. If the actual service time is later recognized, The virtual time is corrected using the service time, and the scheduling is performed using the corrected virtual time.

Description

[0001] APPARATUS AND METHOD FOR REAL-TIME MULTI-CHIP FLASH STORAGE [0002]

The present invention relates to a real-time multi-chip flash storage device and a method thereof, and more particularly, to a real-time multi-chip flash storage device and a method thereof for performing a process equity scheduling or a proportional equity scheduling.

Due to the activation of smart phones and SNS, the speed of content production explosively increases and interest and research on mass storage devices for storing data is increasing.

Due to advances in technology for such mass storage devices, flash storage devices are gradually replacing the hard disk space that has been used for many years as a computer-aided storage device.

Unlike the hard disk, the flash storage device has a characteristic that the execution speed of each of the read, write, and erase operations is different, so that it can not cope with the requested data command from the host. In order to secure these disadvantages, researches on flash conversion layer that can flexibly cope with the characteristics of the flash storage device are being actively conducted on the instructions for the read, write, and erase operations.

However, the conventional flash conversion layer has been limited to a single chip flash storage device or a case where a multi chip is modeled as a logical single chip composed of a super page. In addition, this research has a disadvantage in that it is difficult to predict the response time of the storage device of the application program when the invalid page collection operation is performed irregularly.

In addition, since the conventional flash storage device is developed for a single resource, it can not allocate another request until a service is terminated after a single input / output request is allocated to the corresponding resource. Thus, multiple resources There is a problem that only one resource is utilized and the remaining resources can not be utilized.

Therefore, we need a real - time multi - chip flash storage device that can perform the process equity scheduling that can be applied to multiple resources and predict the response time of the storage device of the application program.

Korean Patent No. 1021364 Korea Patent Publication No. 2014-0111323

One aspect of the present invention is to maximize the parallelism of the multi-chip flash, which is a multi-resource, and to calculate the virtual time, which is the expected processing time for each input / output stream, by using an arbitrary nominal service time so as to predict the response time of the storage device And a real-time multi-chip flash storage device for performing scheduling according to the calculated virtual time, and a method thereof.

According to an aspect of the present invention, there is provided a real-time multi-chip flash storage device that extracts an input / output request from a stream queue in which an input / output request arriving to a plurality of input / output streams is inserted and converts the input / output request into a flash operation, Output stream to a plurality of input / output streams, calculating a virtual time for input / output streams for each of the plurality of input / output streams, and calculating a minimum virtual time among the plurality of input / output streams so that scheduling can be performed according to the calculated virtual time A flash conversion layer for extracting a first flash operation from an operation queue of the input / output stream and inserting the first flash operation into a start queue of a flash chip allocated to the flash operation; and a plurality of flash chips, Run according to the set controller algorithm And a flash controller for inserting an operation termination event into the expiration queue of the flash chip when the execution of the flash operation inserted into the initiation queue is terminated.

Wherein the flash conversion layer calculates a virtual time for the plurality of input / output streams by applying an arbitrary nominal service time for the plurality of input / output streams to a predetermined calculation rule, compares the calculated virtual time, And a flash operation scheduler for extracting the first flash operation from the operation queue of the input / output stream having the minimum virtual time and inserting the extracted flash operation into the start queue.

The flash operation scheduler recognizes the actual service time for the input / output request of the input / output stream through the operation end event when the operation end event is inserted into the expiration queue of the flash chip by the flash control hardware, The virtual time for the input / output stream can be corrected by applying the actual service time to the input / output stream.

The flash operation scheduler can perform scheduling for a plurality of input / output streams including virtual time-corrected input / output streams when the virtual time for the input / output stream is corrected using the actual service time.

Wherein the flash operation scheduler detects an input / output stream having a minimum virtual time by comparing virtual time with respect to a plurality of input / output streams including the virtual time-corrected input / output stream, The first flash operation can be extracted and the scheduling can be performed.

Wherein when a new input / output request is input to the input / output stream while an operation is being performed in a flash chip to which a flash operation for an input / output stream having the minimum virtual time is allocated, the flash operation scheduler A flash operation for an input / output stream having the minimum virtual time is executed by inserting a flash operation for the new input / output request into a start queue of a flash chip other than the flash chip to which the flash operation is allocated and a flash operation .

A method for real-time multi-chip flash storage according to an embodiment of the present invention includes extracting an input / output request from a stream queue in which an input / output request arriving at a plurality of input / output streams is inserted, converting the input / output request into a flash operation, Output stream; calculating a virtual time for an input / output stream for each of the plurality of input / output streams; comparing the calculated virtual time so that scheduling can be performed according to the calculated virtual time, Output stream having a minimum virtual time, extracting a first flash operation from an operation queue of an input / output stream having the minimum virtual time, inserting the first flash operation into a start queue of a flash chip allocated to the flash operation, Flash inserted into the start-up queue of the flash chip When running along the mountain to a preset control algorithm and executing the flash operation inserted in the start queue ends it can be inserted into the operational end of the expiration event queue of the flash chip.

If an operation termination event is inserted into the expiration queue of the flash chip, the actual service time for the input / output request of the input / output stream is recognized through the operation termination event, and the actual service time is applied to the predetermined operation rule, It is possible to correct the virtual time.

Output stream having a minimum virtual time by comparing a virtual time with respect to a plurality of input / output streams including an input / output stream whose virtual time is corrected, when the virtual time for the input / output stream is corrected using the actual service time, The first flash operation may be extracted from the operation queue of the input / output stream having the minimum virtual time to perform the scheduling.

When a new input / output request is input to the input / output stream while the operation is being performed in the flash chip to which the flash operation for the input / output stream having the minimum virtual time is allocated, the flash operation for the flash operation for the input / A flash operation for the new input / output request may be inserted into the start queue of the chip and another flash chip to execute a flash operation for the input / output stream having the minimum virtual time and to execute the flash operation for the new input / output request.

According to an aspect of the present invention, a virtual time, which is an expected processing time for an input / output stream, is calculated using an arbitrary nominal service time in a situation where an actual service time for an input / output request arriving at an input / And performs scheduling according to the calculated virtual time, thereby performing the process equity scheduling according to the process time, and the response time of the storage device can be predicted.

Also, by performing the process equity scheduling using the nominal service time, the flash operation scheduler can be implemented separately from the flash control hardware, thereby simplifying the structure of the flash control hardware.

In addition, by performing the process equity scheduling using the nominal service time, it is possible to maximize the parallelism of multi-chip flash.

1 is a block diagram of a real-time multi-chip flash storage device according to an embodiment of the present invention.
2 is a diagram showing an example in which a flash operation for an input / output stream arrives in a flash chip.
FIG. 3 is a diagram showing how flash operations requested in each input / output stream shown in FIG. 2 are actually performed in each flash chip.
FIGS. 4A and 4B are views showing accumulated virtual time calculated and corrected for specific input / output streams A and B. FIG.
5A and 5B are flowcharts illustrating a real-time multi-chip flash storage method according to an embodiment of the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a block diagram of a real-time multi-chip flash storage device according to an embodiment of the present invention.

The real-time multi-chip flash storage device according to an exemplary embodiment of the present invention can perform process support scheduling for a multi-chip flash, which is a parallel multiple resource, by applying the concept of nominal service time in a situation where actual service time is not known in advance And a real-time multi-chip flash storage device according to an embodiment of the present invention may include a flash conversion layer 100 and a flash control hardware 200.

The flash translation layer 100 may function to emulate a flash memory as a hard disk between a host OS and a flash memory. The flash translation layer 100 masks the unique characteristics of the flash memory to the host operating system and maps the logical address transferred from the file system to the physical address of the flash memory so as to perform the same input / ) Can be performed.

The flash conversion layer 100 according to an embodiment of the present invention can extract an input / output request from a stream queue in which an input / output request arriving at a plurality of input / output streams is inserted by a host OS . The flash conversion layer 100 may insert the extracted input / output request into an operation queue of the corresponding input / output stream. At this time, the operation queue may be provided for each of a plurality of input / output streams. The flash translation layer 100 according to an exemplary embodiment of the present invention may include a flash operation scheduler 110 that arranges a sequence of processing a plurality of input / output requests therein. The real-time multi-chip flash storage device according to an exemplary embodiment of the present invention realizes a flash operation scheduler 110 in software form within the flash conversion layer 100 so that the original flash operation scheduler 110 function can be implemented in a flash control There is an advantage that the flash operation scheduler 110 can be separated from the hardware so that the structure of the flash control hardware 200 can be simplified.

The flash operation scheduler 110 applies an arbitrary nominal service time to a plurality of input and output streams using Equation (1) to calculate a virtual start time and a virtual start time for each input / A virtual finish time can be calculated. In this case, the nominal service time is the time required to process the input / output stream and the response time of the real-time multi-chip flash storage device in a situation where the actual service time for the input / And may be defined as a constant value in the manufacture of a real-time multi-chip flash storage device or an average value of actual service times obtained by executing the operation previously.

은 입출력 스트림 i의 k번째 요청의 가상 시작 시간(virtual start time)을 의미할 수 있으며,

은 입출력 스트림 i의 k번째 요청의 가상 종료 시간(virtual finish time)을 의미할 수 있으며,

은 입출력 스트림 i의 k번째 요청의 물리적인 도착 시간에 관찰된 시스템 가상 시간(system virtual time)으로, 해당 시간에서 적어도 하나의 입출력 요청을 스트림 큐(stream queue)에 가지고 있거나 서비스 받고 있는 스트림 큐(stream queue)들의 가상 시간들 중에서 최소값으로 정의될 수 있다.

은 모든 플래시 칩(220)을 대상으로 한 입출력 스트림 i의 l번째부터 k번째까지의 연산의 명목 서비스 시간(nominal service time)의 합을 의미할 수 있으며,

는 입출력 스트림 i에 대한 가중치를 의미할 수 있다.At this time,

May be the virtual start time of the kth request of the input / output stream i,

May be the virtual finish time of the kth request of the input / output stream i,

Is a system virtual time observed at the physical arrival time of the kth request of the input / output stream i, and has at least one input / output request at the corresponding time in a stream queue or a stream queue stream queues may be defined as the minimum value among the virtual times.

May denote the sum of the nominal service times of the l-th to k-th operations of the input and output stream i for all the flash chips 220,

May be a weight for the input / output stream i.

In this case, the calculated virtual end time may mean the total time taken to process the input / output request of the input / output stream, so the flash operation scheduler 110 can define the calculated virtual end time as the virtual time of the stream.

The flash operation scheduler 110 can detect an input / output stream having a minimum virtual time among a plurality of input / output streams by comparing virtual time calculated for all input / output streams. The flash operation scheduler 110 extracts the first operation from the operation queue of the input / output stream having the minimum virtual time so that the operation can be executed according to the order in which the operation is inserted into the operation queue of the input / output stream having the minimum virtual time, May be inserted into an initiation queue (IQ) of the allocated flash chip 220. In this case, extracting the operation inserted in the operation queue of the input / output stream having the minimum virtual time among the plurality of input / output streams means that the processing time required for processing the operation is short because the virtual time is short, This is to shorten the average response time of the multi-chip flash storage device by processing from this short input / output request. 1, an initiation queue (IQ) is provided for each of a plurality of flash chips 220 provided in the flash control hardware 200. When an operation is inserted from the flash translation layer 100 The operation can be loaded according to the inserted order.

The flash operation scheduler 110 according to an embodiment of the present invention executes an operation inserted in an initiation queue IQ by the flash control hardware 200 and then performs an operation end in a completion queue When the event is inserted, the virtual time for the input / output stream can be corrected through the inserted operation end event.

Specifically, the flash operation scheduler 110 executes an operation inserted into an initiation queue IQ by the flash controller 210 provided in the flash control hardware 200, and then executes the operation executed by the flash controller 210 When an operation termination event for an operation is inserted into an completion queue (CQ) paired with the initiation queue (IQ), execution of the operation inserted in the initiation queue (IQ) , And can detect the actual service time for the operation inserted in the initiation queue (IQ). The detection of the actual service time for the operation inserted into the initiation queue IQ is performed by inserting an operation into the initiation queue IQ and then terminating the operation in the completion queue CQ The actual service time for the operation inserted in the initiation queue (IQ) can be detected by detecting the time until the event is inserted. When the actual service time for the operation inserted into the initiation queue IQ is detected, the flash operation scheduler 110 applies the detected actual service time to Equation (2) to correct the virtual time for the input / output stream can do.

는 입출력 스트림 i의 k번째 요청의 보정된 가상 종료 시간(virtual finish time), 즉 보정된 가상 시간을 의미할 수 있으며,

는 보정되기 전 입출력 스트림 i의 k번째 요청의 가상 시작 시간(virtual start time), 즉 보정되기 전 가상 시간을 의미할 수 있으며,

는 모든 칩에서 입출력 스트림 i의 l번째부터 k번째까지 요청의 연산 종료 사건을 통해 검출된 실제 서비스 시간(actual service time)의 합을 의미할 수 있으며,

역시 모든 칩에서 입출력 스트림 i의 l번째부터 k번째까지의 연산의 명목 서비스 시간(nominal service time)의 합을 의미할 수 있으며,

는 입출력 스트림 i에 대한 가중치를 의미할 수 있다.At this time,

May mean a corrected virtual finish time of the k-th request of the input / output stream i, i.e., a corrected virtual time,

May be a virtual start time of the kth request of the input / output stream i before being corrected, i.e., a virtual time before being corrected,

May refer to the sum of actual service times detected from the l-th to k-th requests of the input / output stream i on all of the chips through an operation termination event of the request,

May also mean the sum of the nominal service times of the l-th to k-th operations of the input and output stream i on all chips,

May be a weight for the input / output stream i.

When the virtual time for the input / output stream is corrected, the flash operation scheduler 110 updates the virtual time for the input / output stream to a virtual time corrected, and performs scheduling to rearrange the processing order for the flash operation of the input / output stream have. At this time, the scheduling is re-executed by using the corrected virtual time. When the virtual time corrected by the flash operation scheduler 110 is updated in the input / output stream, the virtual time is updated using the updated input / output stream and the nominal service time Output stream having the minimum virtual time by comparing the virtual time between the input and output streams calculated in the time, extracts the first operation from the operation queue of the detected input / output stream, and outputs the start queue of the flash chip 220 the scheduling can be re-executed by inserting it into an initiation queue (IQ).

The flash operation scheduler 110 according to an exemplary embodiment of the present invention can perform scheduling using multi-chip flash, which is a multi-resource.

Specifically, the flash operation scheduler 110 calculates a virtual time for each input / output stream by applying a nominal service time to a plurality of input / output streams, and compares the calculated virtual time to obtain a minimum virtual time And extracts the flash operation from the input / output stream detected so that the flash operation for the detected input / output stream can be executed, and outputs the extracted flash operation to the initiation queue (IQ) of the flash chip 220 to which the flash operation is allocated Can be inserted. At this time, when a new input / output request is input to the input / output stream while the flash operation is performed in the flash chip 220 to which the flash operation is allocated, another flash chip 220 provided in the flash control hardware 200 is utilized . When a new input / output request is input to the input / output stream during execution of the flash operation on the flash chip 220 to which the flash operation is allocated, the flash operation scheduler 110 performs a flash operation on the flash chip 220 A new flash operation can be inserted into the initiation queue IQ of the flash chip 220. [ Accordingly, when the flash operation scheduler 110 receives a new flash operation while performing a flash operation on a specific input / output stream, the flash operation scheduler 110 allocates multiple resources to another flash chip 220 provided in the flash control hardware 200 Can be utilized.

The flash control hardware 200 may be composed of one shared channel or a dedicated channel for each chip connecting the flash controller 210 and the plurality of NAND flash chips 220 with each chip.

The flash controller 210 determines whether a flash operation is inserted into an initiation queue IQ during a read, write, or erase operation when an operation is inserted into the initiation queue IQ by the flash operation scheduler 110 Can be processed.

Specifically, when the operation is inserted into the initiation queue (IQ) by the flash operation scheduler 110, the flash controller 210 sets an operation corresponding to the operation inserted in the initiation queue (IQ) Lt; / RTI > algorithm. When the execution of the operation is completed according to the controller algorithm set in advance in the flash controller 210, an operation termination event can be inserted into the completion queue (CQ). At this time, the completion queue (CQ) is provided for each of the plurality of flash chips 220 provided in the flash control hardware 200, and may be provided in pairs with an initiation queue (IQ).

2 is a diagram showing a state in which a flash operation for specific input / output streams A and B arrives in two flash chips Chip 0 and Chip 1.

Referring to FIG. 2, when an operation for stream A arrives at 0us, 120us in chip 0, an operation for stream B arrives at 20us, an operation for stream A is 10us, an operation for stream B This arrives at 200us. In FIG. 2, arrows indicate the arrival time of each input / output stream, and the numbers in parentheses may indicate arrival time.

FIG. 3 is a diagram showing how flash operations requested in each input / output stream shown in FIG. 2 are actually performed in each flash chip.

As shown in FIG. 2, when an operation for stream A arrives at 0us and 120us with chip 0, an operation for stream B reaches 20us, an operation for stream A is 10us and an operation for stream B is performed at chip 1 In case of stream A with arrival time of 0us on chip 0, actual service time is 100us when actual operation is performed on chip 0, and actual operation on chip 0 when stream B with arrival time 20us is on chip 0 The actual service time is 80us. In case of stream A with arrival time 120us on chip 0, the actual service time is 90us when the actual operation is performed on chip 0, and the stream A having the arrival time of 10us on chip 1 The actual service time is 110us when the actual operation is performed on chip 1, and the actual service time is 90us when the actual operation is performed on chip 1 for stream B with arrival time of 200us on chip 1 .

FIGS. 4A and 4B are views showing accumulated virtual time calculated and corrected for specific input / output streams A and B. FIG.

)는 1이라 가정하였을 때, 도착 시간이 0us인 경우 스트림 A에 대한 플래시 연산이 chip 0에 삽입될 수 있다. 도착 시간이 0us인 경우 실제 서비스 시간을 알 수 없으므로 명목 서비스 시간을 [수학식 1]에 적용하여 가상 시간을 산출할 수 있다. 이때, 스트림 A에 대한 가상 시간은 100us로 산출되며, 스트림 A는 산출한 가상 시간만큼 가상 시간이 누적됨을 보이며, 상태는 BUSY 상태가 되고, 스트림 B의 상태는 아직 IDLE 상태임을 보인다.4A, a real-time multi-chip flash storage device is composed of two flash chips (chip 0, chip 1), considering only a page read operation, a nominal service time is 100 us, and an actual service time is 80 to 120 us And the weights for the specific input / output streams A and B

) Is 1, the flash operation for stream A can be inserted into chip 0 when the arrival time is 0us. Since the actual service time can not be known when the arrival time is 0us, the virtual time can be calculated by applying the nominal service time to Equation (1). At this time, the virtual time for the stream A is calculated as 100us, and the stream A shows that the virtual time is accumulated by the calculated virtual time, the state is the BUSY state, and the state of the stream B is still the IDLE state.

If the arrival time is 10us, since the operation is being executed in chip 0 for the operation with arrival time 0us, the flash operation for the arrival time of 10us can be inserted into the initiation queue (IQ) of chip 1. [ Since the actual service time is not known when the arrival time is 10us, the virtual time can be calculated by applying the nominal service time to Equation (1). At this time, virtual time for stream A is calculated as 100us, and stream A shows accumulation of virtual time in chip 0 and chip 1. At this time, the state of the stream A is in the BUSY state, and the state of the stream B is still in the IDLE state.

If the arrival time is 20us, an operation on stream B may be inserted into the initiation queue (IQ) of chip 0. Since the actual service time is not known when the arrival time is 20us, the virtual time can be calculated by applying the nominal service time to Equation (1). At this time, the state of stream B is changed from IDLE to BUSY. Since the system virtual time observed at arrival time is the virtual time of stream A, the virtual start time of stream B is accumulated from the virtual time value of stream A. see. Since the virtual time for stream B is calculated as 100us, the accumulated virtual time for stream B when the arrival time is 20us is 300us.

When the arrival time is 100us, the flash operation whose arrival time is 0us in the stream A is completed. Accordingly, the virtual time value calculated using the nominal service time when the arrival time is 0us can be corrected using the actual service time value. Referring to FIG. 3, since the actual service time when the arrival time is 0us is detected as 100us, the virtual time for the stream A when the arrival time is 100us can be corrected, and the corrected virtual time 100us (= 200 + (100-100)). Thus, the fluctuation of the virtual time value of the stream A does not occur when the arrival time is 100 us.

When the arrival time is 120us, the flash operation with the arrival time of 10us in stream A is completed. Accordingly, the virtual time value calculated using the nominal service time when the arrival time is 10us can be corrected using the actual service time value. Referring to FIG. 3, since the actual service time when the arrival time is 10us is detected as 110us, the virtual time for stream A when the arrival time is 120us can be corrected, The virtual time for A can be corrected from 200us to 210us (= 200 + (110-100)).

Referring to FIG. 4B, since the flash operation is inserted into the initiation queue (IQ) of the chip 0 in the stream A at the same time (arrival time is 120us), a nominal service The virtual time calculated using the time, 100us, can be accumulated. At this time, the state of the stream A becomes the BUSY state, and the state of the stream B is the BUSY state.

When the arrival time is 180us, the execution of the flash association in which the arrival time is 20us in the stream B is completed. Accordingly, the virtual time value calculated using the nominal service time when the arrival time is 20us can be corrected using the actual service time value. Referring to FIG. 3, since the actual service time when the arrival time is 20us is detected as 80us, the virtual time for the stream B when the arrival time is 180us can be corrected, The virtual time for B can be corrected from 300us to 280us (= 300 + (80-100)). At this time, the state of the stream A is in the BUSY state, and the state of the stream B is in the IDLE state.

If the arrival time is 200us, a flash operation for stream B may be inserted into the initiation queue (IQ) of chip 1. Since the actual service time can not be known when the arrival time is 200us, the nominal service time can be applied to Equation (1) to calculate the virtual time. At this time, since the system virtual time observed at the arrival time is the virtual time of the stream A, the virtual start time of the stream B is accumulated from the virtual time value of the stream A. Since the virtual time for stream B is calculated as 100us, the cumulative virtual time for stream B when the arrival time is 200us is 410us.

When the arrival time is 270us, the flash operation whose arrival time is 120us in the stream A is completed. Accordingly, the virtual time value calculated using the nominal service time when the arrival time is 120us can be corrected using the actual service time value. Since the actual service time when the arrival time is 120us is detected as 90us, the virtual time for the stream A when the arrival time is 270us can be corrected, and the virtual time for stream A can be corrected by using the actual service time Can be corrected from 310us to 300us (= 310 + (90-100)). At this time, since stream A has no flash operation to be performed, the state of stream A is changed from BUSY to IDLE state, and the state of stream B is BUSY state.

When the arrival time is 290 us, the execution of the flash operation whose arrival time is 200us in the stream B is completed. Accordingly, the virtual time value calculated using the nominal service time when the arrival time is 200us can be corrected using the actual service time value. At this time, since the actual service time when the arrival time is 200us is detected as 90us, the virtual time for stream B when the arrival time is 290us can be corrected, and the virtual time for stream B Can be corrected from 410us to 400us (= 410 + (90-100)). At this time, streams A and B are in the IDLE state because there is no flash operation being performed.

Hereinafter, a multi-chip flash storage method according to an embodiment of the present invention will be described with reference to FIGS. 5A and 5B.

Referring to FIG. 5A, an input / output request is extracted 310 from a stream queue having an input / output request arriving to a plurality of input / output streams, and the extracted input / output request is converted into a flash operation 315.

At this time, the stream queue is created in the real-time multi-chip flash storage device by the host operating system, and the input / output requests arriving at a plurality of input / output streams can be loaded in the order of arrival.

The converted flash operation is inserted into the operation queue of the corresponding input / output stream among the plurality of input / output streams (320), and the virtual time for each input / output stream into which the converted flash operation is inserted is calculated (325).

At this time, the virtual time for each input / output stream can be calculated using Equation (1), and the virtual end time can be a virtual time for each input / output stream.

(330) an input / output stream having a minimum virtual time among a plurality of input / output streams by comparing the calculated virtual time, and extracts the first operation among the operations inserted in the operation queue of the input / output stream having the minimum virtual time (335) .

At this time, the detection of the input / output stream having the minimum virtual time among the plurality of input / output streams means that the virtual time is short means that the processing time required for processing the operation is short. Therefore, This is to shorten the average response time of the chip flash storage device. The first operation among the operations inserted in the operation queue of the input / output stream having the minimum virtual time is extracted in order to process the operation according to the order inserted in the operation queue of the input / output stream.

The extracted operation is inserted into the assigned initiation queue IQ 340 and the operation inserted into the initiation queue IQ through the flash controller 210 is executed according to a predetermined controller algorithm (345).

At this time, if the operation inserted into the initiation queue IQ is terminated (350), the same operation as the initiation queue (IQ) pairing with the initiation queue (IQ) (355) inserts an operation termination event into the connection completion queue (CQ), and if the operation inserted into the initiation queue (IQ) is not terminated (350), the flow returns to step 345. [

Referring to FIG. 5B, an actual service time of an input / output stream in which an operation end event is inserted is detected (410).

At this time, the actual service time of the input / output stream inserted with the operation end event is detected when the operation end event is inserted into the completion queue (CQ) since the operation is inserted into the initiation queue (IQ) It is possible to detect the actual service time for the operation inserted into the initiation queue IQ.

The detected actual service time is applied to Equation (2) to perform virtual time correction (420), and the scheduling for the input and output streams is performed using the virtual time corrected so that the process share scheduling can be performed reflecting the corrected virtual time (430).

Such a technique for performing process assisted scheduling for multi-chip, which is a multi-resource, may be implemented in an application or may be implemented in the form of program instructions that can be executed through various computer components and recorded in a computer-readable recording medium. The computer-readable recording medium may include program commands, data files, data structures, and the like, alone or in combination.

The program instructions recorded on the computer-readable recording medium may be ones that are specially designed and configured for the present invention and are known and available to those skilled in the art of computer software.

Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tape, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.

Examples of program instructions include machine language code such as those generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules for performing the processing according to the present invention, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

100: Flash conversion layer
110: flash operation scheduler
200: Flash control hardware
210: Flash controller

Claims (10)

Output request from a stream queue in which an input / output request arriving at a plurality of input / output streams is inserted, converts the input / output request into a flash operation, inserts the flash operation into an operation queue provided for each of the plurality of input / output streams, Output stream, extracts the first flash operation from the operation queue of the input / output stream having the smallest virtual time among the plurality of input / output streams so as to perform the scheduling according to the calculated virtual time, A flash translation layer for inserting an operation into the start queue of the allocated flash chip; And
And a controller for executing a flash operation inserted in a start queue of the flash chip in accordance with a predetermined controller algorithm, and when an execution of a flash operation inserted in the start queue is terminated, And a flash controller for inserting the flash controller into the flash memory,
Wherein the flash conversion layer comprises:
Output stream by applying an arbitrary nominal service time for the plurality of input / output streams to a predetermined arithmetic rule to calculate a virtual time for the plurality of input / output streams, and comparing the calculated virtual time to detect an input / And a flash operation scheduler for extracting a first flash operation from an operation queue of the input / output stream having the minimum virtual time and inserting the first flash operation into the start queue,
The flash operation scheduler includes:
When a new input / output request is input to the input / output stream while the operation is being performed in the flash chip to which the flash operation for the input / output stream having the minimum virtual time is allocated, the flash operation for the flash operation for the input / A flash operation for the new input / output request is inserted into a start queue of a chip and another flash chip to execute a flash operation for an input / output stream having the minimum virtual time, and a flash operation for the new input / output request is executed. A real-time multi-chip flash storage device. delete The method according to claim 1,
The flash operation scheduler includes:
When the operation end event is inserted into the expiration queue of the flash chip by the flash control hardware, the actual service time for the input / output request of the input / output stream is recognized through the operation end event, and the actual service time To the virtual time of the input / output stream to correct the virtual time for the input / output stream. The method of claim 3,
The flash operation scheduler includes:
Wherein the scheduling is performed for a plurality of input / output streams including virtual time-corrected input / output streams when the virtual time for the input / output stream is corrected using the actual service time. 5. The method of claim 4,
The flash operation scheduler includes:
Output stream having a minimum virtual time by comparing virtual time with a plurality of input / output streams including the virtual time-corrected input / output stream, and detecting a first flash operation in the operation queue of the input / Chip multi-chip flash storage device. delete Output request from a stream queue in which an input / output request arriving at a plurality of input / output streams is inserted, converts the input / output request into a flash operation, inserts the flash operation into an operation queue provided for each of the plurality of input / output streams, Output streams having a minimum virtual time among the plurality of input / output streams by comparing the calculated virtual time so as to be able to perform scheduling according to the calculated virtual time, Extracting a first flash operation from an operation queue of an input / output stream having a minimum virtual time, inserting the flash operation into a start queue of a flash chip allocated to the flash operation,
Wherein the flash memory controller executes the flash operation inserted in the start queue of the flash chip according to a predetermined controller algorithm and inserts an operation end event into the expiration queue of the flash chip when the execution of the flash operation inserted into the start queue is completed,
When a new input / output request is input to the input / output stream while the operation is being performed in the flash chip to which the flash operation for the input / output stream having the minimum virtual time is allocated, the flash operation for the flash operation for the input / A flash operation for the new input / output request is inserted into a start queue of a chip and another flash chip to execute a flash operation for an input / output stream having the minimum virtual time, and a flash operation for the new input / output request is executed. Time multi-chip flash storage method. 8. The method of claim 7,
If an operation termination event is inserted into the expiration queue of the flash chip, the actual service time for the input / output request of the input / output stream is recognized through the operation termination event, and the actual service time is applied to the predetermined operation rule, Lt; RTI ID = 0.0 > multi-chip < / RTI > flash storage method. 9. The method of claim 8,
Output stream having a minimum virtual time by comparing a virtual time with respect to a plurality of input / output streams including an input / output stream whose virtual time is corrected, when the virtual time for the input / output stream is corrected using the actual service time, And extracting a first flash operation from the operation queue of the input / output stream having the minimum virtual time to perform scheduling. delete

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