KR101653468B1 - Data inversion coding apparatus and method - Google Patents

Abstract

A data reversal coding apparatus and method are disclosed in which the number of bits that are substantially transited in consideration of the DBI flag signal is equal to or less than half of the total number of bits of the current data. Wherein the data reversal coding apparatus comprises a data reversal determination unit for determining whether to reverse the current data in consideration of the bit transition of the current data and the logic of the previous data reversal information signal from the previous data, And outputs the result as output data. Here, the previous data inversion information signal has information on whether the previous data is inverted.

Description

[0001] DATA INVERSION CODING APPARATUS AND METHOD [0002]

The present invention relates to a data reversal coding apparatus and method.

The DBI coding indicates a method of comparing the current data with the previous data and inverting the current data when bits exceeding half of all the bits of the current data are shifted from the bits of the previous data.

However, conventional DBI coding reverses or non-reverses data without considering the logical value of the DBI flag signal. Therefore, if half of the bits of the current data are shifted from the bits of the previous data, if the logic value of the current DBI flag signal is different from the logic value of the previous DBI flag signal, the number of transitions actually occurring is (N + 1) And 2N denotes the total number of bits of the current data. As a result, there is a problem that the number of data pins with low logical values exceeds half.

Korean Registered Patent No. 902051 (registered on June 3, 2009)

The present invention provides a data reversal coding apparatus and method for considering the DBI flag signal so that the number of substantially transited bits is less than half of the total number of bits of the current data.

In order to achieve the above object, the data inversion coding apparatus according to an embodiment of the present invention determines whether or not the current data is inverted in consideration of the bit transition of the current data and the logic of the previous data inversion information signal from the previous data A data inversion determining unit; And a data conversion unit for inverting or noninverting the current data according to the determination of the data inversion determination unit and outputting the inverted or inverted data as output data. Here, the previous data inversion information signal has information on whether the previous data is inverted.

According to another aspect of the present invention, there is provided a data inversion coding apparatus including: a transition determining unit for comparing a current data with a previous data to detect a transition bit; And an inversion decision circuit section for determining whether the current data is inverted in consideration of the output from the transition determining section and the logic of the previous data inversion information signal. Here, the inversion decision circuit part may determine that the bits of the current data inversion information signal having the inversion / non-inversion of the current data and the inversion / non-inversion information are different from the bits of the previous data and the previous data inversion information signal 2N is the total number of bits of the current data.

According to another aspect of the present invention, there is provided a data inversion coding method comprising the steps of: determining whether the current data is inverted in consideration of a bit transition of current data and a logic of a previous data inversion information signal from previous data; Inverting or noninverting the current data according to the determination of the data inversion determining unit and outputting the inverted or inverted data as output data; And outputting a current data inversion information signal having information on inversion or non-inversion of the current data. Here, the previous data inversion information signal has information on whether the previous data is inverted, and the current data inversion information signal has information on whether the current data is inverted.

The data inversion coding apparatus according to another embodiment of the present invention may further include a data inversion coding apparatus for performing inverse and inverse inversion of the current data, A data inversion determining unit for determining whether or not the data is inverted; And a data conversion unit for inverting / noninverting the current data according to the determination and outputting the inverted data as the output data. Herein, 2N denotes the total number of bits of the current data, and the data inversion information signal has information on the inversion / non-inversion.

The data inversion coding method according to another embodiment of the present invention is a method of inverting the current data so that the number of bits corresponding to the reference data bit among the bits of the output data and the data inversion information signal according to the inversion / non- Determining whether to invert; And inverting / noninverting the current data according to the determination to output the output data as the output data. Herein, 2N denotes the total number of bits of the current data, and the data inversion information signal has information on the inversion / non-inversion.

Since the apparatus and method for reversing data according to the present invention inverts / non-inverts the current data in consideration of the DBI flag signal, the number of bit transitions can be maintained substantially equal to or less than N (2N is the total number of bits of the current data) The resulting SSN can be reduced.

In addition, the data inversion coding apparatus and method of the present invention can reduce the SSN because the bits corresponding to the reference data bits in the bits of the D present data and the DBI flag signal are coded to be equal to or greater than other bits.

1 is a block diagram illustrating a data inversion coding apparatus according to a first embodiment of the present invention.
2 is a flowchart illustrating a data inversion coding process according to the first embodiment of the present invention.
3 and 4 are diagrams showing application examples of data inversion coding.
5 is a circuit diagram of a data inversion coding apparatus according to an embodiment of the present invention.
6 is a diagram illustrating an inversion decision circuit portion according to an embodiment of the present invention.
FIG. 7 is a flowchart illustrating a data inversion coding process according to a second embodiment of the present invention.
8 and 9 are diagrams showing application examples of data inversion coding.
10 is a block diagram illustrating a data inversion coding apparatus according to a second embodiment of the present invention.
11 is a circuit diagram of a data inversion coding apparatus according to another embodiment of the present invention.
12 is a diagram showing a majority circuit according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data inversion coding apparatus and method for use in a transmitter, and more particularly, to a data inversion coding apparatus and method for reducing Simultaneous Switching Noise (SSN) . Here, SSN means a voltage fluctuation phenomenon that occurs when a change in the inductance components of the line due to (+) and (-) of the voltage suddenly changes as the signal frequency increases and the voltage can not keep up with the change of the voltage.

DBI coding is a technology defined by JEDEC, one of the standards associations, and is used to further reduce power consumption by reducing data pins with low logic values to less than half of the total.

DBI coding can be classified into DBI-AC coding and DBI-DC coding.

The DBI-AC coding compares the current data (parallel data) with the previous data, inverts the current data when the bits exceeding half of all the bits of the current data are data transition from the bits of the previous data, And a DBI flag signal (DBI Flag signal) of high logic having information on the data and the inversion. Of course, if less than half of all bits of the current data are shifted from the bits of the previous data, the current data is transmitted to the receiver without inverting the current data, and the DBI flag signal of the low logic having the non- Lt; / RTI > The receiver non-inverts or inverts the data transmitted through the logic of the DBI flag signal to recover the current data.

DBI-DC coding reverses or non-inverts the current data so that the number of bits to be output (hereinafter, referred to as "reference data bits") is large among "0" and "1". For example, when a large amount of " 0 "s are to be output, data is inverted if the number of bits of" 0 " Without output.

Currently, this DBI-AC coding inverts or non-inverts the current data without considering the logic value of the DBI flag signal. In this case, if half of the bits of the current data are shifted from the bits of the previous data, if the logic value of the current DBI flag signal is different from the logic value of the previous DBI flag signal, the number of transitions actually occurring is (N + 1) As a result, the number of data pins having low logic values is more than half. Here, 2N means the total number of bits of data.

In addition, since the DBI-DC coding does not consider the logical value of the reference data bit, if the logical value of the DBI flag signal is different from the reference data bit when half of the bits of the current data are different from the reference data bit, There arises a problem that the number of data bits and other bits is larger than the number of bits equal to the reference data bits.

Accordingly, the present invention proposes a data inversion coding apparatus and method considering a DBI flag signal or a reference data bit. Hereinafter, for the convenience of explanation, it is assumed that the total number of bits of data is eight. In addition, the bit is assumed to be a binary number of "0" and "1", but is not limited thereto.

Meanwhile, the data reversal coding apparatus and method according to the present invention can be applied to all data transmission / reception interface circuits using a parallel data transmission system, for example, in an interface circuit of a memory used for mobile or graphic purposes, It can be applied to an interface circuit of a memory or the like.

Hereinafter, various embodiments of the data reversal coding apparatus and method of the present invention will be described in detail with reference to the accompanying drawings.

First, let's look at DBI-AC coding.

1 is a block diagram illustrating a data inversion coding apparatus according to a first embodiment of the present invention.

Referring to FIG. 1, the data inversion coding apparatus of the present embodiment may include a data inversion determination unit 100 and a data conversion unit 102.

The data inversion determining unit 100 determines the inversion of the current data by using input data (hereinafter referred to as "current data"), feedback output data (hereinafter referred to as "previous data"), And outputs a current data inversion information signal having information on the inversion. At this time, the current data inversion information signal may be fed back to the input of the data inversion decision unit 100.

Specifically, the data inversion determining unit 100 determines that the current data is not inverted if the number of transitioned bits is equal to or smaller than N in consideration of the number of transition bits of the current data and the previous data and the logic of the previous data inversion information signal fed back, (N + 1), it is determined that the current data is inverted. Here, 2N denotes the total number of bits of the current data.

On the other hand, the data inversion information signal is a signal including information on whether the current data is inverted, for example, a DBI flag signal. The data inversion information signal may have a low logic when there is no inversion of the current data and a high logic when the current data is inverted. Of course, the data inversion information signal may have a low logic when there is no inversion of the current data and a low logic when the current data is inverted.

However, in consideration of the JEDEC standard, it will be assumed that the data inversion information signal is hereinafter referred to as a DBI flag signal, and the data inversion information signal has a high logic at the time of reversing the current data.

The data conversion unit 102 inverts or non-inverts the current data according to the determination of the data inversion determination unit 100 and outputs the data. At this time, the output (previous data) from the data converting unit 102 is fed back to the data inversion determining unit 100. [

In summary, the data inversion coding apparatus of the present embodiment calculates the number of bit transitions in consideration of the DBI flag signal, and controls the coding so that the number of bit transitions is equal to or less than half of the total number of bits of the current data. As a result, the number of bits shifted from the bits of the output data and the current DBI flag signal output from the data conversion unit 102 from the bits of the previous data and the previous DBI flag signal becomes N or less. That is, since the number of bit transitions actually generated is equal to or less than half of the total number of bits of the current data, the data inversion coding apparatus can further reduce the SSN noise, thereby reducing power consumption.

FIG. 2 is a flowchart illustrating a data inversion coding process according to the first embodiment of the present invention, and FIGS. 3 and 4 are views showing application examples of data inversion coding.

Referring to FIG. 2, the data inversion determining unit 100 compares the current data with the previous data, and calculates the number of bits (or bit shift information) in which the bits of the current data are shifted from the bits of the previous data (S200). For example, referring to the current data and the previous data shown in FIG. 3, it can be confirmed that half of all the bits of the current data are shifted from the bits of the previous data.

Then, the data inversion determining unit 100 determines whether the current data is inverted in step S202, considering the calculated number of bit-shifts (or information) and the previous DBI flag signal. A detailed description thereof will be described later with reference to FIG. 3 and FIG.

Subsequently, the data conversion unit 102 non-inverts or inverts the current data according to the determination of the data inversion determination unit 100 (S204).

Then, the data conversion unit 102 outputs the inverted / non-inverted current data, and the data inversion determining unit 100 outputs the current DBI flag signal (S206).

Hereinafter, an actual example of the above data inversion coding process will be described.

0, 0, 0, 0, 0 "and the previous DBI flag signal is" 0 ", and the current data is" 0, 0 , 0, 0, 1, 1, 1, 1 ".

In this case, since the conventional data inversion coding method does not consider the DBI flag signal, the DBI flag signal having the low logic is output without reversing the current data since the bits of the current data are shifted from the bits of the previous data by 4 bits.

The data inversion coding method of the present invention determines whether the current data is inverted in consideration of the previous DBI flag signal. Specifically, even if the current data bits are shifted from the previous data bits by 4 bits and the logic of the previous DBI flag signal is low logic, even if the DBI flag signal having low logic is output, only 4 bits are entirely changed. That is, when the previous DBI flag signal has the low logic corresponding to the data inversion, the DBI flag signal having the low logic is outputted in the same manner as in the prior art when the bits of the current data are shifted from the bits of the previous data by 4 bits do.

However, when the previous DBI flag signal has a high logic, the prior art and the data inversion coding method of the present invention produce different results.

0, 0, 0, 0, 0 "and the previous DBI flag signal is" 1 "and the current data is" 0, 0 , 0, 0, 1, 1, 1, 1 ".

In this case, since the prior art does not consider the DBI flag signal, the DBI flag signal having the low logic is outputted because the bits of the current data are shifted from the bits of the previous data by 4 bits. As a result, since the logic of the DBI flag signal has also transitioned, an actual 5-bit transition occurs.

On the other hand, since the data inversion coding method of the present invention also takes into account the previous DBI flag signal, if the logic of the previous DBI flag signal is high logic corresponding to data inversion, even if the bits of the current data are shifted 4 bits from the bits of the previous data And outputs a DBI flag signal having a high logic level. As a result, the data conversion unit 102 inverts the current data and outputs the data as shown in FIG. At this time, since the current DBI flag signal has not transitioned from the previous DBI flag signal, the number of bits actually shifted from the bits of the output data and the current DBI flag signal and the bits of the previous DBI flag signal becomes four. Therefore, the data inversion coding method of the present invention can further reduce the SSN compared to the prior art.

In summary, when the bits of the current data are shifted by N / 2 from the bits of the previous data, the data inversion coding method of the present embodiment generates the current DBI flag signal having the low logic when the previous DBI flag signal has the low logic , And if the previous DBI flag signal has a high logic, it can generate a current DBI flag signal having a high logic.

That is, in the data inversion coding method, when the bits of the current data are shifted by N / 2 from the bits of the previous data so that the final bit transition becomes N / 2 or less, the logic of the current DBI flag signal becomes logic .

FIG. 5 is a circuit diagram of a data inversion coding apparatus according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating an inversion determination circuit unit according to an embodiment of the present invention.

Referring to FIG. 5, the data inversion coding apparatus of the present embodiment includes a data inversion determination unit 100 and a data conversion unit 102.

The data inversion determining unit 100 may include an inversion determining circuit unit 500, a data feedback unit 502, a DBI feedback unit 504, and a transition determining unit 506.

The data feedback unit 502 feeds back the previous data DQ [7: 0] output from the data conversion unit 102 to the data comparison unit 506. [ According to one embodiment, the data feedback unit 502 may be formed of a D flip-flop so as to hold bits of previous data.

The DBI feedback section 504 feeds back the previous DBI flag signal output from the inversion decision circuit section 500 to the input terminal of the inversion decision circuit section 500. According to one embodiment, the DBI feedback section 504 may be made up of a D flip-flop so that the logic of the previous DBI flag signal is maintained. At this time, the D flip-flop can be synchronized by using the D flip-flop of the data feedback unit 502 and the clock (CLK). Also, the current data, the previous data, and the clock may all have the same data rate.

The transition determining unit 506 compares the current data (Din [7: 0]) with the previous data fed back, and calculates the number of transitioned bits. For example, the transition determining unit 506 may be configured as an XOR gate that outputs a high logic when the input bits are different, that is, a bit transition, and outputs low logic if the bits are the same, that is, when no transition occurs. That is, the transition determining unit 506 can calculate the number of bit transitions of the current data.

The inversion decision circuit unit 500 receives the output (tran [7: 0]) of the transition decision unit 506 and the previous DBI flag signal fed back and determines whether the current data is inverted according to the input output and the previous DBI flag signal Can be determined.

For example, if the number of bit transitions is four and the logic of the previous DBI flag signal is low logic, the inversion decision circuitry 500 determines whether the output of the transition decision unit 506 (tran [7: 0] 0 "because there are 5" 0 "s and 4" 1 " Here, "0" means data inversion.

In other words, if the number of bit transitions is four and the logic of the previous DBI flag signal is high logic, the inversion decision circuit section 500 compares the output (tran [7: 0]) of the transition decision section 506 with the bits 1 "because" 0 "is 4 and" 1 " Here, "1" means data inversion.

According to one embodiment, the inversion decision circuit part 500 may be a majority circuit.

The majority circuit may include a power supply unit 600, an inversion determination unit 602, and an activation unit 604 as shown in FIG.

The power supply unit 600 transmits the power according to the power supply voltage to the inversion determination unit 602 and may have a mirror structure.

The activating unit 604 serves to activate the majority circuit.

The inversion determination unit 602 is connected between the power supply unit 600 and the activation unit 604 and may include a plurality of N-MOS transistors LO to L7, LD, R0 to R7, and RD.

The MOS transistors L0 to L7 and LD are connected in parallel to each other with reference to the node A and the MOS transistors R0 to R7 and RD are connected to the node A They are connected in parallel. At this time, the output (tran [7: 0]) of the transition determining unit 506 and the previous DBI flag signal can be input to the gates of the MOS transistors L0 to L7 and LD, respectively. The inverting bits of the output tran [7: 0] of the transition determining unit 506 and the inverting signal of the previous DBI flag signal are input to the gates of the MOS transistors R0 to R7 and RD, respectively .

Therefore, if the output of the transition determining unit 506 (tran [7: 0]) and the bit of "1" among the bits of the previous DBI flag signal are four or less, the current of the out node is increased The output of the majority circuit has low logic. On the other hand, if the output of the transition determining unit 506 (tran [7: 0]) and the bits of the previous DBI flag signal are "1" or more, the current of the node A is increased So that the output of the majority circuit has high logic.

The data conversion unit 102 may comprise an XOR gate for inverting or noninverting the current data according to the output of the inversion decision circuit unit 500 and for receiving the output of the inversion decision circuit unit 500 and the current data . Therefore, the data conversion unit 102 inverts the current data when the output of the inversion decision circuit unit 500 is low logic, and inverts the current data when the output of the inversion decision circuit unit 500 is high logic.

Finally, it can be confirmed that the current DBI flag signal outputted from the inversion decision circuit part 500 and the output data outputted from the data conversion part 102 are the same as the results shown in FIG. 3 and FIG.

Hereinafter, DBI-DC coding will be described.

FIG. 7 is a flowchart illustrating a data inversion coding process according to the second embodiment of the present invention, and FIGS. 8 and 9 are views showing application examples of data inversion coding.

Referring to FIG. 7, the data inversion coding method of the present embodiment calculates the number (or information) of bits corresponding to the reference data bits among the bits of the current data (S700). Here, the reference data bit means a bit to be transmitted to a receiver of "0" and "1"

In step S702, the data inversion coding method determines whether the current data is inverted so that the number of bits corresponding to the reference data bit in the bits of the output data to be transmitted to the receiver is greater than the number of other bits. For example, if the current data is "0,0,0,0,0,0,0,0,0,0" when the reference data bit is "1", the data inversion coding method has many bits corresponding to the reference data bits 1, 1, 1, 1, 1, 1 "to output the current data.

However, the data inversion coding method determines whether the current data is inverted in consideration of the logic of the DBI flag signal. An explanation thereof will be described later.

Subsequently, the data inversion coding method reverses or inverses the data according to the determination (S704).

The data inversion coding method outputs the inverted / non-inverted data and outputs a DBI flag signal having information on whether the current data is inverted.

Hereinafter, an actual example of the above data inversion coding process will be described.

Assume that the current data (parallel data) is "0, 0, 0, 0, 1, 1, 1, 1" and the reference data bit is "0", as shown in FIG.

In this case, since the conventional data inversion coding method does not consider the DBI flag signal, the DBI flag signal having the low logic is outputted because the number of bits corresponding to the reference data bit among the bits of the current data is 4.

The data inversion coding method of the present invention takes into account the previous DBI flag signal but since the number of bits corresponding to the reference data bit among the bits of the current data is 4 and the logic of the DBI flag signal according to non-inversion is low logic, The DBI flag signal having the low logic is output. As a result, the number of bits corresponding to the reference data bit among the bits of the output data and the DBI flag signal becomes 5, which is greater than the number of other bits.

However, when the reference data bit is "1 ", the conventional technique and the data inversion coding method of the present invention produce different results.

Assume that the current data (parallel data) is "0, 0, 0, 0, 1, 1, 1, 1" and the reference data bit is "1", as shown in FIG.

In this case, since the conventional data inversion coding method does not consider the DBI flag signal, the DBI flag signal having the low logic is outputted because the number of bits corresponding to the reference data bit among the bits of the current data is 4.

On the other hand, the data inversion coding method of the present invention determines whether the current data is inverted in consideration of the DBI flag signal. When the number of bits corresponding to the reference data bit among the bits of the current data is 4 and thus the DBI flag signal having the low logic is outputted, the number of bits corresponding to the reference data bit "1 " The number of bits becomes 5. Therefore, the data inversion coding method of the present invention outputs a DBI flag signal having a high logic even if the number of bits corresponding to the reference data bit among the bits of the current data is 4, and outputs the inverted DBI flag signal. As a result, the number of bits corresponding to the reference data bit "1" is 5 and the number of bits corresponding to "0 " That is, the problem of the prior art is solved.

In summary, in the data inversion coding method of the present embodiment, considering the DBI flag signal as well as the current data, the inversion / non-inversion of the current data is performed so that the number of bits corresponding to the reference data bit is equal to or greater than the number of bits not corresponding to the reference data bit .

A data inversion coding apparatus for realizing such a data inversion coding method is shown in Figs. 10 to 12 below.

10 is a block diagram illustrating a data inversion coding apparatus according to a second embodiment of the present invention.

Referring to FIG. 10, the data inversion coding apparatus of the present embodiment includes a data inversion determination unit 1000 and a data conversion unit 1002.

The data inversion determining unit 1000 receives the current data and reference data bits and determines whether the current data is inverted according to the input data and the reference data bits. For example, if the current data is " 0,0,0,0,0,1,1,1,1 ", and the reference data bit is "1 ", the data inversion determining unit 1000 determines whether the bit of the DBI flag signal Determines that the current data is inverted so that the number of bits corresponding to the reference data bit increases, and outputs the DBI flag signal having the high logic.

The data conversion unit 1002 inverts / non-inverts the current data in accordance with the determination of the data inversion determination unit 1000.

FIG. 11 is a circuit diagram of a data inversion coding apparatus according to another embodiment of the present invention, and FIG. 12 is a diagram illustrating a majority circuit according to another embodiment of the present invention.

Referring to FIG. 11, the data inversion determining unit 1000 may be formed of a majority circuit, and current data (Din [7: 0]) and reference data bits may be input to the input terminal of the majority circuit.

The majority circuit may include a power supply unit, an inversion determination unit, and an activation unit as shown in FIG. The overall circuit configuration of the majority circuit is similar to the overall circuit configuration of the majority circuit of FIG. 6, so that the following description of the structure and operation will be omitted. 6, instead of the transistors LD and RD to which the DBI flag signal or the inverted DBI flag signal is input, the transistors LR and RR to which reference data bits or inverted reference data bits are input, Is used.

The data conversion unit 1002 may comprise an XOR gate for inverting or non-inverting the current data according to the output of the data inversion decision unit 1000, for example, receiving the output and the current data. Therefore, the data conversion unit 1002 inverts the current data when the output of the data inversion determination unit 1002 is low logic, and inverts the current data when the output of the data inversion determination unit 1002 is high logic.

Finally, it can be confirmed that the DBI flag signal output from the data inversion determining unit 1002 and the output of the data converting unit 1002 are the same as the results shown in FIGS. 8 and 9.

In the above embodiments, 8-bit current data has been described as an example. However, the present invention can be applied to 2N (N is an integer) current data.

Further, although data inversion is described above when the logic of the DBI flag signal is high logic, data inversion may be realized when the logic of the DBI flag signal is low logic. In this case, the circuit configuration and operation of the data reversal coding apparatus can be easily implemented by those skilled in the art from the above embodiments, and the description will be omitted.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

100, 1000: Data inversion determination unit 102, 1002: Data conversion unit
500: inverting determination circuit section 502: data feedback section
504: DBI feedback section 506: transition decision section
600: power supply unit 602:
604:

Claims (18)

A data inversion determiner for determining whether the current data is inverted in consideration of the bit transition of the current data and the logic of the previous data inversion information signal from the previous data; And
And a data conversion unit for inverting or noninverting the current data according to the determination of the data inversion determination unit and outputting the inverted or inverted data as output data,
Wherein the previous data inversion information signal has information on whether or not the previous data is inverted and if the total number of bits of the current data is 2N and the number of shifted bits by comparing the current data with the previous data is N, And determines that the logic of the current data inversion information signal having information on whether the current data is inverted is equal to the logic of the previous data inversion information signal. The method of claim 1, wherein the current data and the previous data are parallel data having the same data rate, the previous data inversion information signal is a previous DBI (Data Bus Inversion) flag signal,
Wherein the previous data is a feedback signal output from the data conversion unit and the previous DBI flag signal is a feedback signal output from the data inversion determination unit. 3. The apparatus of claim 2, wherein the data inversion determining unit determines that the bits of the output data and the current DBI flag signal output from the data inversion determining unit are N or less from the previous data and the bits of the previous DBI flag signal And determines whether or not the current data is inverted. 4. The method of claim 3, wherein if the current data is compared with the previous data and the number of transitioned bits is N and the logic of the previous DBI flag signal is high logic indicating inversion, And outputs a current DBI flag signal having a high logic level. delete 3. The data processing apparatus according to claim 2,
A data feedback unit;
DBI feedback section;
A transition determining unit; And
And an inverting decision circuit part,
Wherein the previous data fed back from the data converting unit through the current data and the data feedback unit is input to the transition determining unit and the previous DBI flag signal fed back from the inversion determining circuit unit through the DBI feedback unit and the output of the transition determining unit Inverted decision circuit portion,
And an output from the inversion decision circuit section and the current data are input to the data conversion section. 7. The apparatus of claim 6, wherein the data feedback unit and the DBI feedback unit each include a D flip-flop, the transition determining unit and the data converting unit each include an XOR gate, and the inversion determining circuit unit includes a majority- , ≪ / RTI &
Wherein the clock of the D flip-flops has the same data rate as the current data. 8. The circuit according to claim 7,
First transistors connected to each other in parallel with respect to the A node; And
And second transistors connected in parallel to each other with reference to an out node connected in parallel to the A node based on a power supply voltage,
Wherein the gates of the first transistors are respectively input with the output bits of the transition determining unit and the previous DBI flag signal and the gates of the second transistors are connected with the inverting bits of the output bits and the inverting signal of the previous DBI flag signal Are input to the data reversal coding apparatus. A transition determining unit for comparing the current data with previous data and detecting a transition bit; And
And an inversion decision circuit unit for determining whether the current data is inverted in consideration of a logic of a previous data inversion information signal having an output from the transition determining unit and information on inversion / non-inversion of the previous data,
Wherein the inversion decision circuit comprises: an inversion decision circuit for comparing the output data according to the inversion / non-inversion of the current data and the bits of the current data inversion information signal having information on inversion / non- inversion of the current data, 2N denotes a total number of bits of the current data, and compares the current data with the previous data to obtain the number of shifted bits N, the inversion determining circuit section determines that the logic of the current data inversion information signal is equal to the logic of the previous data inversion information signal. 10. The method of claim 9, wherein when the current data is compared with the previous data and the number of transitioned bits is N and the logic of the previous data inversion information signal is high logic, the inversion determination circuit unit inverts the current data And outputs a current data inversion information signal having high logic. Determining whether the current data is inverted in consideration of the bit shift of the current data and the logic of the previous data inversion information signal from the previous data;
Inverting or noninverting the current data and outputting the inverted data as output data; And
And outputting a current data inversion information signal having information on inversion or non-inversion of the current data,
Wherein the previous data inversion information signal has information on whether the previous data is inverted and the current data inversion information signal has information on whether the current data is inverted and compares the current data with the previous data, And determining that the logic of the current data inversion information signal is equal to the logic of the previous data inversion information signal if the number of bits of the current data shifted from the data is half. 12. The method of claim 11, wherein when the total number of bits of the current data is 2N and the number of transitioned bits by comparing the current data with the previous data is N and the logic of the previous data inversion information signal is high logic indicating inversion And outputs the current data inversion information signal having the high logic by inverting the current data. A data inversion determining unit for determining whether the current data is inverted so that the number of bits corresponding to the reference data bit among the bits of the output data and the data inversion information signal according to the inversion / non-inversion of the current data; And
And a data conversion unit for inverting / noninverting the current data according to the determination and outputting the inverted data as the output data,
2N denotes the total number of bits of the current data, the data inversion information signal has information on the inversion / non-inversion, and the data inversion determination unit determines that the N bits of the current data are equal to the reference data bit Logic determines that the logic of the data inversion information signal has the same logic as the reference data bit. 14. The apparatus of claim 13, wherein the data inversion information signal is a DBI flag signal, the current data and the reference data bit are input to the data inversion determination unit, and the data inversion determination unit And determines whether the current data is inverted or not. delete 15. The apparatus of claim 14, wherein the data inversion determining unit is a majority circuit, and the data converting unit includes an XOR gate,
Wherein the current data and the output of the data inversion determination unit are input to the data conversion unit, and the data inversion determination unit outputs the DBI flag signal. 17. The circuit according to claim 16,
First transistors connected to each other in parallel with respect to the A node; And
And second transistors connected in parallel to each other with reference to an out node connected in parallel to the A node based on a power supply voltage,
Wherein the bits of the current data and the reference data bits are respectively input to the gates of the first transistors and the inverting bits of the bits of the current data and the inverting bits of the reference data are And the data is inverted. Determining whether the current data is inverted so that the number of bits corresponding to the reference data bit among the bits of the output data and the data inversion information signal according to the inversion / non-inversion of the current data is N or more; And
Inverting the current data according to the determination and outputting the inverted data as the output data,
2N denotes the total number of bits of the current data, the data inversion information signal has information on the inversion / non-inversion, and if N bits of the current data have the same logic as the reference data bit, Wherein the logic of the inverted information signal is determined to have the same logic as the reference data bit.

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