KR101647839B1 - Semiconductor Device Having Balanced Band-Pass Filter Implemented with LC Resonators - Google Patents

Abstract

The bandpass filter has a plurality of frequency band channels including a first inductor each having a first terminal connected to the first balance port and a second terminal connected to the second balance port. A first capacitor is connected between the first and second terminals of the first inductor. The second inductor has a first terminal connected to the first unbalanced port and a second terminal connected to the second unbalanced port. The second inductor is located within a first distance of the first inductor to induce an electromagnetic coupling. A second capacitor is connected between the first and second terminals of the second inductor. A third inductor is located within a second distance of the first inductor and a third distance of the second inductor to induce the electromagnetic coupling. And a third capacitor is connected between the first and second terminals of the third inductor.

Semiconductor devices, capacitors, inductors, integrated circuits, magnetic induction, electronic coupling, balanced ports, unbalanced ports

Description

[0001] The present invention relates to a semiconductor device having a balanced band-pass filter implemented by an LC resonator,

Domestic priority claim

The present application claims priority benefit to U. S. Patent Application Serial No. 61 / 017,360, filed December 28, 2007, entitled " Balanced BPF Using LC Resonator "by Kai Liu et al.

The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device having a balanced band-pass filter implemented with an LC resonator.

Semiconductor devices are commonly found in modern electronics. Semiconductor devices vary in number and density of electronic components. Individual semiconductor devices typically include one form of electrical component such as a light emitting diode (LED), a transistor, a resistor, a capacitor, an inductor, and a power MOSFET (metal oxide semiconductor field effect transistor). Integrated semiconductor devices typically include hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirrors (DMDs).

Some semiconductor devices perform a wide range of functions such as high speed computation, transmission and reception of electromagnetic signals, control of electronic devices, conversion of sunlight into electric arc furnaces, and visual projection for television displays. Semiconductor devices are found in products for the entertainment, communications, network, computer, and home market sectors. Semiconductor devices are also found in military, aerospace, automotive, industrial controllers and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its electrical conductivity to be controlled through application of an electric field or doping process. Doping introduces impurities into the semiconductor material to control or control the conductivity of the semiconductor devices. And performs various electrical functions necessary for each of these applications. One semiconductor device includes active and passive electrical structures. The active structure, including the transistors, controls the current flow. By varying the doping and application of the electric field, the transistor promotes or limits the flow of current. Passive structures including resistors, diodes and inductors form the relationship between voltage and current necessary to perform various electrical functions. Such active and passive structures are electrically connected to form logic circuits that allow the semiconductor device to perform high-speed computation and other useful functions.

Semiconductor devices are typically manufactured using complex manufacturing processes such as front-end manufacturing and back-end manufacturing, each of which potentially includes hundreds of steps. Front-end fabrication involves forming multiple dies on a surface of a semiconductor wafer. Each semiconductor die typically includes circuits formed by electrically connecting the same and active and passive components. Back-end fabrication means singulating the final wafer into individual die and packaging for structural support and environmental isolation.

One goal of semiconductor fabrication is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be manufactured more efficiently. In addition, smaller semiconductor devices have a smaller footprint that is suitable for small end products. The small die size can be achieved by the improvement of the front-end process of making the die with small, high-density active and passive components. Back-end processes can lead to semiconductor device packages with smaller footprints by improvements in electrical connections and packaging materials.

Another goal for semiconductor fabrication is to fabricate high performance semiconductor devices. Increasing device performance can be achieved by forming active components that can operate at high speeds. BACKGROUND OF THE INVENTION In high frequency applications such as radio frequency (RF) wireless communications, integrated passive devices (IPDs) are often included within semiconductor devices. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the necessary electrical functions.

Baluns and band-pass filters (BPFs) are important components in wireless communication systems. Many conventional arrangements achieve both balancing and filtering functions using individual, cascaded components. The balloon is implemented as a distribution-lnie whose size is inversely proportional to the operating frequency. The smaller the operating frequency, the larger the required balloon. However, consumer demand requires a smaller size that makes miniaturization difficult in low frequency applications such as GSM cellular.

 There is a need to minimize balloons for RF signal processing circuits.

Thus, in one embodiment, the present invention provides a band-pass filter comprising a plurality of frequency band channels, each having first and second balanced ports and first and second unbalanced ports. Each frequency band channel has a first inductor having a first terminal connected to the first balance port and a second terminal connected to the second balance port. A first capacitor is connected between the first and second terminals of the first inductor. The second inductor has a first terminal connected to the first unbalanced port and a second terminal connected to the second unbalanced port. The second inductor is positioned within a first distance from the first inductor to induce an electromagnetic coupling between the first inductor and the second inductor. A second capacitor is connected between the first and second terminals of the second inductor. A third inductor is located within a third distance from the first inductor and a second distance from the second inductor to induce electron coupling between the first, second, and third inductors. A third capacitor is connected between the first and second terminals of the third inductor.

In another embodiment, the present invention provides a band-pass filter comprising a plurality of LC resonators, each having first and second balanced ports and first and second unbalanced ports. The band-pass filter includes a first inductor having a first terminal connected to the first balance port and a second terminal connected to the second balance port. A first capacitor is connected between the first and second terminals of the first inductor. The second inductor has a first terminal connected to the first unbalanced port and a second terminal connected to the second unbalanced port. The second capacitor is connected between the first and second terminals of the second inductor. The third inductor is positioned adjacent to the first inductor and the second inductor to induce an electromagnetic coupling between the first, second and third inductors. The third capacitor is connected between the first and second terminals of the third inductor.

In another embodiment, the present invention provides an LC resonator circuit comprising a first inductor having first and second terminals. A first capacitor is connected between the first and second terminals of the first inductor. The second inductor has first and second terminals. The second capacitor is connected between the first and second terminals of the second inductor. The third inductor is positioned adjacent to the first and second inductors to induce electron coupling between the first, second and third inductors. The third capacitor is connected between the first and second terminals of the third inductor.

In another embodiment, the present invention provides an integrated circuit package housing multiple LC resonators and having first, second, third and fourth interconnect terminals. The integrated circuit includes a first inductor having a first terminal connected to the first interconnect terminal and a second terminal connected to the second interconnect terminal. A first capacitor is connected between the first and second terminals of the first inductor. The second inductor has a first terminal connected to the third interconnection terminal and a second terminal connected to the fourth interconnection terminal. The second capacitor is connected between the first and second terminals of the second inductor. The third inductor is positioned adjacent to the first and second inductors to induce electron coupling between the first, second and third inductors. A third capacitor is connected between the first and second terminals of the third inductor.

Minimizing balloons for RF signal processing circuits.

The invention will be described in more detail in one or more of the following description with reference to the drawings in which like numerals represent like or similar elements. While the present invention has been described in terms of the best modes for carrying out the objects of the invention, those skilled in the art will readily appreciate that many modifications are possible in the spirit and scope of the invention as defined by the appended claims and their equivalents as are supported by the following description and drawings Variations, changes and substitutions without departing from the spirit and scope of the invention.

Semiconductor devices are typically fabricated using two complex processes: front-end fabrication and back-end fabrication. Front-end manufacturing generally means forming multiple semiconductor die on the surface of the wafer. Each die on the wafer includes active and passive electrical components, which are electrically connected to form a functional electrical circuit. Active electronic components such as transistors have the ability to control current flow. Passive components such as capacitors, inductors, resistors and transformers create the voltage and current relationships needed to perform electrical circuit performance.

Passive and active components are formed on the surface of the semiconductor wafer by a series of process steps including doping, fusing, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process changes the electrical conductivity of the semiconductor material in an active device, converts the semiconductor material to a permanent insulator, a permanent conductor, or changes the way the semiconductor material changes in conductivity in response to an electric field. Transistors include regions of various types and degrees of doping arranged such that the transistors are required to facilitate or limit the flow of current in accordance with the application of an electric field.

The active and passive components are comprised of layers of material having different electrical properties. The layers can be formed by various fusion techniques, which are determined in part by the type of material to be fused. For example, thin film fusing includes chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. Each layer is typically patterned to form active connections, passive components, or electrical connections between the components.

The layers can be patterned using photolithography, which involves the fusion of a photosensitive material such as a photoresist over the layer to be patterned. One pattern is transferred from the photomask to the photoresist using light. The portion of the photoresist pattern that receives light is removed using a solvent to expose the underlying layers that are patterned. The remainder of the photoresist is removed, leaving behind the patterned layer. Alternatively, some forms of the material are patterned by directly fusing the material into regions or voids formed by previous fusing / etching processes using techniques such as electroplating and electroless plating.

Fusing onto an existing pattern of thin film material can worsen the underlying pattern and create a non-uniform flat surface. Flat surface uniformity is required to make smaller and more dense active and passive components. Planarization can be used to remove material from the wafer surface to create a uniform flat surface. The planarization includes polishing the wafer surface with a polishing pad. During polishing, abrasive and corrosive chemicals are added to the wafer surface. The combination of the mechanical action of the abrasive material and the corrosive action of the chemical material removes the irregular shape, resulting in a uniform flat surface.

Back-end fabrication refers to packaging the die for structural support and environmental separation after cutting or singulating the final wafer into individual die. To singulate a die, the wafer is broken along the non-functional area of the wafer, referred to as a saw street or scribe, and is broken. The wafer is singulated using a laser cutting device or a saw blade. After singulating, the individual die is mounted to a package substrate comprising pins or contact pads for interconnecting with other system components. The contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connections may be made of solder bumps, stud bumps, conductive pastes, or wire bonds. An encapsulant or other molding material is fused onto the package to provide physical support and electrical isolation. The final package is then inserted into the electrical system and the functionality of the semiconductor device becomes available to other system components.

1 shows an electronic device 10 having a chip carrier substrate or a printed circuit board (PCB) 12 with a plurality of semiconductor packages mounted on its surface. The electronic device 10 may have one form of a semiconductor package or multiple forms of a semiconductor package depending on the application. Different forms of semiconductor packages are shown in FIG. 1 for illustration purposes.

The electronic device 10 may be a stand-alone system using a semiconductor package to perform an electrical function. Further, the electronic device 10 may be a sub-component of a larger system. For example, the electronic device 10 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an application specific integrated circuit (ASIC), a logic circuit, an analog circuit, an RF circuit, discrete devices or other semiconductor dies or electrical components.

In Figure 1, the PCB 12 provides a general substrate for structural support and electrical interconnection of a semiconductor package mounted on a PCB. The conductive signal traces 14 are formed on or in the surface of the PCB 12 using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal fusing process. The signal trace 14 provides electrical communication between each of the semiconductor package, the mounted components, and other external system packages. Trace 14 also provides power and ground connections to each of the semiconductor packages. In some embodiments, the semiconductor device has two package levels. First level packaging is a technique for electrically and mechanically attaching a semiconductor die to a carrier. Second level packaging involves attaching the carrier electrically and mechanically to the PCB. In another embodiment, the semiconductor device may have a first level packaging in which the die is mechanically and electrically directly mounted to the PCB.

For purposes of illustration, various forms of first level packaging are illustrated on the PCB 12, including a wire bond package 16 and a flip chip 18. A ball grid array (BGA) 20, a bump chip carrier (BCC) 22, a dual in-line package (DIP) 24, a land grid array a land grid array (LGA) 26, a multi-chip module (MCM) 28, a quad flat non-leaded package (QFN) 30, Various forms of second level packaging, including flat packages 32, have been shown mounted on the PCB 12. Depending on the system requirements, any combination of semiconductor packages consisting of any combination of the first and second level packaging types as well as other electronic components may be connected to the PCB 12. [ In some embodiments, the electronic device 10 includes a single attached semiconductor package, while other embodiments include multiple interconnection packages. By combining one or more semiconductor packages on a single substrate, manufacturers can include prebuilt components in an electronic device or system. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and shorter manufacturing processes. The resulting devices are less prone to failure and less costly, resulting in lower costs for consumers.

2A shows another detail of the DIP 24 mounted on the PCB 12. In Fig. The DIP 24 includes a semiconductor die 34 having contact pads 36. The semiconductor die 34 has an active area including analog devices or digital circuits implemented as active devices, passive devices, conductive layers, and insulating layers formed in the semiconductor die 34, Respectively. For example, the circuitry may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed in the active region of die 34. The contact pad 36 is made of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold And is electrically connected to the elements. The contact pads 36 are formed by PVD, CVD, electroplating, or electroless plating processes. During assembly of the DIP 24, the semiconductor die 34 is mounted to the carrier using an adhesive material such as a gold-silver process layer or thermal epoxy. The package body includes an insulating package material such as a polymer or ceramic. A conductor lead 40 is connected to the carrier 38 and a wire bond 42 is formed between the lead 40 and the contact pad 36 of the die 34 as a first level packaging. An encapsulant 44 is fused onto the package for environmental protection by preventing moisture or particles from entering the package and contaminating the die 34, contact pads 36, or wire bonds 42. The DIP 24 is connected to the PCB 12 by inserting the leads 40 into holes formed through the PCB 12. A solder material 46 flows around the lid 40 and enters the hole to physically and electrically connect the DIP 24 to the PCB 12. The solder material 46 may be selected from the group consisting of tin (Sn), lead (Pb), gold (Au), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi) , ≪ / RTI > and the like. For example, the solder material may be process Sn / Pb, high lead or lead-free.

FIG. 2B shows another detail of the BCC 22 mounted on the PCB 12. FIG. Semiconductor die 47 is connected to the carrier by wirebonded first level packaging. The BCC 22 is mounted on the PCB 12 as a BCC type second level packaging. A semiconductor die 47 with contact pads 48 is mounted on the carrier using an underfill or epoxy-resin adhesive 50. [ The semiconductor die 47 has an active area including analog devices or digital circuits implemented as active devices, passive devices, conductive layers, and insulating layers formed in the semiconductor die 47, Respectively. For example, the circuitry may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active area of the die 47. The contact pad 48 is made of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag) And is electrically connected to the elements. The contact pads 48 are formed by PVD, CVD, electroplating, or electroless plating processes. Wire bonds 54 and bond pads 56 and 58 electrically connect contact pads 48 of semiconductor die 47 to contact pads 52 of BCC 22 forming first level packaging. A molding compound or encapsulant 60 is fused onto the semiconductor die 47 to provide physical support and electrical isolation of the device. A contact pad 64 is formed on one surface of the PCB 12 using evaporation, electrolytic plating, electroless plating, screen printing, PVD or other suitable metal fusing process, and is generally plated to prevent oxidation. The contact pad 64 electrically connects one or more conductive signal traces 14. The solder material is fused between the contact pads 52 of the BCC 22 and the contact pads 64 of the PCB 12. [ The solder material is reflowed to form bumps 66 that form a mechanical and electrical connection between the BCC 22 and the PCB 12.

2C, the semiconductor die 18 is mounted face-down on the carrier 76 with flip-chip type first level packaging. The BGA 20 is attached to the PCB 12 in a BGA type second level packaging. The active regions, including active devices, passive devices, conductive layers, and analog or digital circuits implemented as insulating layers, formed in the semiconductor die 18 are electrically interconnected according to the electrical design of the die. For example, the circuitry may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed in the active area 70 of the die 18. The semiconductor die 18 is mechanically or electrically attached to the carrier 76 via a plurality of discrete conductive solder bumps or balls 78. Solder bumps 76 are formed on the bump pads or interconnection sites 80 that are located on the active area 70. The bump pads 80 are made of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag) And is electrically connected to the formed circuit elements. The bump pads 80 are formed by PVD, CVD, electroplating, or electroless plating processes. The solder bumps 78 are electrically and mechanically connected to the interconnect sites 82 on the contact pads or carriers 76 by a solder reflow process. The BGA 20 is mechanically and electrically attached to the PCB 12 by a plurality of discrete conductive solder bumps or balls 86. Solder bumps are formed on the bump pads or interconnecting sites 84. The bump pads 84 are electrically connected to the interconnect sites 82 through conductive lines 90 routed through the carrier 76. A contact pad 88 is formed on one surface of the PCB 12 using evaporation, electrolytic plating, electroless plating, screen printing, PVD or other suitable metal fusing process, and is generally plated to prevent oxidation. The contact pad 88 electrically connects one or more conductive signal traces 14. Solder bumps 86 are electrically and mechanically connected to the contact pads or bonding pads 88 on the PCB 12 by a solder reflow process. A molding compound or encapsulant 92 is fused onto semiconductor die 18 and carrier 76 to provide physical support and electrical isolation of the device. The flip-chip semiconductor device includes a short electrical path from the active devices on the semiconductor die 18 to the conductive track on the PCB 12 to reduce the signal propagation distance, achieve low capacitance, and achieve overall good circuit performance. Providing a conductive path. In another embodiment, semiconductor die 18 may be mechanically and electrically connected directly to PCB 12 using flip chip type first level packaging without carrier 76.

Referring to FIG. 3, a semiconductor die or package 94 includes a semiconductor substrate 96 made of silicon (Si), gallium arsenide (GaAs), glass or other bulk semiconductor material for structural support. An active region 98 is formed on the surface of the semiconductor substrate 96. Active region 98 includes active devices, integrated passive devices (IPD), conductive layers, and insulating layers in accordance with the electrical design of the die. Active devices include transistors, resistors, diodes, and the like. The IPD includes thin film transistors, resistors and capacitors. The active area 98 occupies about 5-10% of the overall thickness or height H1 of the semiconductor die 98. The semiconductor die 94 may be electrically connected to other devices using flip chips, bond wires, or interconnecting pins.

Semiconductor devices including multiple IPDs can be used in high frequency applications such as microwave, radar, communication devices, wireless transceivers, electronic switches, and other devices that perform radio frequency (RF) electrical functions. The IPD can be used in conjunction with balloons (balanced and unbalanced), resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonator transformers, matching network and tuning capacitors. For example, the IPD can be used as front-end wireless RF components that can be located between the antenna and the transceiver. The wireless applications may include multiple bands such as wideband code division multiple access (WCDMA) bands (PCS, IMT, low) and global system mobile communication (GSM) bands (low and high) Lt; RTI ID = 0.0 > a < / RTI >

Balloons can often be used to change impedance through magnetic coupling and minimize common-node noise. In some applications, multiple balloons are formed on the same substrate to enable multi-band operation. For example, two or more balloons may be used in a quad-band for mobile phones or other GSM communicators, each balloon representing an operating frequency band of a quad-band device. A typical RF system requires multiple IPDs and other high frequency circuits in one or more semiconductor packages to perform the required electrical functions.

4 shows a wireless communication system 100 using an RF integrated circuit (RFIC) The RFIC 102 performs BPF signal processing of RF signals in five distinct frequency band processing channels. The RFIC 102 includes a frequency band A, a frequency band B, a frequency band C, a frequency band D, (E). The frequency band A has an unbalanced port or terminal 104 and the frequency band B has an unbalanced port or terminal 106. The frequency band C has an unbalanced port or terminal 108, (D) has an unbalanced port or terminal (110), and the frequency band (E) has an unbalanced port or terminal (112). The ground terminal 116 is the return path for unbalanced ports 104-112 in frequency band A-E. The frequency band A has a balanced port or terminals 118, 120; The frequency band B has a balanced port or terminals 122, 124; The frequency band C has a balanced port or terminals 126 and 128 and the frequency band D has a balanced port or terminals 130 and 132. The frequency band E is connected to a balanced port or terminals 134, 136). The balance ports 118-136 are each connected to the transceiver 140 for other transmitter and receiver signal processing. Wireless RF components use multiple bands to increase functionality and service. For example, frequency bands A-C process WCDMA and frequency band D-E processes GSM. The RFIC 102 uses a balloon in each frequency band (A-E) to transform the impedance and minimize common-mode noise.

FIG. 5 shows details of another layout of the RFIC 102 with a frequency band (A-E) processing channel. In one embodiment, the RFIC 102 occupies an area of 3.2 mm x 2.2 mm. 6A shows a schematic circuit diagram equivalent to the capacitor 142 and the inductor 144 connected between the unbalanced port 104 and the ground terminal 116 and between the unbalanced port 104 and the ground terminal 116 Giving. An inductor 146, a capacitor 150 and a resistor 152 are connected between the balance ports 118, The register 152 provides a flat pass-band response. A direct current (DC) power supply bus 154 is connected to the center point of the inductor 146. The DC power bus 154 is common to all connected devices. DC power is applied at terminal 156. Because of the close spatial and interleaving layout, mutual inductance and electromagnetic coupling is induced between the inductors 144, 146. Thus, inductors 144-146 operate as part of the balloon in the BPF arrangement of frequency band A.

The frequency band B includes the unbalanced port 106, the ground terminal 116 and the capacitors 160 and 162 connected between the unbalanced port 106 and the ground terminal 116, . An inductor 164, a capacitor 166, and a resistor 168 are connected between the balance ports 122, The register 152 provides a flat pass-band response. A direct current (DC) power supply bus 154 is connected to the center point of the inductor 164. The DC power bus 154 is common to all connected devices. DC power is applied at terminal 156. Due to the close spatial and interleaving layout, mutual inductance and electromagnetic coupling is induced between the inductors 162 and 164. Thus, the inductors 162-164 operate as part of the balloon in the BPF arrangement of frequency band B.

The frequency band C includes the unbalanced port 108, the ground terminal 116 and the capacitors 170 and inductors 172 connected between the unbalanced port 108 and the ground terminal 116, . An inductor 174, a capacitor 176 and a resistor 178 are connected between the balance ports 126 and 128. [ The register 178 provides a flat pass-band response. A direct current (DC) power supply bus 154 is connected to the center point of the inductor 174. Because of the close spatial and interleaving layout, mutual inductance and electromagnetic coupling are induced between the inductors 172, 174. Thus, inductors 172-174 operate as part of the balloon in the BPF arrangement of frequency band C.

The frequency band D is configured similar to FIG. 6B, including the unbalanced port 110, the ground terminal 116, and the capacitor 182 connected between the unbalanced port 110 and the ground terminal 116. An inductor 186 is connected between unbalanced port 110 and node 185. A capacitor 184 is connected between the node 185 and the ground terminal 116. A parallel combination of inductor 188 and capacitor 190 is connected between nodes 185 and 191. A capacitor 192 and an inductor 194 are connected between the node 191 and the ground terminal 116. Capacitors 182, 184, 190, 192 and inductors 186, 188 act as low-pass filters. An inductor 196 is connected between the balance ports 130 and 132. A combination of series of capacitors 198 and 200 is connected between the balanced ports 130 and 132. A resistor 202 is connected between the balance ports 130 and 132. The register 202 provides a flat pass-band response. A direct current (DC) power supply bus 154 is connected to the connection between the center point of the inductor 196 and the capacitors 198 and 200. Due to the close spatial and interleaving layout, mutual inductance and electromagnetic coupling are induced between the inductors 194, 196. Thus, the inductors 194-196 operate as part of the balloon in the BPF arrangement of the frequency band D.

The frequency band E is configured similar to FIG. 6C, including an unbalanced port 112, a ground terminal 116, and an inductor 210 connected between the unbalanced port 112 and the node 212. A capacitor 214 is connected between the ground terminal 116 and the node 212. A parallel combination of inductor 218 and capacitor 216 is connected between nodes 212 and 220. [ A capacitor 222 and an inductor 224 are connected between the node 220 and the ground terminal 116. Capacitors 214, 216, 220 and inductors 210, 218 act as low-pass filters. An inductor 226 is connected between the balance ports 134, 136. A combination of the series of capacitors 228 and 230 is connected between the balance ports 134 and 136. A resistor 232 is connected between the balance ports 134 and 136. The register 232 provides a flat pass-band response. A direct current (DC) power supply bus 154 is connected to the connection between the center point of the inductor 226 and the capacitors 228 and 230. Because of the close spatial and interleaving layout, mutual inductance and electromagnetic coupling are induced between the inductors 224, 226. Thus, the inductors 224-226 operate as part of the balloon in the BPF arrangement of the frequency band (E).

Another embodiment of the balloon used in the RFIC 102 is shown in FIG. The balloon 238 is implemented using an LC (inductor and capacitor) resonator that can be integrated on the substrate 93 of FIG. In this case, the balloon 238 is connected between the unbalanced port and the balanced port of the RFIC 102. Inductor 240 includes first and second end terminals connected to unbalanced ports 242, 244. In one embodiment, port 242 is a single ended unbalanced port and port 244 is a ground terminal. Also, port 244 is a single-ended unbalanced port and port 242 is a ground terminal. Capacitor 246 is connected between unbalanced ports 242 and 246. The inductor 240 and the capacitor 246 constitute a first LC resonator. The inductor 248 includes first and second end terminals connected to the balance ports 250, 252. The capacitor 254 is connected between the balance ports 250 and 252. The inductor 248 and the capacitor 254 constitute a second LC resonator. The inductor 256 includes end terminals 258, 260. The capacitor 262 is connected in series between the end terminals 258 and 260 of the inductor 256. The inductor 256 and the capacitor 262 constitute a third LC resonator. The inductor 256 is positioned at the periphery of the inductors 240 and 248 so as not to overlap with a plane interval of d2, d3, d4, and d5. Inductor 256 may have a larger, smaller, or even harmonized value with inductors 240, 248.

The circuit layout shown in Figure 7 is implemented in the RFIC 102 and provides balloon and filter functions such as balance filters in a small foam form factor. The circuit includes three LC resonators using mutual inductive or magnetic inductive connections. The inductors 240, 248, and 256 may have a rectangular, polygonal, or circular shape or shape, and may be wound to create an electronic coupling. The capacitors 246 and 254 provide electrostatic discharge (ESD) protection for the balloon. The inductors 240, 248, and 256 are implemented with an 8 탆 conductive material such as Al, Cu, Sn, Ni, Au, or Ag. The capacitors 246, 254, and 262 are implemented using an insulating thin film. The thin film material increases the capacitance density. The robustness of ESD in thin film materials can be verbalized using inductive shunt protectors across weak capacitors. In an ESD event, most of the energy is collected at low frequencies, in which the inductor in the nano-Henry range becomes an effective short circuit. In a magnetic connection circuit, each capacitor is protected by a low value shunt inductor to increase the stiffness of the ESD.

The mutual inductance or the electromagnetic coupling strength between the inductors 240 and 248 is determined by the distance d1 between the coils. Similarly, the electromagnetic coupling strength between the inductors 240 and 256 and between the inductors 248 and 256 is determined by the distances d2, d3, d4 and d5 between the two coils. In one embodiment, the distance d1-d5 is set to 10 mu m. The BPF parameter is selected by adjusting the separation between the inductive rings capacitively loaded to tune the electron coupling. The capacitors 246, 254, and 262 are tuned to match the impedance for the required application.

Unbalanced ports 242 and 244 and balance ports 250 and 252 do not share a common DC reference. Each input and output can operate either single-ended or differential. There is no need for a separate balloon transformer in applications requiring balance-to-unbalance conversion.

Another embodiment of the balloon used in the RFIC 102 is shown in FIG. The balloon 268 may be implemented using an LC resonator that may be integrated on the substrate of FIG. In this case, the balloon 268 is connected between the balance ports and the unbalanced ports of the RFIC 102. Inductor 270 includes first and second end terminals connected to unbalanced ports 272 and 274. In one embodiment, port 272 is a single-ended unbalanced port and port 274 is a ground terminal. Also, the port 274 is a ground terminal. Capacitor 276 is connected between unbalanced ports 272 and 274. The inductor 270 and the capacitor 276 constitute the first LC resonator. The inductor 278 includes first and second end terminals connected to the balance ports 280,282. The capacitor 284 is connected between the balance ports 280 and 282. The inductor 278 and the capacitor 284 constitute a second LC resonator. Inductor 270 is located at a distance d6 from inductor 278. [ The inductor 290 includes end terminals 292, 294. The capacitor 296 is connected in series between the end terminals 292 and 294 of the inductor 290. The inductor 290 and the capacitor 296 constitute a third LC resonator. The inductor 290 overlaps the inductors 270 and 278 in a vertically electrically insulated state and has a planar spacing d7, d8, d9, and d10. The inductor 290 may have a larger, smaller or even harmonized value with the inductors 270 and 278.

The circuit layout shown in Figure 8 is implemented as an RFIC and provides balloon and filter functions such as balance filters in a small foam form factor. The circuit includes three LC resonators using mutual induction or magnetic flow connections. The inductors 270, 278, and 290 may have a rectangular, polygonal, or circular shape or shape, and may be wound to create an electromagnetic coupling. The capacitors 276 and 284 provide ESD protection for the balloon. The inductors 270, 278, and 290 are implemented with an 8 탆 conductive material such as Al, Cu, Sn, Ni, Au, or Ag. The capacitors 276, 284, and 296 are implemented using an insulating thin film. The thin film material increases the capacitance density. The robustness of ESD in thin film materials can be verbalized using inductive shunt protectors across weak capacitors. In an ESD event, most of the energy is collected at low frequencies, in which the inductor in the nano-Henry range becomes an effective short circuit. In a magnetic connection circuit, each capacitor is protected by a low value shunt inductor to increase the stiffness of the ESD.

The mutual inductance or electromagnetic coupling strength between the inductors 270, 278 is determined by the distance d6 between the coils. Similarly, the electromagnetic coupling strength between the inductors 270 and 290 and between the inductors 278 and 290 is determined by the distances d7, d8, d9 and d10 between the two coils. In one embodiment, the distance d6-dlO is set to 10 [mu] m. The BPF parameter is selected by adjusting the separation between the inductive rings capacitively loaded to tune the electron coupling. The capacitors 276,284, and 296 are tuned to match the impedance for the required application.

Unbalanced ports 272 and 274 and balance ports 280 and 282 do not share a common DC reference. Each input and output can operate either single-ended or differential. There is no need for a separate balloon transformer in applications requiring balance-to-unbalance conversion.

9 is a graph of insertion loss versus frequency of balloon 238 for different values of dl. 10 is a graph of insertion loss versus frequency of balloon 238 for different values of d2. 11 is a graph of insertion loss versus frequency of balloon 238 for different values of d3.

 While one or more embodiments of the invention have been described in detail, it will be understood that variations and modifications may be made thereto without departing from the scope of the invention as set forth in the following claims.

Figure 1 shows a PCB on which different types of packages are mounted on the surface.

Figures 2a-2c show other details of a semiconductor package mounted on a PCB.

3 shows a semiconductor package including an integrated semiconductor device.

Figure 4 illustrates a multi-channel RF signal processing circuit coupled to a transceiver.

Fig. 5 shows the layout of the multi-channel RF signal processing circuit.

Figures 6A-6C are schematic diagrams of separate RF signal processing circuits.

Figure 7 shows a multiple LC resonator for use in an RF signal processing channel.

Figure 8 shows another embodiment of an LC resonator for use in an RF signal processing channel.

9 is a graph of insertion loss versus frequency for a different distance d1 between the inductors of the LC resonator.

10 is a graph of insertion loss versus frequency for a different distance d2 between the inductors of the LC resonator.

11 is a graph of insertion loss versus frequency for a different distance d3 between the inductors of the LC resonator.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

10: Semiconductor device 12: PCB

14: TRACE 16: WIRE BOND PACKAGE

20: BGA 34: Die

36: contact pad 76: carrier

82: Interconnection site 90 challenging lines

Claims (31)

delete delete delete delete delete delete delete A band-pass filter comprising a plurality of LC resonators, each comprising first and second balanced ports and first and second unbalanced ports, Wherein the LC resonator comprises: A first inductor including a first end terminal connected to the first balance port and a second end terminal connected to the second balance port;         A first capacitor connected between the first end terminal and the second end terminal of the first inductor; A second inductor having a first portion of a second inductor in parallel with a first portion adjacent the second inductor of the first inductor, wherein a first end terminal of the second inductor is connected to the first unbalanced port, A second end terminal of the second inductor is connected to the second unbalanced port;         A second capacitor connected between the first end terminal and the second end terminal of the second inductor; A first portion of a third inductor in parallel with a second portion of the first inductor adjacent to the third inductor, a second portion of a third inductor parallel to a second portion of the second inductor adjacent to the third inductor, A third inductor including a terminal and a second end terminal; And And a third capacitor connected between the first end terminal and the second end terminal of the third inductor, wherein the third inductor is disposed adjacent to the first and second inductors to form first, second, and third inductors, To induce electromagnetic coupling between the inductors. 9. The method of claim 8, Wherein the second inductor is positioned within a distance d1 from the first inductor and the constant distance is selected to induce an electromagnetic coupling between the first inductor and the second inductor. 9. The method of claim 8, Wherein the third inductor is located within a first distance d2 from the first inductor and a second distance d4 from the second inductor such that the first distance and the second distance are greater than the first inductor, A band-pass filter selected to induce an electromagnetic coupling between the inductor and the third inductor. 9. The method of claim 8, Wherein the first inductor, the second inductor, and the third inductor comprise a thin conductive material, and wherein the first capacitor, the second capacitor, and the third capacitor comprise a thin dielectric material. 9. The method of claim 8, Wherein the first inductor and the second inductor are coplanar and overlap with the third inductor. 9. The method of claim 8, Wherein the first inductor is positioned non-overlapping with the second inductor and the third inductor is positioned non-overlappingly around the first and second inductors. 9. The method of claim 8, Further comprising a substrate on which the first inductor, the second inductor, and the third inductor, and the first capacitor, the second capacitor, and the third capacitor are integrated. An LC resonator circuit comprising a first interconnect terminal, a second interconnect terminal, a third interconnect terminal, and a fourth interconnect terminal, A first inductor including a first end terminal and a second end terminal respectively connected to the first interconnection terminal and the second interconnection terminal; A first capacitor connected between the first end terminal and the second end terminal of the first inductor; And a first portion of a second inductor parallel to the first portion adjacent to the second inductor of the first inductor, wherein the first and second end terminals of the second inductor comprise a first inductor and a second inductor, A third inductor connected to the third interconnection terminal and the fourth interconnection terminal, respectively; A second capacitor connected between the first end terminal and the second end terminal of the second inductor; A first portion of the third inductor in parallel with the second portion adjacent to the third inductor of the first inductor and a second portion adjacent to the third inductor of the second inductor, A third inductor including a second portion of the third inductor and positioned adjacent to the first inductor and the second inductor to induce electromagnetic coupling between the first inductor and the second inductor; And a third capacitor connected between the first end terminal and the second end terminal of the third inductor. delete delete delete 16. The method of claim 15, Wherein the first inductor is positioned non-overlapping with the second inductor and the third inductor is positioned non-overlapping around the first inductor and the second inductor. delete delete delete delete delete delete delete delete delete delete delete delete

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