KR101646501B1 - Semiconductor package having lid - Google Patents

Semiconductor package having lid Download PDF

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Publication number
KR101646501B1
KR101646501B1 KR1020150043994A KR20150043994A KR101646501B1 KR 101646501 B1 KR101646501 B1 KR 101646501B1 KR 1020150043994 A KR1020150043994 A KR 1020150043994A KR 20150043994 A KR20150043994 A KR 20150043994A KR 101646501 B1 KR101646501 B1 KR 101646501B1
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KR
South Korea
Prior art keywords
opening
insulating layer
substrate
conductive
lead
Prior art date
Application number
KR1020150043994A
Other languages
Korean (ko)
Inventor
정구웅
김병진
신민철
이재웅
임호정
Original Assignee
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020150043994A priority Critical patent/KR101646501B1/en
Application granted granted Critical
Publication of KR101646501B1 publication Critical patent/KR101646501B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a semiconductor package having a lead, and more particularly, to a semiconductor package having a lead, wherein the frame laminate structure of the substrate to which the leg portion of the lead is attached is improved to secure a space for conductive pattern routing of the substrate, To a semiconductor package having a lead.
That is, according to the present invention, a second insulating layer is formed on the edge region of the substrate and a second opening having a larger size is formed in the second insulating layer as compared with a conventional opening, And to provide a semiconductor package having a lead that can be accurately matched to and adhered to a conductive adhesive means filled in two openings.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor package having leads,

The present invention relates to a semiconductor package having a lead, and more particularly, to a semiconductor package having a lead, wherein the frame laminate structure of the substrate to which the leg portion of the lead is attached is improved to secure a space for conductive pattern routing of the substrate, To a semiconductor package having a lead.

In spite of the high integration and high performance of the semiconductor package, research for making the semiconductor package more compact has been continuously carried out. As a result, a conductive bump is formed between the bonding pad of the semiconductor chip and the conductive pattern of the substrate, Semiconductor packages are manufactured to be electrically connected through a medium. As a representative example, a flip chip ball grid array (FCBGA) package, a wafer level chip size / scale package (WLCSP) And the like.

Further, in addition to the miniaturization trend of the semiconductor package, since a lot of heat is generated during operation of the semiconductor chip, the heat dissipation performance of the semiconductor package is improved by combining heat dissipating means such as a heat spreader.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a conventional semiconductor package in which a semiconductor chip and a substrate are connected to a conductive bump together with leads for heat dissipation and ground.

1, reference numeral 10 denotes a printed circuit board (PCB), and reference numeral 20 denotes a semiconductor chip.

First, the semiconductor chip 20 is attached to the central region of the upper surface of the substrate 10 so as to exchange electric signals.

The conductive pattern for chip connection and the bonding pads of the semiconductor chip 20 exposed through the central region of the top surface of the substrate 10 are electrically connected to each other via the conductive bumps 22, The semiconductor chip 20 is attached to the semiconductor chip 20.

Subsequently, the underfill material 24 is filled between the substrate 10 and the semiconductor chip 10.

More specifically, the substrate 10 and the semiconductor chip 10 are spaced apart from each other with the conductive bump 22 interposed therebetween. An underfill material such as epoxy or the like The filled underfill material 24 surrounds the conductive bumps 22 to insulate the conductive bumps 22 from each other and maintains the durability of the conductive bumps 22.

A lead 30 for protecting the semiconductor chip is attached to the upper surface of the semiconductor chip 20 through an adhesive means. The lead 30 is attached to the upper surface of the semiconductor chip 20 A flat plate portion 32, and a leg portion 34 attached to the upper surface of the substrate 10.

Thus, the flat plate portion 32 of the lead 30 is attached via a bonding means such as a resin-based thermal interface material (TIM), and the leg portion 34 of the lead 30 is electrically connected to the conductive epoxy To the upper surface of the substrate 10 via an adhesive means such as a soldering material.

Finally, the input / output terminal 12 such as a solder ball is fused to the borland 19 formed on the bottom surface of the substrate 10 to complete the semiconductor package having leads.

Such a conventional flip chip ball grid array type package having a lead is removed from the conventional wire bonding method and the semiconductor chip and the substrate are connected to the conductive bump so that the electrical connection distance between the semiconductor chip and the substrate is shortened, And thus it is possible to realize the miniaturization of the package.

On the other hand, the lead shields the electromagnetic wave and functions to ground the electromagnetic wave through the substrate.

Here, the connection structure for the ground between the lead and the substrate will be described with reference to an enlarged view of FIG.

The conductive pattern 13 for routing and the conductive pattern 13 for routing which are connected to the via hole 14 in a conductive manner are formed on the resin layer which is the core layer of the substrate 10 And an insulating layer 15 such as a solder resist is coated on the conductive pattern 13 for routing.

An opening 16 of a predetermined size to which the insulating layer 15 is not applied is formed at a position where the leg portion 34 of the lead 30 is attached. A separate ground metal 17 is formed to fit the size of the opening 16.

The opening 16 is filled with a conductive adhesive 18 such as a conductive epoxy to which the leg 34 of the lid 30 is attached so that the leg 34 of the lid 30 contacts the substrate 10 And is adhered and fixed by the conductive adhesive means 18.

Therefore, the lead 30 is grounded by the conductive bonding means 18 and the ground metal 17 in the opening 16 of the substrate 10 through the leg portion 34 as well as the heat releasing function of the semiconductor chip It plays a role.

However, the above-described conventional semiconductor package having a lead has the following problems.

First, there is a problem that the semiconductor package size depends on the size of the opening of the substrate and the size of the ground metal.

That is, the leads 30 having different sizes of the leads 30, that is, the legs 34 of different width sizes, should be attached to the substrate 10 according to the size of the semiconductor package, Since the size of the semiconductor package 16 and the ground metal 17 are constantly determined irrespective of the size of the semiconductor package, there is a limitation in forming the semiconductor package size as desired.

Secondly, as the size of the opening 16 and the ground metal 17 formed in the edge region of the substrate 10 is fixed to a predetermined size, the degree of freedom in the routing design for forming the conductive pattern in the edge region of the substrate is decreased There is a problem.

Thirdly, when the leg portion 34 of the lead 30 is attached to the upper surface rim of the substrate 10 by pressing the conductive bonding means 18, the conductive bonding means 18 is pressed by the pressing force of the leg portion 34 There is a problem that it is escaped to the outside through a gap between the substrate 10 and the leg portion 34 to cause contamination.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a second insulating layer is further formed on an insulating layer in a peripheral region of a substrate, 2 openings so that the legs of the leads having different width sizes can be precisely matched and adhered to the conductive adhesive means filled in the second openings.

Another object of the present invention is to improve the degree of freedom in designing conductive pattern routing with respect to the edge region of the substrate by greatly reducing the size of the existing opening and the size of the ground metal formed in the edge region of the substrate.

It is still another object of the present invention to provide a method of manufacturing a semiconductor device in which a trench is further formed on the inner and outer portions of a second insulating layer formed on a rim portion of a substrate and when a leg portion of the lead is adhered to an upper surface rim of the substrate, Is accommodated in the trench so that the conductive adhesive means can be easily prevented from escaping to the outside.

According to an aspect of the present invention, there is provided a conductive pattern for routing comprising: a conductive pattern for routing that is plated on a resin layer; an insulating layer that covers the conductive pattern for routing; an opening formed in the insulating layer; And a ground metal formed underneath the opening, the ground metal being coplanar with the conductive pattern for routing; A semiconductor chip attached to a central region of an upper surface of the substrate; A lead that is groundably attached to a conductive adhesive means that is filled in the opening of the substrate in contact with the semiconductor chip; Wherein a second insulating layer is laminated on the insulating layer in the edge region of the substrate and a second opening is formed in the second insulating layer with a larger size than the opening, Wherein the semiconductor package is filled with a conductive adhesive means that is attached to the semiconductor chip so as to be able to be grounded.

Preferably, the second opening is formed as an independent space communicating with the opening while being equally spaced along the four-sided edge region of the substrate.

More preferably, a shield groove for shielding electromagnetic waves is further formed between the second opening and the second opening of the second insulating layer.

In addition, the shield groove is filled with a conductive adhesive means filled in the second opening.

In particular, trenches are formed at the inner and outer positions of the second insulating layer at the positions where the second openings are formed to accommodate the conductive adhesive means that escape to the outside.

Preferably, as the second opening is formed in the second insulating layer, the opening size and the size of the ground metal immediately below are minimized, thereby further securing a design space of the conductive pattern for routing.

Through the above-mentioned means for solving the problems, the present invention provides the following effects.

First, a second insulating layer is further laminated on the insulating layer in the edge region of the substrate, and a second opening of a larger size is formed in the second insulating layer as compared with the opening formed in the existing insulating layer, And the size of the ground metal can be reduced.

Secondly, since the leg portions of the leads are adhered to each other in the conductive adhesive means filled in the second opening, the size of the existing opening and the size of the ground metal formed in the edge region of the substrate can be minimized, It is possible to secure a space for forming the conductive pattern in the secured space, thereby improving the degree of freedom in designing the conductive pattern routing.

Third, when a trench is further formed on the inner and outer portions of the second insulating layer formed on the substrate, and the leg portion of the lead is attached by pressing the conductive bonding means, the conductive bonding means is received in the trench, It can be easily prevented from going out.

1 is a cross-sectional view of a conventional semiconductor package,
2 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention,
3 and 4 are plan views showing a semiconductor package according to the first embodiment of the present invention,
5 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

2 is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention, and FIGS. 3 and 4 are plan views thereof.

As described above, the conductive pattern for chip connection exposed through the central region of the upper surface of the substrate 10 and the bonding pads of the semiconductor chip 20 are electrically connected to each other via the conductive bumps 22 so as to be electrically exchangeable, (20) is attached to the semiconductor chip (10).

At this time, the substrate 10 and the semiconductor chip 10 are spaced apart from each other with the conductive bump 22 interposed therebetween. An underfill material 24 such as epoxy is filled in the spaced space by an underfilling process And the filled underfill material 24 surrounds and insulates the respective conductive bumps 22 to maintain the durability of the conductive bumps 22.

A lead 30 for protecting the semiconductor chip is attached to the upper surface of the semiconductor chip 20 through an adhesive means. The lead 30 is attached to the upper surface of the semiconductor chip 20, And a leg portion 34 attached to the upper surface of the substrate 10. The leg portion 34 is formed on the upper surface of the substrate 10,

Thus, the flat plate portion 32 of the lead 30 is attached via a bonding means such as a resin-based thermal interface material (TIM), and the leg portion 34 of the lead 30 is electrically connected to the conductive epoxy To the upper surface of the substrate 10 via an adhesive means such as a metal plate.

Finally, the input / output terminal 12 such as a solder ball is fused to the borland 19 formed on the bottom surface of the substrate 10 to complete the semiconductor package having leads.

Here, the frame structure for the lead and ground connection will be described with reference to an enlarged view of FIG.

The conductive pattern 13 for routing and the conductive pattern 13 for routing are connected to the via hole 14 and the conductive pattern 11 for chip connection are formed on the resin layer which is the core layer of the substrate 10 And an insulating layer 15 such as a solder resist is coated on the conductive pattern 13 for routing.

An opening 16 of a predetermined size to which the insulating layer 15 is not applied is formed at a position where the leg portion 34 of the lead 30 is attached. A separate ground metal 17 is formed to fit the size of the opening 16.

The insulating layer 15 is formed on the rim of the substrate 10 so as to cover the conductive patterns 13 for routing, the insulating layer 15 coated on the resin layer, The opening 16 and the ground metal 17 formed on the lower side of the opening 16 in the same plane as the conductive pattern 13 for routing are formed.

At this time, a second insulating layer 100 is further laminated on the insulating layer 15 in the edge region of the substrate 10, and the second insulating layer 100 has a larger size than the opening 16 The second opening 102 is formed and the second opening 102 and the opening 16 are vertically aligned to form a "T" shaped cross section.

A conductive adhesive means 18 such as a conductive epoxy is filled in the opening 16 and the second opening 102 so that the leg portion 34 of the lead 30 is attached to the leg portion 34 of the lead 30 34 are adhered and fixed by the conductive adhesive means 18 filled in the second opening 102 while being seated on the upper surface of the substrate 10.

The second insulating layer 100 is further laminated on the insulating layer 15 in the edge region of the substrate 10 and the opening 16 formed in the existing insulating layer 15 is formed in the second insulating layer 100, The size of the opening of the substrate and the size of the ground metal to be secured by filling the opening 16 and the second opening 102 with the conductive bonding means 18 after forming the second opening 102 of the larger size .

Preferably, the second opening 102 formed in the second insulating layer 100 is formed to minimize the size of the opening 16 and the ground metal 17 directly underneath, It is only necessary that the conductive bonding means 18 in the second opening 102 and the conductive bonding means 18 in the opening 16 are conductively connected to each other in a state where the opening 102 and the opening 16 are aligned up and down Because.

The size of the conventional opening 16 and the size of the ground metal 17 can be minimized so that the space occupied by the opening 16 and the ground metal 17 in the internal space of the substrate can be reduced, And the space occupied by the ground metal 17 can be utilized as a space for forming the conductive pattern 13 for routing, thereby improving the degree of freedom in designing the conductive pattern for routing.

In other words, since the leg portion 34 of the lead 30 is adhered to the edge portion of the substrate 10 by the conductive adhesive means 18 filled in the second opening 102, It is possible to minimize the size of the existing opening 16 and the size of the ground metal 17 and to secure a space for forming the conductive pattern 13 for routing in a space secured by the size reduction of the ground metal 17 Therefore, the degree of freedom of the conductive pattern routing design can be improved.

Of course, the lid 30 may be made of a conductive material, such as a conductive material, through the legs 34 and the conductive adhesive means 18 in the second opening 100 and the opening 16 of the substrate 10, The ground metal 17 is grounded.

3, the second openings 102 formed in the second insulating layer 100 are formed at equal intervals along the four-sided edge region of the substrate 10, Space.

Shielding grooves 104 for shielding electromagnetic waves are further formed between the second opening 102 and the second opening 102 of the second insulating layer 100 and the shielding grooves 104 are formed between the second opening 102 and the second opening 102, The second opening 102 and the second opening 102 are connected to each other. As shown in FIG. 4, the second opening 102 and the shielding groove 104 form a rectangular array of grooves.

Also, the shield groove 104 is filled with the conductive adhesive means 18 filled in the second opening 102.

The reason why the conductive adhesive means 18 is filled in the shield groove 104 by further forming the shield groove 104 between the second opening 102 and the second opening 102 is that the leg portion 104 of the lead 30 The electromagnetic wave is completely blocked from flowing into the semiconductor chip through the gap between the first insulating layer 34 and the second insulating layer 100.

That is, the conductive adhesive means 18 is filled in the second opening 102 and the shield groove 104 in a state in which the second opening 102 and the shielding groove 104 form a rectangular ring-type groove arrangement The area of the leg 30 of the lead 30 adhered to the conductive adhesive means 18 is increased so that the adhesion of the lead to the leg 34 can be increased, The gap between the portion 34 and the second insulating layer 100 is completely sealed by the conductive adhesive means 18 so that the electromagnetic wave can be completely blocked from flowing into the semiconductor chip.

Second Embodiment

5 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention.

The second embodiment of the present invention has the same structure as that of the first embodiment described above and is further characterized in that the structure for preventing the conductive adhesive means 18 from escaping to the outside is further formed.

5, a trench 106 (shown in FIG. 5) for receiving a conductive bonding means 18 that escapes to the inside and outside of the second opening 102 of the second insulating layer 100 at a position where the second opening 102 is formed, Is formed.

When the leg portion 34 of the lead 30 is attached to the upper surface of the substrate 10 by pressing the conductive adhesive means 18 filled in the second opening 102, The trench 106 allows the conductive adhesive means 18 to move outwardly through the gap between the substrate 10 and the leg portion 34 by the pressing force of the leg portion 34, It is possible to prevent a problem of contaminating the side of the package by flowing out to the outside through the space between the leg portion 34 of the package 10 and the substrate 10.

10: substrate
11: Conductive pattern for chip connection
12: I / O terminal
13: Conductive pattern for routing
14:
15: Insulating layer
16: aperture
17: Ground metal
18: Conductive adhesive means
19: Borland
20: semiconductor chip
22: Conductive bump
24: underfill material
30: Lead
32:
34:
100: second insulating layer
102: second opening
104: Shield Home
106: trench

Claims (6)

An insulating layer coated with the conductive pattern for routing, an opening formed in the insulating layer, a conductive adhesive means for grounding filled in the opening, and a conductive pattern for grounding the conductive pattern for routing And a ground metal formed on the underside of the opening;
A semiconductor chip attached to a central region of an upper surface of the substrate;
A lead that is groundably attached to a conductive adhesive means that is filled in the opening of the substrate in contact with the semiconductor chip;
Lt; / RTI >
Depositing a second insulating layer on the insulating layer in the edge region of the substrate and forming a second opening in the second insulating layer having a larger size than the opening in the second insulating layer, Wherein the first and second openings are formed as independent spaces communicating with the openings while being equally spaced, and the openings and the second openings are filled with conductive adhesive means that are attached to the leads so as to be grounded.
delete The method according to claim 1,
And a shield groove for shielding electromagnetic waves is formed between the second opening and the second opening of the second insulating layer.
The method of claim 3,
Wherein the shield groove is filled with a conductive adhesive means to be filled in the second opening.
The method according to claim 1,
Wherein a trench for accommodating a conductive adhesive means that escapes to the outside is formed at a position where the second opening of the second insulating layer is formed at its inner and outer positions.
The method according to claim 1,
Wherein a size of the opening immediately below and a size of the ground metal are minimized as the second opening is formed in the second insulating layer so that a design space for a conductive pattern for routing can be further secured. .
KR1020150043994A 2015-03-30 2015-03-30 Semiconductor package having lid KR101646501B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110064471A (en) * 2009-12-08 2011-06-15 삼성전기주식회사 Package substrate and fabricating method of the same
KR20120053332A (en) * 2010-11-17 2012-05-25 삼성전자주식회사 Semiconductor package and method of forming the same
US20120306061A1 (en) * 2011-05-31 2012-12-06 Broadcom Corporation Apparatus and Method for Grounding an IC Package Lid for EMI Reduction
KR20140093503A (en) * 2013-01-18 2014-07-28 앰코 테크놀로지 코리아 주식회사 Semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110064471A (en) * 2009-12-08 2011-06-15 삼성전기주식회사 Package substrate and fabricating method of the same
KR20120053332A (en) * 2010-11-17 2012-05-25 삼성전자주식회사 Semiconductor package and method of forming the same
US20120306061A1 (en) * 2011-05-31 2012-12-06 Broadcom Corporation Apparatus and Method for Grounding an IC Package Lid for EMI Reduction
KR20140093503A (en) * 2013-01-18 2014-07-28 앰코 테크놀로지 코리아 주식회사 Semiconductor package

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