KR101645120B1 - Voltage controlled oscillator for realizing multi-phase - Google Patents

Abstract

A multiphase voltage controlled oscillator is disclosed in which the multiphase clock outputs have the same load. The voltage controlled oscillator includes a first oscillation unit, a second oscillation unit, a plurality of first filter units connected to the first oscillation unit, and a plurality of second filter units connected to the second oscillation unit. Here, the multiple clock outputs output from the oscillation units have the same load.

Description

[0001] VOLTAGE CONTROLLED OSCILLATOR FOR REALIZING MULTI-PHASE [0002]

The present invention relates to a multi-phase voltage controlled oscillator.

The multiphase voltage-controlled oscillator outputs multiple clocks, but the phase difference of the clocks is not uniform because the clock outputs do not have the same load. Therefore, although the voltage-controlled oscillator outputs multiple phases, practically only one phase has to be used. In this case, the voltage controlled oscillator should be designed to have a higher frequency output than when a multi-phase clock is available. As a result, the current consumption is increased and the desired operating frequency may not be realized due to process limitations.

Korean Patent Laid-Open Publication No. 2014-0117938 (Publication Date: October 8, 2014)

The present invention provides a multiphase voltage controlled oscillator in which the multiphase clock outputs have the same load.

In order to achieve the above object, according to one aspect, a multi-phase voltage controlled oscillator includes a first oscillation unit; A second oscillation unit connected to the first oscillation unit; A plurality of first filter units connected to the first oscillation unit; And a plurality of second filter units connected to the second oscillation unit. Here, the multi-phase clock outputs output from the oscillation units have the same load.

According to another aspect, a multi-phase voltage controlled oscillator comprises: a first oscillation unit having first inverters sequentially connected; A second oscillation unit having second inverters serially connected; And a first filter portion having first resistors connected to nodes between the first inverters and first filter paths connected to the first resistors. Here, the first filter path portions are not activated redundantly but are sequentially activated, and the first inverters and the second inverters have a ring structure. In the first filter portion, the first resistor and the first A first node between the filter path portions is connected to a second node between the second inverters of the second oscillation portion.

The multi-phase voltage controlled oscillator according to the present invention is designed so that the clock outputs have the same load while improving the phase noise, so that the phase difference of the clocks can be uniform. Thus, it is possible to use all of the multi-phase clocks and reduce the current consumption by lowering the output frequency.

FIG. 1 is a diagram schematically illustrating a concept of a voltage-controlled oscillator according to an embodiment of the present invention. Referring to FIG.
2 is a circuit diagram showing an inverter according to an embodiment of the present invention.
3 is a circuit diagram showing a multimode filter according to an embodiment of the present invention.
4 is a diagram illustrating an actual structure of a voltage-controlled oscillator according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator (VCO) that is used in a phase locked loop (PLL) or the like to generate a multiphase clock, and a voltage controlled oscillator do.

In particular, the voltage controlled oscillator of the present invention implements such that the clock outputs have the same load so that the phase difference of the clocks is uniform, so that all clocks are actually available. Thus, the output frequency of the voltage controlled oscillator can be lowered, and as a result, current consumption can be reduced.

In addition, when the clock generated by the voltage-controlled oscillator of the present invention is used for the transmitting / receiving end, the phase difference of the multi-phase clocks is uniform, so that faster data transmission is possible and BER reduction can be minimized.

In addition, the voltage controlled oscillator uses a multi-phase filter to reduce the phase noise of the clock, and as a result, the performance of the clock can be improved through the PLL using the voltage controlled oscillator.

Hereinafter, various embodiments of the voltage-controlled oscillator of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a voltage controlled oscillator according to an embodiment of the present invention, and FIG. 2 is a circuit diagram illustrating an inverter according to an embodiment of the present invention. Referring to FIG. 3 is a circuit diagram showing a multimode filter according to an embodiment of the present invention. However, the voltage controlled oscillator of FIG. 1 is a conceptual circuit diagram, and the actual implementation circuit is shown in FIG. For the sake of convenience, it is assumed that the voltage-controlled oscillator outputs eight clocks having different phases.

Referring to FIG. 1, the voltage controlled oscillator (VCO) of the present embodiment may include a first oscillation unit 100, a second oscillation unit 102, a phase difference unit 104, and filter units 110.

The first oscillation unit 100 may include four first inverters arranged in order to determine the output frequency, for example, to generate clocks having four different phases.

The second oscillation unit 102 may include four second inverters arranged in order to determine the output frequency, for example, to generate clocks having four different phases.

Although the inverters of the oscillation parts 100 and 102 are not shown in the ring structure in FIG. 1, they may have a ring structure as shown in FIG. 4, that is, they may be ring oscillators.

According to one embodiment, each inverter may be composed of a P-MOS transistor MP and an N-MOS transistor MN connected in series between a power supply voltage V _DD and a control voltage V _C. A control voltage V _C may be applied to the source and the body of the NMOS transistor MN. That is, the inverter may invert the input signal (IN) in response to a control voltage (V _C) outputs an output signal (OUT) to swing between the power supply voltage (V _DD) and a control voltage (V _c). At this time, the degree of delay of the inverter varies depending on the control voltage V _C , and as a result, the phase of the clock is controlled. Of course, the structure of the inverter and its control method can be variously modified.

The phase difference section 104 generates a phase difference, for example, a 180-degree phase difference between the oscillation sections 100 and 102, and may consist of latch pairs for differential circuit operation. For example, each pair of latches may be connected between nodes N0 to N3 between the inverters of the first oscillation section 100 and nodes N4 to N7 between the inverters of the second oscillation section 102. As a result, the clocks output from the first oscillation unit 100 and the clocks output from the second oscillation unit 102 may have a phase difference of 180 degrees.

On the other hand, since the oscillation parts 100 and 102 and the phase difference part 104 mainly determine the output frequency, they can be named as the main delay path.

As a multiphase filter path, the filter units 110 are connected to the nodes NO to N7 between the inverters of the oscillation units 100 and 102, respectively, and may be RC filters. Of course, the filter units 110 may be implemented as an LC filter, but it is preferable that the filter units 110 are RC filters in consideration of the filter size. Here, the filter units 110 may be band-pass filters to obtain a high-performance Q factor.

Each of the filter portions 110 corresponds to one phase, and each may include one resistor R and a plurality of filter path portions 120, 122, 124, and 126. The number of filter path portions of the filter portion 110 may be half of the number of clocks and may be equal to the number of inverters of the oscillation portion 100 or 102.

According to one embodiment, the filter units 110 may be connected to the nodes N0 to N7, respectively, and the structures of the filter units 110 may be the same. As a result, the clock outputs can have the same load, and thus the phase difference of the clocks can be uniform.

According to one embodiment, the filter path portions 120, 122, 124 and 126 may have the same structure and may include, for example, one capacitor (C1, C2, C3 or C4) have. Here, when the number of clocks is 2 ⁿ , the number of switches may be (n-1).

The first filter path unit 120 may include a switch S11 and S21 and a capacitor C1 that are connected to the resistor R to form a first path and sequentially connected. Here, the switches S11 and S21 can be controlled by the output clocks and can be turned on or off at the same time.

The second filter path portion 122 may include a switch S12 and a capacitor S22 and a capacitor C2 connected in series to the resistor R to form a second path. Here, the switches S12 and S22 can be controlled by the output clocks, and can be turned on or off at the same time.

The third filter path portion 124 may include a switch S13 and S23 and a capacitor C3 that are connected to the resistor R to form a third path and sequentially connected. Here, the switches S13 and S23 can be controlled by the output clocks, and can be turned on or off at the same time.

The fourth filter path portion 126 may be connected to the resistor R to form a fourth path and may include switches S14 and S24 and a capacitor C4 that are sequentially connected. Here, the switches S14 and S24 can be controlled by the output clocks and can be turned on or off at the same time.

According to one embodiment, the first path, the second path, the third path, and the fourth path are not activated redundantly but can be activated sequentially. For example, when the first path is activated, the second path through the fourth path are not activated, and when the second path is activated, the first path, the third path, and the fourth path may not be activated.

The switches S11 to S24 can be controlled by the output clocks (< 0 > to < 7 >) so that this operation is possible. Specifically, the switches S11 and S21 of the first path are respectively connected to the clock (phi <0>) output from the first oscillation unit 100 and the clock (phi <5>) output from the second oscillation unit 102, And the switches S12 and S22 of the second path may be controlled by the clocks? <2> output from the first oscillation unit 100 and the clocks? <2> output from the second oscillation unit 102, 7 &gt;).

The switches S13 and S23 in the third path are respectively connected to the clocks? <4> output from the first oscillation unit 100 and the clocks? <1> output from the second oscillation unit 102 And the switches S14 and S24 of the fourth path are controlled by the clock φ <6> output from the first oscillation unit 100 and the clock φ <3> output from the second oscillation unit 102, ). &Lt; / RTI &gt;

However, the method of controlling the switches S11 to S24 may be variously modified as long as the first to fourth paths are not activated redundantly, and it is obvious to those skilled in the art that such a modification belongs to the scope of the present invention It will be obvious. For example, in the above, although the switches S11 to S24 are controlled by the clocks (phi <0> to phi <7>), they may be controlled by the control signals output from the external control unit .

According to one embodiment, the specific filter path portions of each filter portion 110-0 to 110-7 may be activated at the same time, and the remaining filter path portions may not be activated. That is, when the first path portions are activated, the second path portions through the fourth path portions may not be activated.

In summary, the voltage-controlled oscillator of the present embodiment includes the multi-phase filter units 110 to remove the phase noise, and the filter units 110-0 to 110-7 are implemented in the same structure so that the clock outputs have the same load . Therefore, the phase difference of the clocks can be uniform.

Particularly, the first to fourth paths of the filter unit 110 may be activated one by one without being activated redundantly.

4 is a diagram illustrating an actual structure of a voltage-controlled oscillator according to an embodiment of the present invention. However, detailed description of the components shown in FIG. 1 among the components shown in FIG. 4 will be omitted.

4, the nodes N10 to N17 are connected to the nodes N0 to N7 through a corresponding inverter and a resistor R, and each of the nodes N10 to N17 is connected to the filter path portions 400, 402, 404, and 406 are formed.

The filter path portions 400, 404, 404, and 406 correspond respectively to the filter path portions 120, 122, 124, and 126 of the filter portion 110 of FIG. That is, the first to fourth paths are formed in the nodes N10 to N17, respectively, and the first to the fourth paths may be sequentially activated without being activated redundantly.

According to one embodiment, the filter path portions 400, 404, 404, and 406 may all have the same structure (e.g., the circuit shown in FIG. 3) 406 may be activated sequentially without being activated redundantly.

4, the node N16 is connected to the node N0 between the inverters of the first oscillation section via the inverter B0, and the node N17 is connected to the inverter N11 of the first oscillation section via the inverter B1, Lt; RTI ID = 0.0 &gt; N1. &Lt; / RTI &gt; The node N12 is connected to the node N4 between the inverters of the second oscillation section via the inverter B4 and the node N13 is connected to the node N12 between the inverters of the second oscillation section via the inverter B5 N5. That is, the first oscillation unit and the second oscillation unit can be interconnected, and as a result, the signal of the filtered first oscillation unit can be provided to the second oscillation unit, and the signal of the filtered second oscillation unit can be provided to the first oscillation unit.

The node N10 is connected to the node N2 between the inverters of the first oscillation section via the inverter B2 and the node N11 is connected to the node N3 between the inverters of the first oscillation section via the inverter B3, Lt; / RTI &gt; Further, the node N14 is connected to the node N6 between the inverters of the second oscillation section via the inverter B6, and the node N15 is connected to the node N15 between the inverters of the second oscillation section via the inverter B7 N7.

At this time, the inverters B0 to B7 may serve to inject the filtered clock to nodes between the inverters of the corresponding oscillation part.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

100: first oscillation section 102: second oscillation section
104: phase difference section 110: filter section
120, 122, 124, 126:

Claims (13)

A first oscillating portion;
A second oscillation unit connected to the first oscillation unit;
A plurality of first filter units connected to the first oscillation unit; And
And a plurality of second filter units connected to the second oscillation unit,
Wherein at least one of the first filter units and the second filter units includes a plurality of filter path units and the filter path units have the same structure Characterized by a multiphase voltage controlled oscillator. The method of claim 1, wherein the first oscillation unit includes first inverters sequentially connected to each other, the second oscillation unit includes second inverters sequentially connected to each other, and the first filter units are respectively connected between the first inverters Nodes, the second filter portions being each connected to nodes between the second inverters,
Wherein the first filter portions and the second filter portions each include a resistor and a plurality of filter path portions. 3. The apparatus of claim 2, wherein the filter path portions each include (n-1) switches and a capacitor connected in series to one of the switches,
Wherein the switches are controlled by clocks output from the first oscillation unit and the second oscillation unit, and the number of clocks is 2 &^lt; ^{n &gt};. 4. The multi-phase voltage controlled oscillator of claim 3, wherein the filter path portions are sequentially activated without being redundantly activated. The method of claim 3, wherein the switches of the particular filter path portion are turned on or off simultaneously, and the switches of the remaining filter path portions except for the specified filter path portion are turned off when the switches of the particular filter path portion are turned on. Voltage controlled oscillator. 3. The method of claim 2, wherein all of the filter units have the same circuit structure, and a first node between the resistor and the corresponding filter path units in a specific first filter unit is connected to a second node between the second inverters of the second oscillation unit. And a third node between the resistor and the corresponding filter path units in a specific second filter unit is connected to the fourth node between the first inverters of the first oscillation unit via the corresponding third inverter, Wherein the first and second voltage-controlled oscillators are connected to each other through a second resistor. [7] The method as claimed in claim 6, wherein, in some of the first filter units, the resistor and the fifth node between the corresponding filter path units are connected to the sixth node between the first inverters of the first oscillation unit via the corresponding third inverter And a seventh node between the resistor and the corresponding filter path part is connected to the eighth node between the second inverters of the second oscillation part via the corresponding third inverter in some of the second filter parts. A multi-phase voltage controlled oscillator. 3. The method of claim 2,
Further comprising latch pairs coupled between nodes between the first interverters of the first oscillation unit and nodes between the second inverters of the second oscillation unit,
Wherein the clock output from the first oscillation unit and the clock output from the second oscillation unit are 180 degrees out of phase due to the latch pairs. 3. The multi-phase voltage controlled oscillator of claim 2, wherein the first inverters and the second inverters have a ring structure. A first oscillation unit having first inverters connected in series;
A second oscillation unit having second inverters serially connected; And
A first filter having a first resistor connected to a node between the first inverters and first filter paths connected to the first resistor,
Wherein the first filter path portions are activated in sequence without being activated redundantly, the first inverters and the second inverters have a ring structure, and the first filter portion and the first filter path And a first node between the first and second oscillation units is connected to a second node between the second inverters of the second oscillation unit. 11. The method of claim 10,
Further comprising a second filter portion having a second resistor connected to a node between the second inverters and second filter path portions connected to the second resistor,
Wherein the filter portions all have the same circuit structure, and the filter path portions each include (n-1) switches and a capacitor connected in series to one of the switches,
Wherein the switches are controlled by clocks output from the first oscillation unit and the second oscillation unit, and the number of clocks is 2 &^lt; ^{n &gt};. 12. The method of claim 11, wherein a third node between the second resistor and the second filter path portions in the second filter portion is connected to a third node between the first inverters of the first oscillator, And wherein the phase-locked loop is connected to the output of the multi-phase voltage controlled oscillator. 11. The method of claim 10,
Further comprising latch pairs coupled between nodes between the first interverters of the first oscillation unit and nodes between the second inverters of the second oscillation unit,
Wherein the clock output from the first oscillation unit and the clock output from the second oscillation unit are 180 degrees out of phase due to the latch pairs.

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