KR101644712B1 - Error correcting methods and circuit for improving block-wise concatenated bch codes - Google Patents

Abstract

The decoding method according to an embodiment includes dividing a message into blocks and arranging the divided message blocks in two-dimensional form composed of rows and columns; Generates a block unit concatenated BCH code for protecting the message in the two-dimensionally arranged message block, and stores an SPC block by adding a single parity check (SPC) code to the inside or outside of the block unit concatenated BCH code step; Performing a first decoding of the block-based concatenated BCH code as an error occurs; And performing a second decoding of the block-based concatenated BCH code to correct an error remaining in a parity part of the block-based concatenated BCH code that has undergone the first decoding.

Description

Technical Field [0001] The present invention relates to an error correction method and a decoding method for improving the performance of a block-based concatenated BC code,

The following description relates to a decoding method of a block-unit concatenated BCH code and an error correction method of a memory device using the same.

Block - based concatenated BCH codes have been proposed for areas such as memory requiring very low error rates. It is known that block - based concatenated BCH codes have a trade - off relationship between performance and error floor. Therefore, it is important to solve the error floor problem to improve the performance of the block - based concatenated BCH code.

The error floor of the block unit concatenated BCH code is caused by the patterned error. In order to solve the patterned error problem, a simple method of using an external call has been proposed. However, a method for solving the conventional error problem has been improved And the like.

The present invention can provide an error correction method for improving the performance of a block-based concatenated BC code according to an embodiment.

The present invention can provide a decoder of a block-based concatenated BC code according to an embodiment.

The decoding method according to an embodiment includes dividing a message into blocks and arranging the divided message blocks in two-dimensional form composed of rows and columns; Generates a block unit concatenated BCH code for protecting the message in the two-dimensionally arranged message block, and stores an SPC block by adding a single parity check (SPC) code to the inside or outside of the block unit concatenated BCH code step; Performing a first decoding of the block-based concatenated BCH code as an error occurs; And performing a second decoding of the block-based concatenated BCH code to correct an error remaining in a parity part of the block-based concatenated BCH code that has undergone the first decoding.

According to an aspect of the present invention, performing the second decoding of the block BCH code to correct an error remaining in a parity part of the block-based concatenated BCH code that has performed the first decoding may include error correction through SPC And decoding the block-based concatenated BCH code with an error pattern.

According to another aspect of the present invention, performing the second decoding of the block-based concatenated BCH code to correct an error remaining in the parity part of the block-based concatenated BCH code that has performed the first decoding may include: Receiving error information through a sum of a plurality of error-occurred message blocks; And performing decoding using error information of a plurality of message blocks in which the error has occurred.

According to another aspect of the present invention, performing the second decoding of the block-based concatenated BCH code to correct an error remaining in the parity part of the block-based concatenated BCH code that has performed the first decoding may include: And performing decoding of the block-based concatenated BCH code from a plurality of message blocks including the minimized error information.

According to another aspect of the present invention, performing the second decoding of the block unit concatenated BCH code to correct an error remaining in the parity part of the block-based concatenated BCH code that has performed the first decoding may include: And performing Chase decoding through the SPC block including position information of a plurality of message blocks.

According to another aspect of the present invention, a block-based concatenated BCH code for protecting the message in the two-dimensionally arranged message block is generated, and a single parity check (SPC) code is added to the inside or the outside of the block- Wherein the step of storing the SPC block comprises the steps of performing the coding of the SPC code and the coding of the block unit concatenated BCH code in parallel or the coding of the SPC code after performing the coding of the block unit concatenated BCH code And performing the method of any one of the following methods.

According to another aspect of the present invention, a block-based concatenated BCH code for protecting the message in the two-dimensionally arranged message block is generated, and a single parity check (SPC) code is added to the inside or the outside of the block- And storing the SPC block may include generating the SPC block through an XOR sum of the message blocks divided in units of blocks.

According to another aspect of the present invention, a block-based concatenated BCH code for protecting the message in the two-dimensionally arranged message block is generated, and a single parity check (SPC) code is added to the inside or the outside of the block- And storing the SPC block may include adjusting a size of the SPC block added to the inside or the outside of the block unit concatenated BCH code.

The decoder according to one embodiment includes a layout unit that divides a message into blocks and arranges the divided message blocks in a two-dimensional array composed of rows and columns; Generates a block unit concatenated BCH code for protecting the message in the two-dimensionally arranged message block, and stores an SPC block by adding a single parity check (SPC) code to the inside or outside of the block unit concatenated BCH code A BC-BCH code generation unit; A first decoding unit which performs a first decoding of the block-based concatenated BCH code as an error occurs; And a second decoding unit for performing a second decoding of the block-based concatenated BCH code to correct an error remaining in a parity part of the block-based concatenated BCH code that has undergone the first decoding.

According to one aspect of the present invention, the second decoder can decode the block-based concatenated BCH code with an error pattern capable of error correction through the SPC.

According to another aspect of the present invention, the second decoder receives error information through a sum of a plurality of message blocks in which an error has occurred from the SPC block, and performs decoding using error information of a plurality of message blocks in which the error occurred can do.

According to another aspect of the present invention, the second decoder may perform the first decoding to decode the block-based concatenated BCH code from a plurality of message blocks including the minimized error information.

According to another aspect of the present invention, the second decoding unit may perform Chase decoding through the SPC block including positional information of a plurality of error-occurred message blocks.

According to another aspect of the present invention, the BC-BCH code generation unit may perform the encoding of the SPC code and the encoding of the block-unit concatenated BCH code in parallel or the encoding of the block-based concatenated BCH code, Encoding of the code can be performed.

According to another aspect of the present invention, the BC-BCH code generator may generate an SPC block by XORing the last message blocks among the message blocks divided in units of blocks.

According to another aspect of the present invention, the BC-BCH code generator may adjust the size of the SPC block added to the inside or the outside of the block-unit concatenated BCH code.

The decoder according to an exemplary embodiment can adjust the size of an SPC block according to a desired performance by adopting a method of adding an SPC to a block-unit concatenated BCH code, thereby reducing parity usage and improving performance. Can be solved.

The decoder according to an embodiment of the present invention can identify the location of an error through the sum of SPCs and improve the performance of a block-based concatenated BCH code through Chase decoding.

1 is a block diagram illustrating a configuration of a decoder according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a structure of a block-unit concatenated BCH code, which is an embodiment of a block-unit concatenated BCH code technique on which the present invention is based.
3 is a diagram illustrating a structure of a code according to an embodiment.
4 is a diagram illustrating a case where a patterned error occurs according to an embodiment.
FIG. 5 illustrates a situation in which two error patterns generated by adding SPC information to one message block among the message blocks including a patterned error according to an embodiment are unified in a pattern with a small error.
6 is a flowchart illustrating a decoding method of a decoder according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating performance improvement of a decoder according to an embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a decoder according to an embodiment of the present invention.

The decoder 100 is an apparatus for decoding a coded message and may include a placement unit 110, an execution unit 120, an SPC block storage unit 130, and a decryption unit 140.

The arrangement unit 110 may divide the message into blocks and arrange the divided message blocks in two dimensions. At this time, the divided message block may be composed of two dimensions including rows and columns.

The BC-BCH code generation unit 120 can generate a block-unit concatenated BCH code for protecting a message in a two-dimensionally arranged message block, and generate a single parity (SPC) code inside or outside the generated block- Check) code to the SPC block. The BC-BCH code generation unit 120 performs a method of performing encoding of an SPC code and encoding of a block-unit concatenated BCH code in parallel, or a method of encoding an SPC code after performing encoding of a block-unit concatenated BCH code Either method can be performed. In this case, the BC-BCH code generator 120 can generate an SPC block by XORing the message blocks divided on a block basis, and adjust the size of the SPC block added to the inside or the outside of the block-unit concatenated BCH code .

The first decoding unit 130 may perform the first decoding of the block-based concatenated BCH code as the error occurs.

The second decoding unit 140 may perform the second decoding of the block unit concatenated BCH code to correct an error remaining in the parity part of the block unit concatenated BCH code that has performed the first decoding. The second decoding unit 140 can decode the block-based concatenated BCH code with an error pattern capable of error correction through the SPC.

The second decoder 140 receives error information through a sum of a plurality of message blocks in which an error has occurred from the SPC block, and can perform decoding using error information of a plurality of error-occurred message blocks. The second decoding unit 140 may perform the first decoding to decode the block-based concatenated BCH code from the plurality of message blocks including the minimized error information.

The second decoding unit 140 can perform Chase decoding through the SPC block including the location information of a plurality of message blocks in which an error occurs. At this time, the Chase decoding means a technique of reversing the bits determined to be error locations and then performing decoding again.

FIG. 2 is a diagram illustrating a structure of a block-unit concatenated BCH code, which is an embodiment of a block-unit concatenated BCH code technique on which the present invention is based.

개로 나뉘어 메시지 블록

와 같이 2차원으로 배치한 뒤, 각 행, 각 열을 BCH 부호를 통해 메시지를 보호하는 부호를 블록 단위 연접 BCH 부호(Block-Wise Concatenated BCH Codes)라고 한다.The block unit concatenated BCH code can be expressed as shown in FIG. That is, the message to be encoded is

Message block

, And a code for protecting a message through each BCH code for each row and each column is called a block-wise concatenated BCH code (BCH code).

Blocks denoted by R in FIG. 2 show the parity of a BCH code. In this case, a block generated by XOR summing of message blocks inside a block-unit concatenated BCH code is called a single parity check (SPC) block.

The dominant error pattern that forms the error floor of the block-unit concatenated BCH code is the (1, 1) error pattern generated by failure of decoding one row code and one column code. For example, when the decoding of the remaining codes succeeds and the decoding of the second row code and the second column code fails, it can be determined that an error remains only in the hatched area to the right. At this time, if the last block is generated by the XOR sum of the remaining message blocks, B _2.2 can be restored to the sum of the remaining B blocks. This can improve error floor performance.

3 is a diagram illustrating a structure of a code according to an embodiment.

The structure of the proposed code can store the SPC block 310 outside the block unit concatenated BCH code generated through XOR sum using only a part of the block. The SPC code is stored outside the block-unit concatenated BCH code, and the size of the SPC block 310 is adjusted according to the desired performance. In addition, the proposed code structure may use only a part of the blocks to store the SPC block 310 in the block-unit concatenated BCH code through the XOR sum, and to change the size of the block-unit concatenated BCH SPC block 310. There may be a degree of freedom in the size of the SPC block and the location where the SPC is utilized in each block.

The encoder can process the SPC and block-unit concatenated BCH coding sequentially. In addition, the SPC code encoding and the block-unit concatenated BCH encoding may be performed in parallel without sequentially processing. At this time, either the method of processing the SPC code and the encoding of the block unit concatenated BCH code in parallel, or the method of performing the encoding of the SPC code after performing the coding of the block unit concatenated BCH code . The encoded message can be generated by performing the SPC code encoding and the block-based concatenated BCH encoding sequentially or in parallel.

By adjusting the amount of parity used as the SPC through the structure of the code according to the embodiment, the parity can be utilized more efficiently according to the target performance.

The decoder not only partially corrects the (1, 1) error but also decodes the block-based concatenated BCH code after SPC decoding because it stores the SPC block externally.

4 is a diagram illustrating a case where a patterned error occurs according to an embodiment.

의 정보를 획득할 수 있다. 이때, 획득된

정보로부터 SPC 정보를

에 더할 수 있고 SPC 정보를

에 더할 수 있다. The decoder can remove (2, 1) or (1, 2) error patterns as well as (1, 1) errors. For example, suppose that the fourth column code of the second row and third row code fails to decode. Then, the decoder decodes the

Can be obtained. At this time,

SPC information from information

And SPC information.

.

에 더함으로써 생성된 패턴에 대하여 복호를 수행하고, SPC 정보를

에 더함으로써 생성된 패턴에 대하여 복호를 수행해봄으로써 최소화된 오류 패턴오류 패턴 중 더 적은 오류 정보를 가지고 있는 오류 패턴을 이용하여 다시 복호를 시도할 수 있다. SPC information

And decodes the generated SPC information.

It is possible to attempt decoding again using an error pattern having less error information among the minimized error pattern error patterns by performing decoding on the generated pattern.

FIG. 5 illustrates a situation in which two error patterns generated by adding SPC information to one message block among the message blocks including a patterned error according to an embodiment are unified in a pattern with a small error.

의 정보를 획득할 수 있고, 오류를 최소화하여 복호를 수행할 수 있다. The decoder can remove (2, 1) or (1, 2) error patterns as well as (1, 1) errors. For example, suppose that the fourth column code of the second row and third row code fails to decode. Then, the decoder decodes the

It is possible to acquire the information of the error, and to perform the decoding with minimizing the error.

정보로부터 SPC 정보를

에 더할 수 있고

에 더할 수 있다. SPC 정보를

에 더함으로써 생성된 패턴에 대하여 복호를 수행하고, SPC 정보를

에 더함으로써 생성된 패턴에 대하여 복호를 수행해봄으로써 최소화된 오류 패턴오류 패턴 중 더 적은 오류 정보를 가지고 있는 오류 패턴을 이용하여 다시 복호를 시도할 수 있다. At this time,

SPC information from information

Can add to

. SPC information

And decodes the generated SPC information.

It is possible to attempt decoding again using an error pattern having less error information among the minimized error pattern error patterns by performing decoding on the generated pattern.

이라고 하는 오류의 위치 정보를 갖고 있기 때문에 Chase 복호를 수행할 수 있다. 이때, Chase 복호는 오류의 위치라 판단되는 비트들을 반전시킨 뒤 다시 복호를 수행하는 기법을 의미할 수 있다. The decoder

It is possible to perform Chase decoding. At this time, the Chase decoding may be a technique of inverting bits determined to be error locations and then performing decoding again.

6 is a flowchart illustrating a decoding method of a decoder according to an embodiment of the present invention.

The decoding method can be performed by a decoder, and a decoder will be described with reference to FIGS. 1 to 5. FIG.

In step 610, the decoder may divide the message into blocks and arrange the divided message blocks into two-dimensional rows and columns.

In step 620, the decoder generates a block-unit concatenated BCH code for protecting a message in a two-dimensionally arranged message block, and stores an SPC block by adding an SPC code to the inside or the outside of the block-unit concatenated BCH code . The decoder can perform either the method of performing the coding of the SPC code and the coding of the block-unit concatenated BCH code in parallel, or the method of performing the coding of the block-unit concatenated BCH code and the coding of the SPC code have. The decoder can generate the SPC block by XORing the message blocks divided by the block unit and adjust the size of the SPC block added to the inside or the outside of the block unit concatenated BCH code.

In step 630, the decoder may perform the first decoding of the block-based concatenated BCH code as the error occurs.

In step 640, the decoder may perform a second decoding of the block-unit concatenated BCH code to correct an error remaining in the parity part of the block-unit concatenated BCH code that has performed the first decoding. The decoder can perform coding of a block-unit concatenated BCH code with an error pattern capable of error correction through the SPC.

The decoder receives error information through a sum of a plurality of message blocks in which an error has occurred from the SPC block, and can perform decoding using error information of a plurality of error-occurred message blocks. The decoder may perform the first decoding to decode the block-based concatenated BCH code from the plurality of message blocks including the minimized error information.

The decoder can perform Chase decoding through an SPC block including position information of a plurality of message blocks in which an error occurs.

FIG. 7 is a diagram illustrating performance improvement of a decoder according to an embodiment.

Since the decoder can adjust the amount of parity used as the SPC, the parity can be utilized more efficiently according to the target performance. In FIG. 7, assume that the coding rate is 0.93 and the message length is 8 KB. And the expected performance in the case where the individual constituent code is neglected to be decoded by another code is shown in a graph.

Through the graph, it is possible to compare the performance of each block by outputting the combination of the performance of the block-based concatenated BCH code, the error floor according to the existing method, the method of performing decoding from a plurality of message blocks including the minimized error information, have.

The decoder according to an exemplary embodiment may utilize a block-based concatenated BCH code in a field such as a memory requiring a very low error rate. At this time, since the performance of the block-based concatenated BCH code is related to the trade-off between the performance and the error floor, the error flooring problem can be solved more efficiently through the technique proposed in the present invention (for example, reduction in parity usage and improvement in performance). Thus, the performance of the block-based concatenated BCH code can be improved from the improved error floor.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (16)

Dividing a message into blocks, and arranging the divided message blocks in two-dimensionally composed of rows and columns;
Generates a block-based concatenated BCH codeword for protecting the message through the BCH code, and generates an SPC generated by XORing the message blocks divided in the block unit, (Single Parity Check) block inside or outside the block-based concatenated BCH codeword;
Performing a first decoding of the block-based concatenated BCH codeword when an error occurs; And
Performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword performing the first decoding;
Lt; / RTI >
Performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword that has performed the first decoding,
Receiving error information through a sum of a plurality of message blocks in which an error has occurred from the SPC block; And
Performing decoding using error information of a plurality of message blocks in which the error occurs;
. The method according to claim 1,
Performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword that has performed the first decoding,
Performing decoding of the block-based concatenated BCH codeword using the SPC code for the error pattern when an error pattern is generated
. delete The method according to claim 1,
Performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword that has performed the first decoding,
Performing decryption of the block-based concatenated BCH codeword from a plurality of message blocks including the minimized error information by performing the first decoding;
. Dividing a message into blocks, and arranging the divided message blocks in two-dimensionally composed of rows and columns;
Generates a block-based concatenated BCH codeword for protecting the message through the BCH code, and generates an SPC generated by XORing the message blocks divided in the block unit, (Single Parity Check) block inside or outside the block-based concatenated BCH codeword;
Performing a first decoding of the block-based concatenated BCH codeword when an error occurs; And
Performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword performing the first decoding;
Lt; / RTI >
Performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword that has performed the first decoding,
Performing Chase decoding through the SPC block including position information of a plurality of message blocks in which the error occurs;
. The method according to claim 1,
Generates a block-based concatenated BCH codeword for protecting the message through the BCH code, and generates an SPC generated by XORing the message blocks divided in the block unit, (Single Parity Check) block inside or outside the block-based concatenated BCH codeword,
A method of performing the encoding of the SPC code and the encoding of the block unit concatenated BCH codeword in parallel or a method of performing the encoding of the SPC code after performing the encoding of the block unit concatenated BCH codeword Steps to Perform
. delete The method according to claim 1,
Generates a block-based concatenated BCH codeword for protecting the message through the BCH code, and generates an SPC generated by XORing the message blocks divided in the block unit, (Single Parity Check) block inside or outside the block-based concatenated BCH codeword,
Adjusting a size of the SPC block added to the inside or the outside of the block-based concatenated BCH codeword
. A layout unit for dividing a message into blocks and arranging the divided message blocks in two dimensions composed of rows and columns;
Generates a block-based concatenated BCH codeword for protecting the message through the BCH code, and generates an SPC generated by XORing the message blocks divided in the block unit, A BC-BCH code generator for storing a Single Parity Check (BCCH) block inside or outside the block-based concatenated BCH codeword;
A first decoding unit for performing a first decoding of the block-based concatenated BCH codeword when an error occurs; And
A second decoding unit for performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword that has performed the first decoding,
Lt; / RTI >
Wherein the second decoding unit comprises:
Receiving error information through a sum of a plurality of message blocks in which an error occurs from the SPC block, and performing decoding using error information of a plurality of message blocks in which the error occurred. 10. The method of claim 9,
Wherein the second decoding unit comprises:
When an error pattern is generated, decodes the block-based concatenated BCH codeword using the SPC code for the error pattern
Decoder. delete 10. The method of claim 9,
Wherein the second decoding unit comprises:
And performs the first decoding to decode the block-based concatenated BCH codeword from a plurality of message blocks including the minimized error information
Decoder. A layout unit for dividing a message into blocks and arranging the divided message blocks in two dimensions composed of rows and columns;
Generates a block-based concatenated BCH codeword for protecting the message through the BCH code, and generates an SPC generated by XORing the message blocks divided in the block unit, A BC-BCH code generator for storing a Single Parity Check (BCCH) block inside or outside the block-based concatenated BCH codeword;
A first decoding unit for performing a first decoding of the block-based concatenated BCH codeword when an error occurs; And
A second decoding unit for performing a second decoding of the block-based concatenated BCH codeword to correct an error remaining in a parity part of the block-based concatenated BCH codeword that has performed the first decoding,
Lt; / RTI >
Wherein the second decoding unit comprises:
And performs a Chase decoding through the SPC block including position information of a plurality of message blocks in which the error occurs. 10. The method of claim 9,
Wherein the BC-BCH code generator comprises:
A method of performing the encoding of the SPC code and the encoding of the block unit concatenated BCH codeword in parallel or a method of performing the encoding of the SPC code after performing the encoding of the block unit concatenated BCH codeword A decoder to perform. delete 10. The method of claim 9,
Wherein the BC-BCH code generator comprises:
The size of the SPC block added to the inside or the outside of the block-based concatenated BCH codeword is adjusted
Decoder.

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