KR101636809B1 - Binary field reduction method for Elliptic Curve Cryptography - Google Patents

Abstract

The present invention relates to a binary field reduction method for elliptic curve cryptography (ECC). More preferably, the method comprises the steps of: allowing an input unit to receive a plurality of words, indicating the order of binary fields, from a memory unit and load the received words into a register; and allowing a reduction unit to performing reduction through an irreducible polynomial consisting of a trinomial or a pentanomial with respect to the words loaded into the register. By such a configuration, the binary field reduction method for ECC according to the present invention loads data stored in the memory into the register, and stores a result of reduction in the memory to minimize memory loads and storage and implement in an assembly language, thereby increasing a reduction improvement rate.

Description

{Binary field reduction method for Elliptic Curve Cryptography}

The present invention relates to a method of subtracting an elliptic curve cryptography binary, and more particularly, to a subtraction method of an elliptic curve cryptography binary that can efficiently subtract a binary value in an 8-bit ATmega 128 processor environment.

Due to the rapid increase of various electronic commerce, various cryptosystems have been widely studied not only in electronic commerce systems but also in security systems.

Among them, a public key cryptosystem (ECC) using an elliptic curve system is a public key cryptographic algorithm based on the disadvantage of discrete logarithm, and is a core technology of e-commerce following the RSA algorithm Has recently attracted attention. The elliptic curve cryptosystem based on the difficulty of discrete algebra is a kind of public key system together with DSA algorithm and RSA based on factorial decomposition. The ECC was first proposed in 1985 by N. Koblitz and V.S. Miller as an alternative to RSA encryption, and is currently being widely adopted by security systems and e-commerce solution providers.

In particular, the ECC has a feature that an existing public key algorithm is implemented using an elliptic curve, although a new public key cryptographic algorithm is not made at a finite position using an elliptic curve. More precisely, the ECC provides a mathematical place where a cryptographic algorithm can be implemented rather than a specific cryptographic algorithm, and it is possible to use algorithms such as RSA, Diffie-Hellman, Elgamal, To be implemented on non-elliptic curves. Cryptographic implementations on elliptic curves are much more robust than those implemented on integers of the same key size because of their mathematical complexity, so it is very likely that most of the future cryptographic algorithms will turn into ECC.

This elliptic curve cryptosystem is a system based on multiplicative group of finite fields and can design various cryptosystems and has a safe characteristic.

In particular, various elliptic curves that can provide a group can be utilized. That is, it is easy to design various cryptographic systems. Also, even if all users use the same base K, each user can select a different curve. That is, all users can use the same hardware to perform operations, and can periodically change the curve for additional security.

In order to investigate the theoretical safety of a public key cryptosystem, it is necessary to analyze how much it is necessary to solve the mathematical problem underlying the system in attacking the system. Public key cryptosystem RSA based on real small number problem, public key cryptosystem based on discrete logarithm problem Both DSA and elliptic curve cryptosystem have been analyzed for many years and precise analysis of such system attacks is based on mathematical analysis It is said to be loose. Therefore, it should now be analyzed what is the "underlying problem". Elliptic Curve Discrete logarithm problem is known to be relatively easy when it is a small class of elliptic curves, a super-specific elliptic curve. However, these vulnerabilities can be easily identified and therefore easily avoided. The sub-exponential time algorithm is generally known as the sub-algebraic problem and the discrete logarithm problem in modular p. The sub-exponential time algorithm is still known to be a difficult problem, but it is easier than a problem that allows only a fully exponetail time algorithm. The execution time of this algorithm is constant for c but there is no sub-exponential time algorithms in this group (avoiding the super-specific elliptic curve). That is, it is easy to design a secure cryptosystem. While RSA and DSA use 1024 bit modular, ECC shows that 160 bit modular is sufficient. Moreover, as the key size increases, the ratio increases further.

In order to perform the binary subtraction method to be applied to the ECC, there is a problem that the load on the redundant memory access is relatively large in a resource limited environment.

KR 10-2010-0025403 (Polynomial basis based binary parallel multiplication device and method, and microprocessor using the same, Industry University Collaboration Foundation of Korea University) 2010.03.09.

In order to solve the problems of the prior art as described above, the present invention reduces the load on memory access redundancy by efficiently using a register through a binary subtraction method in an environment where resources are limited, such as an 8-bit based ATmega 128 processor And to provide a method for subtracting binary codes for elliptic curve cryptosystems.

According to an aspect of the present invention, there is provided a method of subtracting an elliptic curve cryptography binary from a memory, the method comprising: inputting a plurality of words representing a degree of an input binary object into a register; And a subtracting step of subtracting a plurality of words loaded in the register by a ternary polynomial of a ternary or a five-polynomial.

More preferably, the memory unit may update and store the plurality of subtracted words.

More preferably, the step of subtracting a plurality of words loaded in the register by a subtracting unit for subtracting the plurality of words through the 1-bit left shift and word shift operations may be performed by the irreducible polynomial.

A method of subtracting an elliptic curve cryptography binary according to the present invention comprises the steps of: loading data stored in a memory into a register, storing the result of the subtraction operation in a memory, There is an effect that the improvement ratio of the subtraction operation can be increased.

1 is a diagram illustrating a 32-bit processor-based binary subtraction method.
FIG. 2 is a diagram illustrating a method of subtracting a binary body according to a conventional technique applied to a 32-bit processor.
3 is a flowchart of a method of subtracting an elliptic curve cryptography binary according to an embodiment of the present invention.
4 shows a general purpose register of an 8 bit based ATmega 128 processor.
FIG. 5 is a diagram illustrating a method of subtracting an 8-bit processor-based binary code for elliptic curve cryptosystem.
6 is a diagram illustrating an operation process of a subtraction process for each loop counter for a subtraction operation.
FIG. 7 is a table showing words that are finally shifted by subtracting each word in the subtraction process.
8 is a table showing a comparison of efficiency between the prior art and the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, the present invention will be described in detail with reference to preferred embodiments and accompanying drawings, which will be easily understood by those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Hereinafter, a binary subtraction method used in ECC (Elliptic Curve Cryptography), which is the next generation public key cryptosystem, will be described in detail.

First, the elliptic curve cryptosystem using the present invention will be briefly described. The elliptic curve cryptosystem is a public key cryptographic algorithm based on the disadvantage of discrete logarithm, and has recently attracted attention as a core technology of e-commerce following RSA algorithm. The elliptic curve cryptosystem based on the difficulty of discrete algebra is a kind of public key system together with DSA algorithm and RSA based on factorial decomposition. ECC was first proposed in 1985 by N. Koblitz and V.S. Miller as an alternative to RSA encryption, and is now widely adopted by security systems and e-commerce solution providers. ECC does not make a new public key cryptographic algorithm in the finite position using elliptic curves, but it has the feature that it implemented the existing public key algorithm with elliptic curves.

Also, the binary body is a finite field GF (2m) with 2m elements for arbitrary m (order of finite field). The element of this finite field is a bit string of length m, and finite field arithmetic is implemented in terms of bits. The elliptic curve applicable to this binary form takes the form y2 + xy = x3 + ax2 + b.

The number of possible curves satisfying the equation is actually infinity, but only a small number of curves are used for ECC. These curves are specified in FIPS 186 and are called NIST recommended elliptic curves. Each curve consists of a set of area parameters consisting of the x and y coordinates of the base point G (x, y) on each name and fractional module p, the prime number n, the coefficient a, the coefficient b and the curve.

의 원소들을 비트(bit)의 나열하여 기약다항식으로 표현할 수 있다. 이때, 각 비트들은 최고차항이

이하인 다항식의 계수들을 나타낼 수 있다. 상기 이진체의 원소들은 기약다항식에 따라 구성방식이 달라지며 각 원소들끼리의 곱셈 연산은 기약다항식을 이용한 감산 연산을 통해서 수행 될 수 있다. Binary

Can be expressed in terms of irreducible polynomials by arranging the bits. At this time,

Or less. The elements of the binary body are structured according to the irreducible polynomial, and the multiplication operation between the elements can be performed by the subtraction operation using the irreducible polynomial.

Hereinafter, a fast reduction method, which is a subtraction method that depends on an irreducible polynomial in a binary form according to the prior art, will be described.

1 is a diagram illustrating a 32-bit processor-based binary subtraction method.

일 때, 입력 값의 10번째 워드

를 하기의 수학식 1과 같이 표현할 수 있다.As shown in FIG. 1, in the binary subtraction method according to the related art, subtraction is performed by one word per loop. For example, in a 32-bit processor environment,

, The tenth word of the input value

Can be expressed by the following equation (1).

Considering the right four columns of the joint expression, the subtraction operation of C [9] is performed by performing four exclusive OR operations (XOR) on the corresponding lower words C [5], C [4], and C [ It is possible. The least significant bits of C [9] are processed by exclusive-OR (XOR) operations on 132, 131, 128, and 125th bits, respectively.

2 is a diagram illustrating a binary subtraction method according to the prior art applied to a 32-bit processor.

에 대한 Fast reduction 방법을 수행한다. As shown in FIG. 2, in a 32-bit processor environment, a value obtained by doubling the word size as a result of a multiplication operation or a square operation is received as an input value,

The fast reduction method is performed.

Hereinafter, a method of subtracting an elliptic curve cryptography binary according to an embodiment of the present invention will be described with reference to FIG.

3 is a flowchart of a method of subtracting an elliptic curve cryptographic binary according to the present invention.

As shown in FIG. 3, in the method for subtracting an elliptic curve cryptographic binary according to the present invention, a plurality of words indicating the degree of an input binary object are input from a memory unit and loaded into a register (S110).

The subtraction unit subtracts the plurality of words loaded in the register by the selected irreducible polynomial (S120).

또는 오항다항식

을 기약다항식으로 선택한다. 예를 들어, 만약 삼항 기약다항식이 존재한다면 그 중에서 가장 차수가 낮은

를 선택하고, 삼항 기약다항식이 존재하지 않으면 오항 기약다항식에서 차수가 가장 낮은

를 선택한다. 이어서,

도 차수가 가장 낮은 것으로 기약다항식을 선택한다. 위와 같은 방식으로 모든

에 대해 기약다항식을 선택할 수 있다. In particular, the polynomial is made up of a ternary or five-polynomial. For binomial calculations, the ternary polynomial

Or a pentagon polynomial

As an irreducible polynomial. For example, if a ternary irreducible polynomial exists,

, And if the ternary irrational polynomial does not exist,

. next,

Select the irreducible polynomial with the lowest order. All of the above

Can choose an irreducible polynomial.

In addition, the plurality of words can be subtracted through 1-bit left shift and word shift operations.

The memory unit updates the subtracted words and stores the words therein (S130).

적용하는 경우를 살펴보기에 앞서, 본 발명이 적용되는 8 비트 기반의 ATmega128 프로세서에 대하여 간략히 살펴보도록 한다. The present invention is not limited to a 32-bit based processor environment but a fast reduction algorithm in an 8-bit based ATmega128 processor environment,

Hereinafter, an ATmega128 processor based on 8 bits according to an embodiment of the present invention will be briefly described.

The ATmega128 processor is an 8-bit based microprocessor in the MICA2 / MICAz sensor motto, which is typically used in wireless sensor networks. In order to maximize performance and parallelism, the ATmega 128 processor has a Havard structure for distinguishing memory and bus for programs and data. When an instruction is executed in a program memory, a command to be executed next is stored in a program memory Lt; RTI ID = 0.0 > prefetched < / RTI > Through this process, the ATmega128 processor can execute instructions every clock cycle.

The general register file in the ATmega128 CPU is executed by the ALU for two data items from the register file in one clock cycle, and the result is stored in the register file again, as shown in Fig. Six of the 32 registers (R31: R30, R29: R28, R27: R26) are used as three 16-bit indirect address registers (X, Y, Z) The remaining 26 registers can be used to perform finite field operations.

에 적용하면 도 5와 같이 나타낼 수 있다. 특히, 8 비트 프로세서 환경에서 271 비트 원소는 34개의 8 비트 워드로 구성되는데, 유한체의 감산 연산 시에는 유한체 곱셈 연산과 유한체 제곱 연산의 결과를 입력받기 때문에 최대 68개의 워드를 입력받는다. 따라서 C[67]부터 C[0]까지의 입력을 C[33] 부터 C[0]으로 감산 연산이 진행된다. In this 8 bit based ATmega128 processor environment, the fast reduction algorithm is called the irreducible polynomial

It can be expressed as shown in FIG. In particular, in an 8-bit processor environment, the 271-bit element is composed of 34 8-bit words. When subtracting a finite field, the result of finite field multiplication and finite field operation is input. Therefore, the subtraction operation from C [67] to C [0] is performed from C [33] to C [0].

FIG. 6 is a flowchart illustrating an operation of a loop counter for a subtraction operation in the method of subtracting an elliptic curve cryptographic binary according to the present invention.

으로 감산하는 루프 카운터

가 66에서 62에 대하여 동작할 때를 나타낸 것이다. As shown in FIG. 6, the result of the finite-field multiplication operation and the finite field multiplication operation is called the irreducible polynomial

Loop counter

Lt; RTI ID = 0.0 > 66 < / RTI >

In FIG. 6, an underline of a line indicates a portion where data is redundantly loaded from memory or a result value is redundantly stored. In this case, C [32], C [30], C [29], and C [28], which are underlined in a single line, are loaded twice from the memory each time when five loops are executed, . This redundant load or store value can be reused in the register to reduce the load due to memory access.

가 66일 때와

가 62일 때 두줄 밑줄로 표기된 C[54]를 각각 로드하여 감산 연산 루프를 수행하여 다시 저장하게 된다. 이처럼 루프 카운터가 진행됨에 따라서 동일한 워드를 다시 호출하는 경우가 발생하게 된다. 따라서 이를 효율적으로 처리할 수 있는 방법이 필요하다.The loop counter

When it was 66

Is 62, C [54] indicated by two underlines are loaded, respectively, and a subtraction operation loop is performed and stored again. As the loop counter proceeds, the same word is called again. Therefore, there is a need for a method that can efficiently handle this.

부터 차례로 8 비트씩 각각 하나의 워드를 형성한다. 여기서 각 워드들은 오직 1-비트 레프트 시프트(1-bit left shift)와 워드 시프트 연산을 통해 감산을 수행한다. Looking at the upper word of the object to be subtracted

One word each in 8-bit order. Where each word performs subtraction through only a 1-bit left shift and a word shift operation.

이고 272와 208, 176, 112의 차는 각각 64, 32, 64로 모두 8의 배수이므로 워드 시프트 연산으로 처리 가능하고

는 1-비트 레프트 시프트로 처리하여 감산이 가능하다. E.g,

And the difference between 272 and 208, 176, and 112 is 64, 32, and 64, which are all multiples of 8, so that they can be processed by a word shift operation

Can be processed by a 1-bit left shift and subtracted.

FIG. 7 is a table showing words that are finally shifted by subtracting each word in the subtraction process.

C [34], C [42], C [46], C [50], C [54], and C [62] are written in the first word C [0] An exclusive-OR (XOR) operation is performed in a state of being left-shifted by one bit. C [34], C [42], C [46], and C [64] are shifted leftward by one bit in the fifteenth word C [ , C [50], C [54], and C [62] generate an exclusive OR operation.

Considering these characteristics, memory access operations can be minimized by efficiently loading the word into the register and reusing it and storing it in the memory only after the subtraction operation is completed.

Accordingly, in the case of performing the subtraction operation according to the present invention, the operation of loading from the memory requires 1 time from C [0] to C [41], twice from C [42] to C [67] Since the operation to be stored in memory is stored only after the operation of each word is completed, it is used only once from C [0] to C [33].

In particular, in the method of subtracting an elliptic curve cryptographic binary according to the present invention, only one clock cycle is required for an operation performed on data in a register, while the data stored in the memory is loaded into a register, Lt; RTI ID = 0.0 > 2 < / RTI > clock cycles. Therefore, memory load and storage are minimized and implemented in assembly language.

FIG. 8 is a table comparing performance in terms of clock cycles when implementing the fast reduction method according to the related art and the subtraction method according to the present invention in an assembly language.

에서 기약다항식

에 Fast reduction을 구현 시 1,084 클럭 사이클이 소모되었고, 제안하는 감산 연산 알고리즘을 사용하여 구현 시 482 클럭 사이클이 소모되어 약 56% 정도 속도가 향상된 것을 알 수 있다. As shown in Fig. 8,

In this case,

, It is shown that 1,084 clock cycles are consumed when fast reduction is implemented, and 482 clock cycles are consumed in the implementation using the proposed subtraction algorithm, resulting in a speed improvement of about 56%.

However, such a value is an improvement rate of the subtraction method of the present invention, and additional processing is indispensably added to realize a real public key cryptosystem. For example, a register that contains an address value in an input or output memory is put into the stack with the push instruction before using it, and then the address value is received by the pop instruction again after the subtraction is finished, . Due to the additional operation, the fast reduction according to the prior art increases from 1,084 clock cycles to 1,126 clock cycles, and in the present invention, from 482 clock cycles to 524 clock cycles. The added clock cycle lowers the overall improvement rate. Therefore, the actual improvement ratio of the subtraction operation is about 53%.

Embodiments of the present invention may be implemented in the form of program instructions that can be executed on various computer means and recorded on a computer readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Examples of program instructions, such as magneto-optical and ROM, RAM, flash memory and the like, can be executed by a computer using an interpreter or the like, as well as machine code, Includes a high-level language code. The hardware devices described above may be configured to operate as at least one software module to perform operations of one embodiment of the present invention, and vice versa.

The method of subtracting an elliptic curve cryptography binary according to the present invention requires a memory load and a storage to be minimized by a subtraction algorithm as the data stored in the memory is loaded into the register or the result of the operation is stored in the memory again for 2 clock cycles. So that the improvement rate of the subtraction operation can be increased.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Do.

Claims (4)

Inputting a plurality of words representing the order of the binary input unit from the memory unit and loading the words into the register; And
Subtracting a plurality of words loaded in the register by a ternary polynomial of a ternary or a five-polynomial,
Wherein the step of performing the subtraction operation with the irreducible polynomial expression comprises:
And subtracting the plurality of words by a 1-bit left shift and a word shift operation.
The method according to claim 1,
Updating the plurality of words by the memory unit and storing the updated words;
Further comprising the steps of: (a) inputting a binary code for the elliptic curve cryptography code;
delete A computer-readable recording medium on which a program for executing the method according to any one of claims 1 to 2 is recorded.

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