KR101631465B1 - Low-pass filter and semiconductor device including the same - Google Patents

Low-pass filter and semiconductor device including the same Download PDF

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KR101631465B1
KR101631465B1 KR1020150191718A KR20150191718A KR101631465B1 KR 101631465 B1 KR101631465 B1 KR 101631465B1 KR 1020150191718 A KR1020150191718 A KR 1020150191718A KR 20150191718 A KR20150191718 A KR 20150191718A KR 101631465 B1 KR101631465 B1 KR 101631465B1
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South Korea
Prior art keywords
amplifier
low
pmos transistor
input
nmos transistor
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KR1020150191718A
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Korean (ko)
Inventor
박유진
김수환
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서울대학교 산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/0422—Frequency selective two-port networks using transconductance amplifiers, e.g. gmC filters
    • H03H11/0427—Filters using a single transconductance amplifier; Filters derived from a single transconductor filter, e.g. by element substitution, cascading, parallel connection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/0422—Frequency selective two-port networks using transconductance amplifiers, e.g. gmC filters
    • H03H11/0461—Current mode filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/06—Frequency selective two-port networks comprising means for compensation of loss
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/004—Capacitive coupling circuits not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2210/00—Indexing scheme relating to details of tunable filters
    • H03H2210/02—Variable filter component
    • H03H2210/021—Amplifier, e.g. transconductance amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2210/00—Indexing scheme relating to details of tunable filters
    • H03H2210/02—Variable filter component
    • H03H2210/025—Capacitor

Abstract

A low frequency filter according to an embodiment of the present invention includes a resistor connected between an input terminal and an output terminal, an amplifier, a current source for providing a bias current to the amplifier, a first capacitor connected between the output terminal and the output terminal of the amplifier, And a second capacitor connected between the output and the input of the amplifier.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low-

The present invention relates to a low-pass filter and a semiconductor device including the low-pass filter. More particularly, the present invention relates to a low-pass filter that occupies a narrow area and does not deteriorate filtering performance over a wide range of input voltages, and a semiconductor device including the low-pass filter.

The vehicle is equipped with a number of sensors, which receive signals in the low-frequency range of tens to tens of thousands of hertz.

The low frequency filter included in the input of the device receiving signals from these sensors can use a large capacity capacitor to reduce the bandwidth.

1 is a circuit diagram of a general low-pass filter.

The low-pass filter of FIG. 1 low-pass filters the input voltage Vi to produce an output voltage Vo.

As shown in FIG. 1, a conventional low-pass filter composed only of a resistor R and a capacitor C, which are passive elements, must have a large resistor R and a large capacitor C in order to reduce the bandwidth.

However, when the resistance R is increased, noise due to the temperature increases, and when the capacitance of the capacitor C is increased, the area of the circuit increases.

A capacitance multiplier may be used to solve the problem of increasing the capacitance of the capacitor C.

The capacity multiplier has the effect of increasing the size of the substantial capacity by the amplification ratio, and the capacity of the capacitor to be used can be made small.

2 and 3 are circuit diagrams of a conventional low frequency filter using a capacitance multiplier.

2, the effective capacitance is given by a value obtained by multiplying the capacitance of the capacitor C by the current gain of the transistor Q.

That is, the capacitance of the actual capacitor C can be reduced in proportion to the current gain.

However, when the transistor Q is turned on, a voltage drop occurs as much as the threshold voltage, so that the input voltage Vi can not be provided as the output voltage Vo.

3 is a circuit diagram of a low-frequency filter including a capacitance multiplier circuit using an operational amplifier A. In Fig.

In Fig. 3, the effective capacitance corresponds to the value obtained by multiplying the capacitor C by the resistance ratio R1 / R2.

However, in the circuit shown in FIG. 3, the input / output of the operational amplifier A is limited not only to the range of the power supply voltage but also requires a minimum voltage margin for operation of the component. Therefore, when the input voltage Vi swings in a wide range from several volts to several tens of volts, it is very difficult to operate normally when the input voltage Vi swings.

Even if the operation is performed with a minimum voltage margin, the structure of the input / output stage circuit becomes complicated, thereby causing an increase in circuit area and an increase in power.

And a semiconductor device for receiving signals from a plurality of sensors in a complex system such as an automobile. When such a semiconductor device uses a low-frequency filter for each channel, the area of the low-frequency filter greatly affects the area of the semiconductor device.

Accordingly, there is a demand for a low-frequency filter that occupies a small area and does not deteriorate the filtering performance over a wide range of input voltages, and a semiconductor device including the low-frequency filter.

US 2008-0246539 A1 KR 10-0604983 B1 KR 10-2005-0027899 A KR 10-2010-0127839 A

The present invention provides a low-frequency filter having a reduced area and a filtering performance against a wide range of input voltages, and a semiconductor device including the low-frequency filter.

A low frequency filter according to an embodiment of the present invention includes a resistor connected between an input terminal and an output terminal, an amplifier, a current source for providing a bias current to the amplifier, a first capacitor connected between the output terminal and the output terminal of the amplifier, And a second capacitor connected between the output and the input of the amplifier.

A semiconductor device according to an embodiment of the present invention includes a plurality of low frequency filters for receiving a plurality of signals, a channel multiplexer for selecting one of the outputs of the plurality of low frequency filters according to an internal channel activation signal, And a channel controller for outputting an internal channel activation signal according to a channel activation signal, wherein the plurality of low-pass filters include a resistor connected between the input and the output, a current source for providing a bias current to the amplifier, an output terminal between the output terminal and the output terminal A first capacitor connected to the first capacitor; And a second capacitor connected between the output and the input of the amplifier.

The present invention can provide a low-frequency filter that does not deteriorate the low-frequency filtering performance over a wide range of input voltages without occupying a large area, and a semiconductor device including the low-frequency filter.

1 to 3 are circuit diagrams of a conventional low-frequency filter.
4 is a circuit diagram of a low-pass filter according to an embodiment of the present invention.
5 is a block diagram of a semiconductor device according to an embodiment of the present invention;
6 is a circuit diagram of the low-pass filter of Fig.
Figure 7 is a block diagram of the channel controller of Figure 5;
8 is a logic circuit diagram of the first unit of Fig.
9 is a logic circuit diagram of the second unit of Fig.
10 is a waveform diagram showing the operation of the channel controller of FIG. 5;
11 is a graph showing the effect of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

4 is a circuit diagram of a low-frequency filter according to an embodiment of the present invention.

Basically, the low-frequency filtering operation is performed by the resistors R1 and R2, the capacitor C1, the PMOS transistor MP1 and the NMOS transistor NM1.

The PMOS transistor MP1 and the NMOS transistor NM1 function as amplifiers to multiply the capacitance of the capacitor C1.

At this time, the input terminal of the amplifier is the gate of the PMOS transistor MP1, and the output terminal of the amplifier is the common drain of the PMOS transistor MP1 and the NMOS transistor MN1.

Therefore, it can be understood that the capacitor C1 is connected between the output terminal of the low-pass filter and the output terminal of the amplifier, and the capacitor C2 is connected between the output terminal of the low-pass filter and the input terminal of the amplifier.

The PMOS transistor MP2 and the NMOS transistors MN1 and MN2 operate as a current source and provide a bias current to the PMOS transistor MP1 according to the bias voltage VB.

The resistors R1 and R2 operate as a voltage divider to relatively reduce the voltage input to the amplifier compared to the input voltage Vi. Accordingly, the range of the input voltage Vi can be extended more than the power supply voltage of the amplifier.

The voltage division ratio can be changed to a suitable range in consideration of the power supply voltage (VDD) and the breakdown voltage characteristics of the transistors.

Therefore, when the voltage drop of the input voltage Vi is not required, the resistor R2 may not exist.

If the transconductance gain of the PMOS transistor MP1 is g mp1 , the output resistance of the PMOS transistor MP1 is r o , mp 1 and the exit resistance of the NMOS transistor MN 1 is r o , mn 1 , then the effective capacitance C of the low- Can be expressed by Equation (1).

Figure 112015129522405-pat00001

In this case, the bandwidth (f 3dB ) of the low-pass filter can be expressed by the following equation (2).

Figure 112015129522405-pat00002

The switch SW provides the gate voltage of the PMOS transistor MP2 as the gate voltage of the PMOS transistor MP1 in accordance with the precharge signal PC.

The precharge signal PC may be activated when the input voltage Vi is not provided and deactivated when the input voltage Vi is provided.

The capacitor C2 replicates and stores the gate voltage of the PMOS transistor MP2 according to the precharge signal PC.

The capacitor C2 functions to decouple the DC component of the input voltage Vi so that the DC component of the input voltage Vi is not directly applied to the gate of the PMOS transistor MP1.

Accordingly, even if the DC level of the input voltage Vi is changed, the PMOS transistor MP1 can operate in the saturation region.

That is, even if the DC level of the input voltage Vi is changed, the bias point variation of the amplifier constituted by the PMOS transistor MP1 and the NMOS transistor MN1 is suppressed. Accordingly, the input voltage Vi) is applied, the function of the low-pass filter can be fully performed in a constant bandwidth.

2, the base voltage of the transistor Q is directly affected by the DC level of the input voltage Vi. Therefore, unlike the present invention, the low-frequency filtering performance A large difference may occur.

The charge charged in the capacitor C2 during the pre-charge operation may leak due to various factors.

When the charge charged in the capacitor C2 is leaked, the bias change of the amplifier is inevitable. Therefore, it is preferable to perform the pre-charge operation again before the charge charged in the capacitor C2 is leaked.

The precharge signal PC is inactivated while the input voltage Vi is provided. This means that the gate voltage of the PMOS transistor MP1 is no longer fixed.

Accordingly, the high frequency noise component included in the input voltage Vi is transferred to the gate of the PMOS transistor MP1 through the capacitor C2.

This means that the high-frequency noise component contained in the input voltage Vi can be applied to the low-pass filter together and removed.

As described above, the low-frequency filter according to the present invention can suppress an increase in the area due to an increase in the capacity of the capacitor by using the capacity multiplier, and suppress the fluctuation of the bandwidth even if the DC level of the input voltage Vi is changed to perform the low- .

5 is a block diagram of a semiconductor device according to an embodiment of the present invention.

A semiconductor device according to an embodiment of the present invention includes a plurality of low frequency filters 100, a bias voltage generator 200, a channel multiplexer 300, and a channel controller 400.

In this embodiment, the low-pass filter 100 exists for each channel.

In the present embodiment, each of the low-frequency filters 100 may operate as a conventional low-frequency filter as shown in FIG. 1 or may operate as a low-frequency filter according to the present invention as shown in FIG. 4 according to the control of the filter activation signal FEN.

A specific configuration of the low-pass filter 100 will be described below with reference to Fig.

The channel multiplexer 300 includes a plurality of switches SW. Each switch SW selectively provides a signal of a corresponding channel to the outside.

The input terminal of each switch SW is connected to the output terminal of the corresponding low frequency filter 100, and the output terminal of each switch SW is connected to one output terminal.

The channel multiplexer 300 turns on only one of the plurality of switches SW at a specific time point and outputs only one of the signals input through the plurality of channels to the outside.

A plurality of switches SW are controlled by an internal channel activation signal CENI.

The internal channel activation signal CENI is turned on when the signal IN is input from the corresponding channel, and is turned off if not.

The channel controller 400 generates an internal channel activation signal CENI according to the channel activation signal CEN and the clock signal CLK.

The channel activation signal (CEN) provides the information of the currently used channel.

The channel controller 400 generates an internal channel enable signal CENI to sequentially select only currently used channels according to the clock signal CLK.

For channels that are not currently in use, the internal channel enable signal (CENI) remains inactive.

The internal channel activation signal CENI can be controlled so that the low frequency filter CENI operates as in the conventional filter shown in FIG. 1 for a channel that is input to the low frequency filter 100 and is not activated.

In this embodiment, the channel controller 400 generates a precharge signal PC to control the precharge operation of the plurality of filters 100. [

Fig. 6 is a circuit diagram of the low-pass filter 100 of Fig.

The circuit of Fig. 6 is substantially the same as the circuit of Fig.

The low-pass filter 100 of FIG. 6 further includes an NMOS transistor MN3 and NMOS transistors MN4 and MN5 that are complementarily turned on or off so that the low-pass filter 100 operates as the circuit of FIG. 4 Can be selectively controlled.

 When at least one of the filter activation signal FEN and the internal channel activation signal CENI is low, the NMOS transistor MN3 is turned on under the control of the NAND gate ND1 and the NMOS transistor MN4 is turned on under the control of the inverter INV1. And MN5 are turned off.

In this case, the circuit of Fig. 6 becomes substantially the same as the circuit of Fig. Accordingly, when the signal is not input even though the channel is unused or the channel is in use, the power consumed by the filter can be minimized.

When the filter activation signal FEN and the internal channel activation signal CENI are both high, the NMOS transistor MN3 is turned on and the NMOS transistors MN4 and MN5 are turned off.

In this case, the circuit of Fig. 6 becomes substantially the same as the circuit of the low-pass filter of Fig.

Figure 7 is a block diagram of the channel controller of Figure 5;

The channel controller 400 includes a first unit 410 and a plurality of second units 420.

The first unit 410 and the plurality of second units 420 sequentially operate in synchronization with the internal clock signal CLKI and output the precharge signal PC and the internal channel activation signal CENI.

The first unit 410 and the second unit 420 are connected to each other in a ring shape so that the first output FO of the front end is connected to the first input end FI of the rear end.

The power supply voltage VDD is applied to the second input EN of the first unit 410 and the corresponding channel activation signal CEN is applied to the second input EN of the second unit 420. [

The first unit 410 outputs the precharge signal PC at the second output Q and the second unit 420 outputs the internal channel activation signal CENI at the second output Q .

The precharge signal PC is activated before sequentially activating the internal channel activation signal for the currently used channel to precharge the capacitor C2 included in the low frequency filter 100. [

The channel activation signal (CEN) indicates the channels currently in use. Accordingly, the internal channel activation signal CENI can be output so as to sequentially skip channels that are not currently in use and select only the channels in use.

The chip select signal CS and the reset signal RST are signals for determining the active condition of the channel controller 400 and are supplied to the output of the AND gate 430 when the chip select signal CS is activated and the reset signal RST is inactivated The first unit 410 and the second unit 420 are activated and the clock signal CLK is supplied to the internal clock signal CLKI in accordance with the operation of the AND gate 440. [

In this embodiment, the pre-charge signal PC is activated again after selecting the channels in use once, but in another embodiment, the pre-charge signal PC is activated after selecting the channels in use more than two times Precharging operation, which can be selected according to the degree of charge leakage of the capacitor C2.

Fig. 8 is a logic circuit diagram of the first unit 410 in Fig. 7, and Fig. 9 is a logic circuit diagram of the second unit 420. Fig.

The configurations of the two circuits are substantially the same, but the operation differs in the following points.

Although the first unit 410 is always activated (EN = VDD), the second unit 420 is activated or not according to the channel activation signal CEN.

The D flip-flop DFF of the first unit 410 is in the active state and the initial output is "high" while the D flip-flop DFF of the second unit 420 is active and the initial output is "low".

Accordingly, the precharge signal PC, which is the output of the first unit 410, is first activated and the internal channel activation signal CENI, which is the output of the second unit 420, is deactivated at the beginning of the operation.

The first unit 410 has a first input terminal EN and a second input terminal EN so that the values of the first output terminal FO and the second output terminal Q are connected to a first input terminal Has the same value as the output value FO of the front end (last second unit), that is, the value of the input signal FI.

The value of the second input EN of the second unit 420 depends on the channel activation signal CEN.

When the channel enable signal CEN is low, the output of the D flip-flop DFF, i.e., the second output Q, maintains a low level and the value of the first output FO is equal to the value of the first input FI same. That is, when the channel activation signal CEN is low, the second unit DFF transfers the output FO of the previous stage as it is to the next stage.

When the channel enable signal CEN is high, the values of the first output terminal FO and the second output terminal Q are the values of the first input terminal FI latched by the previous clock by the D flip-flop DFF, And has the same value as the output value FO.

10 is a waveform diagram illustrating the operation of the channel controller of FIG.

The waveform diagram of FIG. 10 assumes that channel activation signal CEN <2> of channel 2 is low.

As shown in the figure, the precharge signal PC is activated and deactivated at the beginning of the operation, and the internal channel activation signal CENI is skipped over the channel 2 and sequentially activated in order of 1, 3, ..., N channels .

After the Nth channel is activated, the precharge signal PC is activated and the same operation is repeated.

The above embodiment assumes that the precharge signal PC is reactivated every time each channel is activated once to perform a precharge operation.

The period of the precharge operation can be set differently according to the degree of leakage of charge in the capacitor C2 of the low frequency filter 100. [

For example, an embodiment in which the precharge operation is performed after each channel is activated twice or a different number of times is also possible.

11 is a graph showing the effect of the present invention.

(a) is a graph showing the operation of the conventional low-frequency filter shown in Fig. 1, Fig. 4 (b) is a graph showing the operation when the capacitor C2 is not present and the switch SW is always turned on (C) is a graph showing a case where the capacitor C2 is present as shown in FIG. 4 and the switch SW is turned on only during the pre-charge operation.

(a) shows that although the bandwidth is constant according to the DC level of the input voltage (Vi), there is a problem that a capacitor having a large area is used in order to narrow the bandwidth, and a problem that the bandwidth can not be narrowed sufficiently when capacitors having the same capacity are used Lt; / RTI &gt;

(b) shows that the bandwidth is not constant but varies according to the DC level of the input voltage Vi. The graph indicates that low frequency filtering can not be performed at the desired bandwidth when the DC level is between 0 and 11V.

(c) shows that the low-frequency filtering is performed to a desired level even if the bandwidth is constant according to the DC level of the input voltage Vi and the DC level is 0 to 11 V. FIG.

The embodiments of the present invention have been described with reference to the drawings. The foregoing disclosure is intended to be illustrative of the invention and not to limit the scope of the invention by the foregoing disclosure. The scope of the present invention is defined by the claims and their equivalents.

100: Low frequency filter (LPF)
200: bias voltage generator
300: channel multiplexer
400: channel controller
410: first unit
420: second unit
430, 440: AND gate

Claims (20)

A resistor connected between the input and output
amplifier;
A current source for providing a bias current to the amplifier;
A first capacitor connected between the output terminal and the output terminal of the amplifier; And
And a second capacitor connected between the output terminal and the input terminal of the amplifier,
, &Lt; / RTI &
Wherein the second capacitor is precharged while a signal is not input to the input terminal to fix an initial voltage at an input terminal of the amplifier. The low-pass filter according to claim 1, further comprising precharging means for precharging the second capacitor according to a precharge signal. The low-frequency filter according to claim 1, further comprising a resistor having one end connected to the output end and the other end grounded. 2. The semiconductor memory device according to claim 1, wherein the amplifier includes a first PMOS transistor and a first NMOS transistor having drains connected in common, and the current source includes a second PMOS transistor and a second NMOS transistor having drains connected in common, And a source of the second PMOS transistor is connected to a power supply terminal and a source of the first NMOS transistor and a source of the second NMOS transistor are grounded. 5. The method of claim 4, wherein the input of the amplifier is a gate of the first PMOS transistor and the output of the amplifier is a common drain of the first PMOS transistor and the first NMOS transistor, And a bias voltage is input to the gates of the first NMOS transistor and the second NMOS transistor. The low-frequency filter according to claim 5, further comprising a switch for commonly connecting gates of the first PMOS transistor and the second PMOS transistor according to a precharge signal. The low-pass filter according to claim 1, further comprising a first switch for grounding the output terminal of the amplifier in accordance with a control signal, and a second switch for stopping the operation of the amplifier in accordance with the control signal. A plurality of low frequency filters receiving a plurality of signals;
A channel multiplexer for selecting one of the outputs of the plurality of low frequency filters according to an internal channel activation signal and outputting the selected one to the outside; And
A channel controller for outputting the internal channel activation signal according to a channel activation signal,
Wherein the plurality of low-frequency filters comprise
A resistor connected between the input and output
amplifier;
A current source for providing a bias current to the amplifier;
A first capacitor connected between the output terminal and the output terminal of the amplifier; And
And a second capacitor connected between the output terminal and the input terminal of the amplifier,
. 9. The semiconductor device of claim 8, wherein each of the plurality of low-pass filters further includes precharging means for precharging the second capacitor according to a precharge signal. 10. The semiconductor device of claim 9, wherein the precharge signal is activated in a period in which the plurality of internal channel activation signals are inactivated. 11. The semiconductor device of claim 10, wherein the channel controller sequentially activates the plurality of internal channel activation signals corresponding to the channels selected by the channel activation signal in synchronization with the clock signal. 12. The semiconductor device of claim 11, wherein the channel controller activates the precharge signal before sequentially activating the plurality of internal channel enable signals. 9. The semiconductor device according to claim 8, further comprising bias voltage generating means for controlling the current source. 9. The semiconductor device of claim 8, wherein the channel multiplexer includes a plurality of switches for outputting any one of the outputs of the plurality of low-pass filters according to the internal channel activation signal. The semiconductor device according to claim 8, wherein each of the plurality of low-frequency filters further includes a resistor having one end connected to the output end and the other end grounded. [10] The method of claim 8, wherein the amplifier includes a first PMOS transistor and a first NMOS transistor having drains connected in common, and the current source includes a second PMOS transistor and a second NMOS transistor having drains connected in common, Source and the source of the second PMOS transistor are connected to a power supply terminal, and the source of the first NMOS transistor and the source of the second NMOS transistor are grounded. 17. The method of claim 16, wherein the input of the amplifier is a gate of the first PMOS transistor and the output of the amplifier is a common drain of the first PMOS transistor and the first NMOS transistor, And a bias voltage is input to the gates of the first NMOS transistor and the second NMOS transistor. The semiconductor device according to claim 17, wherein the plurality of low-pass filters further include switches for commonly connecting gates of the first PMOS transistor and the second PMOS transistor according to a precharge signal. The low frequency filter of claim 8, further comprising a first switch for grounding the output terminal of the amplifier when a control signal is activated, and a second switch for stopping the operation of the amplifier when the control signal is activated A semiconductor device. 21. The semiconductor device of claim 19, wherein the control signal is activated when the internal channel activation signal is inactivated.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226594B1 (en) * 1995-09-18 1999-10-15 니시무로 타이죠 Electronic circuit and filter device using same
KR20050027899A (en) 2003-09-15 2005-03-21 삼성전자주식회사 Capacitance multiplier
KR100604983B1 (en) 2004-06-14 2006-07-31 삼성전자주식회사 Capacitance multiplier for a pll loop filter
US20080246539A1 (en) 2007-04-04 2008-10-09 Zadeh Ali E Capacitor multipler circuits and the applications thereof to attenuate row-wise temporal noise in image sensors
KR20100127839A (en) 2008-03-21 2010-12-06 퀄컴 인코포레이티드 Capacitance multiplier circuit
KR20110073171A (en) * 2009-12-23 2011-06-29 한국전자통신연구원 Transimpedance amplifier circuit
KR20120073351A (en) * 2009-10-21 2012-07-04 퀄컴 인코포레이티드 Low-pass filter design

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100226594B1 (en) * 1995-09-18 1999-10-15 니시무로 타이죠 Electronic circuit and filter device using same
KR20050027899A (en) 2003-09-15 2005-03-21 삼성전자주식회사 Capacitance multiplier
KR100604983B1 (en) 2004-06-14 2006-07-31 삼성전자주식회사 Capacitance multiplier for a pll loop filter
US20080246539A1 (en) 2007-04-04 2008-10-09 Zadeh Ali E Capacitor multipler circuits and the applications thereof to attenuate row-wise temporal noise in image sensors
KR20100127839A (en) 2008-03-21 2010-12-06 퀄컴 인코포레이티드 Capacitance multiplier circuit
KR20120073351A (en) * 2009-10-21 2012-07-04 퀄컴 인코포레이티드 Low-pass filter design
KR20110073171A (en) * 2009-12-23 2011-06-29 한국전자통신연구원 Transimpedance amplifier circuit

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