KR101616272B1 - Semiconductor package manufacturing method - Google Patents

Abstract

A method of manufacturing a semiconductor package according to the present invention includes the steps of bonding a semiconductor die having a chip pad formed thereon to a lower surface of an expansion substrate using an adhesive member; A step of preparing a substrate having a lower conductive bump for a plurality of lower I / Os; a step of forming a rear conductive bump and a lower conductive bump corresponding to each other; And a step of bonding the extension substrate and the substrate by bringing the extension substrate into contact with the wiring layer of the substrate.

Description

Technical Field [0001] The present invention relates to a semiconductor package manufacturing method,

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package suitable for preventing a warpage phenomenon of a substrate caused by a difference in thermal expansion coefficient between different types of substrates, and a manufacturing method thereof.

Recently, as the market for portable electronic devices such as smart phones and smart pads has exploded, demand for semiconductor packages capable of responding to light and small sized products has been gradually increasing.

(Package-on-package: PoP) is used as one of semiconductor packages to cope with thin and light small-sized products. In such a stacked package, an expandable substrate (e.g., interposer ) Is inserted.

Here, the interposer can provide a role of rearranging a plurality of lower I / Os formed on the lower substrate so that I / O terminals can be formed in the inner space of a chip attached to the upper substrate. That is, in the conventional stacked package, since the I / O terminal can be formed in the inner space of the chip by inserting the interposer between the lower substrate and the upper substrate, the space efficiency for the I / O terminal can be increased.

Korean Patent Laid-Open Publication No. 2013-0051232 (Published on May 20, 2013)

However, a conventional stacked semiconductor package using an interposer has a problem that a warpage phenomenon occurs due to a difference in thermal expansion coefficient between a substrate and an interposer. Such a problem of occurrence of warpage causes peeling and cracking of the substrate, Which is a cause of lowering the reliability of the package.

The present invention, in accordance with an aspect, provides a semiconductor device comprising a substrate on which a lower conductive bump for a semiconductor die and a plurality of lower I / Os is formed, and an extension having a rearrangement conductive bump for a plurality of rearrangement I / O for rearranging the lower I / And a bonding member for bonding a lower portion of the semiconductor die and the extension substrate to each other.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: attaching a semiconductor die on a substrate; forming a lower conductive bump for a plurality of lower I / Os at a predetermined position on the substrate; Forming a plurality of rearrangement I / O rearrangement conductive bumps for rearranging the lower I / O; preparing a lower conductive bump and a rearrangement conductive bump corresponding to each other; And adhering the substrate and the extension substrate such that a portion of the extension substrate abuts against the adhesive member.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of bonding a semiconductor die having a lower chip pad formed thereon to a lower surface of a substrate for extension using an adhesive member, Forming a rear conductive bump for the plurality of lower I / Os; preparing a rear conductive bump corresponding to each of the rear conductive bumps; And bonding the extension substrate and the substrate such that the pad is in contact with the wiring layer of the substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: attaching a semiconductor die onto a substrate; forming a lower conductive bump for a plurality of lower I / Os at a predetermined position on the substrate; A step of forming an adhesive member on the lower semiconductor die, a step of forming a plurality of relocation conductive bumps for rearrangement I / O for rearrangement of the lower I / O, A step of preparing a substrate for extension on which the lower conductive bump and the rearranging conductive bump are brought into contact with each other and a part of the lower portion of the expansion substrate is brought into contact with the adhesive member, The present invention also provides a method of manufacturing a semiconductor package.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of bonding a semiconductor die having a lower chip pad formed thereon to a lower surface of a substrate for extension using an adhesive member, Forming a rear conductive bump for a plurality of lower I / Os; forming a rear conductive bump for a plurality of lower I / Os; A step of preparing a substrate and a step of bonding the expansion substrate and the substrate with each other so that the rearrangement conductive bumps and the lower conductive bumps abut each other and the chip pads of the semiconductor die come into contact with the wiring layer of the substrate The present invention also provides a method of manufacturing a semiconductor package.

The present invention provides a means (a bonding member) for physically fixing the upper portion of a semiconductor die attached to a substrate and the interposer, thereby preventing the substrate from being warped due to a difference in thermal expansion coefficient between the two substrates, The reliability of the product can be improved.

1 is a sectional view of a semiconductor package according to the present invention,
FIG. 2 is an exemplary sectional view illustrating a semiconductor package in which two substrates are bonded in a ball-to-ball manner according to the present invention;
FIG. 3 is an exemplary cross-sectional view illustrating a semiconductor package in which two substrates are bonded in a ball-to-
FIG. 4 is an exemplary sectional view illustrating a semiconductor package in which two substrates are bonded in a post-to-ball manner according to the present invention;
FIG. 5 is an exemplary sectional view illustrating a semiconductor package in which two substrates are bonded in a post-to-post manner according to the present invention;
6A to 6E are process flow diagrams showing a main process of fabricating a semiconductor package according to an embodiment of the present invention,
7A to 7E are process flow diagrams showing a main process of fabricating a semiconductor package according to another embodiment of the present invention,
8A to 8E are process flow diagrams showing a main process of fabricating a semiconductor package according to another embodiment of the present invention;
9A-9E are process flow diagrams illustrating a major process for fabricating a semiconductor package in accordance with another embodiment of the present invention.

First, the advantages and features of the present invention, and how to accomplish them, will be clarified with reference to the embodiments to be described in detail with reference to the accompanying drawings. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. It is to be understood that the following terms are defined in consideration of the functions of the present invention, and may be changed according to intentions or customs of a user, an operator, and the like. Therefore, the definition should be based on the technical idea described throughout this specification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor package according to the present invention. The semiconductor package of the present invention includes a lower substrate 110 on which a lower semiconductor die 111 and a plurality of lower conductive bumps 112 for a plurality of lower I / And an adhesive member 113 physically adhered to the lower portion of the extension substrate 120 is formed on the upper portion of the semiconductor die 111.

Here, the extension substrate 120 has a plurality of lower portions I (I) formed on the lower substrate 110 so that I / O terminals can be formed in the inner space of a semiconductor die (chip) attached to an upper substrate / O, and the adhesive member 113 may be any one of, for example, a laminate film, a thermosetting liquid adhesive, and an NCF (none conductive film) adhesive.

A mold member 130 is formed between the lower substrate 110 and the extension substrate 120 to embed a semiconductor die 111 and a plurality of lower conductive bumps 112. The lower substrate 110, A plurality of conductive bumps 114 for physical / electrical connection with the board (not shown) are formed at the lower end of the board. The mold member 130 may be formed through a molding process after the lower substrate 110 and the extension substrate 120 are bonded or may be formed on the lower substrate 110 by a semiconductor die 111 and a plurality of lower conductive bumps 110. [ May be formed between the time when the adhesive 112 is formed and the time when the adhesive 113 is formed on the semiconductor die 111.

The plurality of lower conductive bumps 112 provide a function of physically (electrically) connecting each corresponding I / O of the lower substrate 110 to each corresponding relocation I / O of the expansion substrate 120 A solder ball, a copper ball whose surface is coated with a solder, and a conductive post (for example, a copper post).

On the other hand, in the semiconductor package of the present invention, each I / O of the lower substrate and each corresponding I / O of the expanding substrate may be formed in various ways such as ball to ball, ball to post ), Post-to-ball, post-to-post, and the like.

FIG. 2 is an exemplary sectional view illustrating a semiconductor package in which two substrates are bonded by a ball-to-ball method according to the present invention. The I / O of each of the lower substrate 210 and each of the I / A structure in which a ball-to-ball system is connected is exemplarily shown.

In FIG. 2, a ball formed on the lower substrate 210 may be defined as a lower conductive bump, and a ball formed on the extending substrate 220 may be defined as a rearrangement conductive bump. Reference numeral 213 in FIG. 2 denotes a bonding member for bonding (fixing) between a semiconductor die formed on the lower substrate 210 and a lower portion of the extension substrate 220.

3 is a cross-sectional view illustrating a semiconductor package in which two substrates are bonded by a ball-to-post method according to an embodiment of the present invention. The I / O of each of the lower substrate 310 and each of the I / And a ball-to-post connection.

3, a ball formed on the lower substrate 310 may be defined as a lower conductive bump, and a post formed on the extension substrate 320 may be defined (referred to as a rearranged conductive post). Reference numeral 313 denotes a bonding member for bonding (fixing) between a semiconductor die formed on the lower substrate 310 and a lower portion of the extension substrate 320.

4 is a cross-sectional view illustrating a semiconductor package in which two substrates are bonded in a post-to-ball manner according to an embodiment of the present invention. The I / O of each of the lower substrate 410 and each of the I / The structure shown in the post-to-ball connection is shown as an example.

4, a post formed on the lower substrate 410 may be defined (named) as a lower conductive post, and a ball formed on the extending substrate 420 may be defined as a rearranged conductive bump. 4 shows an adhesive member for adhering (fixing) between a semiconductor die formed on the lower substrate 410 and a lower part of the extension substrate 420.

5 is an exemplary sectional view illustrating a semiconductor package in which two substrates are adhered in a post-to-post manner according to the present invention. The I / O of each of the lower substrate 510 and each of the I / And a post-to-post connection.

5, a post formed on the lower substrate 510 may be defined (named) as a lower conductive post, and a post formed on the extending substrate 520 may be defined as a rearranged conductive post. Reference numeral 513 denotes a bonding member for bonding (fixing) between a semiconductor die formed on the lower substrate 510 and a lower portion of the extension substrate 520.

2 to 4, the ball may be a solder ball or a copper ball coated with solder on its surface, and the post may be a conductive post such as a copper post or the like.

6A to 6E are process flow diagrams illustrating a main process of fabricating a semiconductor package according to an embodiment of the present invention.

6A, a semiconductor die 111 is mounted on a lower substrate 110, that is, each of the connection pads (not shown) on the substrate and each corresponding chip pad (not shown) of the semiconductor die 111 are brought into contact with each other A semiconductor die 111 is attached and a plurality of lower conductive bumps 112, e.g., solder balls, or copper balls coated with solder on the surface, are formed on the other connection pads of the lower substrate 110.

6B, an adhesive member 113 such as a lamination film, a thermosetting liquid adhesive, an NCF adhesive or the like is formed on the semiconductor die 111, and a plurality of relocations I (Prepared for adhesion to the lower substrate) of the extension substrate 120 on which a plurality of rearranging conductive bumps (not shown) for / O are formed. Here, a plurality of relocation I / Os may mean I / O for relocating a plurality of lower I / Os.

Thereafter, each of the rearrangement connection bumps (or rearrangement conductive bumps) of the extension substrate 120 is brought into contact with the corresponding lower conductive bump 112 of the lower substrate 110, and a part of the lower portion of the expansion substrate 120 is bonded The lower substrate 110 and the extending substrate 120 are physically bonded to each other as shown in FIG. 6C, for example, by performing a reflow and bonding process after aligning the upper substrate 110 and the lower substrate 110 to align with the member 113. At this time, the upper part of the semiconductor die 111 and the lower part of the extension substrate 120 are physically adhered (fixed) by the adhesive member 113.

6D, the semiconductor die 111 and the plurality of lower conductive bumps 112, which are formed between the lower substrate 110 and the extension substrate 120, Is embedded in the mold member (130). Here, a semiconductor die and an upper substrate on which a plurality of conductive bumps are formed may be stacked on the extension substrate 120 through a series of subsequent steps.

Finally, by performing a ball drop and reflow process or the like, as shown in FIG. 6E, a plurality of connection pads formed on the lower side of the lower substrate 110 are physically / electrically connected to a board (not shown) Thereby forming a plurality of conductive bumps 114 for connection respectively.

6, the semiconductor die formed between the lower substrate and the extension substrate and the plurality of lower conductive bumps are filled with the mold member (Fan in PoP structure). However, the present invention is not necessarily limited thereto However, the present invention is not limited thereto, and it goes without saying that the present invention can be similarly applied to a package structure in which a mold member is not formed (a package structure in which a mold member is not inserted between two substrates).

7A to 7E are process flow diagrams illustrating a main process of fabricating a semiconductor package according to another embodiment of the present invention.

7A, a semiconductor die 111 is attached to a target position of the lower surface of the extension substrate 120 using an adhesive member 113, that is, a chip pad of the semiconductor die 111 is attached to the extension substrate 120 And a plurality of lower conductive bumps 112, for example, solder balls or copper balls having a surface coated with solder, are formed on the other connection pads of the extension substrate 120, . Here, the adhesive member 113 may be any one of, for example, a laminate film, a thermosetting liquid adhesive, and an NCF adhesive.

Since the lower conductive bump 112 is formed on the extension substrate 120, not on the lower substrate 110, the rear conductive bump 112 is formed on the extension conductive bump, that is, the rear conductive bump 112 for the plurality of rearrangement I / . ≪ / RTI >

Next, as shown in FIG. 7B, the lower substrate 110 having the lower connection bumps for the plurality of lower I / Os is prepared, and the prepared lower substrate 110 and the expansion substrate 120 are aligned with the target (The target position for adhesion to the lower substrate).

Each of the lower conductive bumps 112 of the extension substrate 120 and the corresponding lower connection bumps of the lower substrate 110 are brought into contact with each other so that the chip pads formed on the semiconductor die 111 are electrically connected to the wiring layers (Not shown). Then, the lower substrate 110 and the extension substrate 120 are physically adhered to each other, for example, as shown in FIG.

The semiconductor die 111 formed between the lower substrate 110 and the extension substrate 120 and the plurality of lower conductive bumps 112 are formed as shown in FIG. Is embedded in the mold member (130). Here, a semiconductor die and an upper substrate on which a plurality of conductive bumps are formed may be stacked on the extension substrate 120 through a series of subsequent steps.

Finally, by performing the ball drop and reflow process or the like, as shown in FIG. 7E, a plurality of connection pads formed on the lower side of the lower substrate 110 are physically / electrically connected to a board (not shown) Thereby forming a plurality of conductive bumps 114 for connection respectively.

7, the semiconductor die formed between the lower substrate and the extension substrate and the plurality of lower conductive bumps (or rearrangement conductive bumps) are filled with the mold member. However, the invention of this embodiment is not necessarily limited thereto It is needless to say that the present invention is also applicable to a package structure in which a mold member is not formed as in the embodiment of FIG.

8A to 8E are process flow diagrams illustrating a main process of fabricating a semiconductor package according to another embodiment of the present invention.

8A, a semiconductor die 111 is mounted on a lower substrate 110, that is, a semiconductor die 111 is mounted on a semiconductor chip 111 such that each connection pad (not shown) on the substrate and each corresponding chip pad (not shown) A semiconductor die 111 is attached and a plurality of lower conductive bumps 112, e.g., solder balls, or copper balls coated with solder on the surface, are formed on the other connection pads of the lower substrate 110.

8B, the semiconductor die 111 and the plurality of lower conductive bumps 112 formed on the lower substrate 110 are completely filled with the mold member 130 by performing the molding process Landfill.

The strip grinding process is performed again to expose the upper portions of the upper and lower conductive bumps 112 of the semiconductor die 111 as shown in Fig. 8C as an example by removing the surface of the mold member 130 smoothly .

8 (d), an adhesive member 113 such as an adhesive member such as a laminate film, a thermosetting liquid adhesive, an NCF adhesive, or the like is formed on the semiconductor die 111, and a plurality of relocations I (Prepared for adhesion to the lower substrate) on which the plurality of rearrangement connective bumps (or rearrangement conductive bumps) for O / I are formed. Here, a plurality of relocation I / Os may mean I / O for relocating a plurality of lower I / Os.

Each of the rearrangement connection bumps of the extension substrate 120 and the corresponding lower conductive bump 112 of the lower substrate 110 are in contact with each other and a part of the lower portion of the extension substrate 120 is brought into contact with the adhesive member 113 Then, the lower substrate 110 and the extension substrate 120 are physically bonded to each other, for example, as shown in FIG. 8E by performing a reflow and bonding process. At this time, the upper part of the semiconductor die 111 and the lower part of the extension substrate 120 are physically adhered (fixed) by the adhesive member 113. Here, a semiconductor die and an upper substrate on which a plurality of conductive bumps are formed may be stacked on the extension substrate 120 through a series of subsequent steps.

Finally, by performing the ball drop and reflow process or the like, as shown in FIG. 8E, a plurality of connection pads formed on the lower end of the lower substrate 110 are physically / electrically connected to a board (not shown) Thereby forming a plurality of conductive bumps 114 for connection respectively.

8, the semiconductor die formed between the lower substrate and the extension substrate and the plurality of lower conductive bumps are filled with the mold member. However, the invention of this embodiment is not necessarily limited thereto, The present invention is applicable to a package structure in which a mold member is not formed as in the embodiments of FIGS. 6 and 7.

9A to 9E are process flow diagrams illustrating a main process of fabricating a semiconductor package according to another embodiment of the present invention.

9A, a semiconductor die 111 is attached to a target position of the lower surface of the extension substrate 120 using an adhesive member 113, that is, a chip pad of the semiconductor die 111 is attached to the extension substrate 120 And a plurality of lower conductive bumps 112, for example, solder balls or copper balls having a surface coated with solder, are formed on the other connection pads of the extension substrate 120, . Here, the adhesive member 113 may be any one of, for example, a laminate film, a thermosetting liquid adhesive, and an NCF adhesive.

Since the lower conductive bump 112 is formed on the extension substrate 120, not on the lower substrate 110, the rear conductive bump 112 is formed on the extension conductive bump, that is, the rear conductive bump 112 for the plurality of rearrangement I / . ≪ / RTI >

9B, the semiconductor die 111 formed on the lower surface of the extension substrate 120 and the plurality of lower conductive bumps 112 (or the rearrangement conductive bumps) 112 ) Is completely embedded in the mold member 130.

The lower surface of the chip pads formed on the semiconductor die 111 and the lower surface of the lower conductive bump 130 may be removed by performing the strip grinding process again to flatten the surface of the mold member 130. As a result, 112 (lower portion).

Next, as shown in FIG. 9D, for example, a lower substrate 110 having a plurality of lower connection bumps for a lower I / O is prepared, a prepared lower substrate 110 and a substrate 120 (The target position for adhesion to the lower substrate).

Each of the lower conductive bumps 112 of the extension substrate 120 and the corresponding lower connection bumps of the lower substrate 110 are brought into contact with each other so that the chip pads formed on the semiconductor die 111 are electrically connected to the wiring layers (Not shown). Then, the lower substrate 110 and the extending substrate 120 are physically adhered to each other, for example, as shown in FIG. 9E by performing an adhesion process or the like. Here, a semiconductor die and an upper substrate on which a plurality of conductive bumps are formed may be stacked on the extension substrate 120 through a series of subsequent steps.

Finally, by performing a ball drop and reflow process or the like, a plurality of connection pads formed on the lower side of the lower substrate 110 are physically / electrically connected to a board (not shown) Thereby forming a plurality of conductive bumps 114 for connection respectively.

9, the semiconductor die formed between the lower substrate and the extension substrate and the plurality of lower conductive bumps (or rearrangement conductive bumps) are filled with the mold member. However, the invention of this embodiment is not necessarily limited thereto It is needless to say that the present invention is also applicable to a package structure in which a mold member is not formed as in the embodiments of FIGS.

On the other hand, in the fabrication examples of the present invention shown in FIGS. 6 to 9, the two bumps are electrically connected to each other by using one ball of conductive bumps. However, the present invention is not limited thereto, As shown in FIGS. 2 to 5, the present invention can be similarly applied to a package structure in which two substrates are electrically connected through a ball-to-ball method, a ball-to-post method, a post-to- Of course.

Although the embodiments of the present invention have been described for each individual package element, the present invention is not necessarily limited to this. However, the present invention is not necessarily limited to this, and an adhesive member may be applied to a substrate base having a plurality of sub- It is also possible to fabricate the substrates by attaching the substrates to each other and then sowing them in units of individual package elements.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is easy to see that this is possible. That is, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the present invention.

Therefore, the scope of protection of the present invention should be construed in accordance with the following claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

110: lower substrate 111: semiconductor die
112: lower conductive bump 113: bonding member
114: conductive bump 120: extension board
130: mold member

Claims (7)

delete delete delete delete delete Bonding a semiconductor die 111 on which a chip pad is formed to a lower surface of the extension substrate 120 using an adhesive member 113,
Forming a plurality of relocation conductive bumps (112) for a plurality of relocation I / Os at predetermined positions on the extension substrate (120)
Molding the mold member 130 in such a manner that a chip pad of the semiconductor die 111 and a lower portion of the rearrangement conductive bump 112 are exposed;
Preparing a substrate 110 having a projecting bottom connection bump 110a for a plurality of lower I / Os and a wiring layer on the upper surface thereof,
And the semiconductor chip 111 is brought into contact with the wiring layer of the substrate 110 so that the semiconductor chip 111 is brought into contact with the interconnection layer of the substrate 110, The process of bonding the substrate 120 to the substrate 110
≪ / RTI >
The method according to claim 6,
The molding process includes:
Filling the semiconductor die and the rearrangement conductive bump with the mold member;
Exposing the chip pads of the semiconductor die and the lower portion of the rearranged conductive bumps through strip grinding
≪ / RTI >

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