KR101614769B1 - Array Substrate for Liquid Crystal Display Device and Manufacturing Method of the same - Google Patents

Abstract

An array substrate for a liquid crystal display according to the present invention includes: a gate wiring extending in a first direction on a substrate; a pixel region extending in a second direction on the substrate and defining the pixel region together with the gate wiring; A source electrode extending in the data line, a first ohmic contact layer sequentially stacked on the source electrode, a semiconductor layer including an active layer and a second ohmic contact layer, A drain electrode of the gate electrode, a gate insulating film above the drain electrode and the gate wiring, a gate electrode which is located above the gate insulating film and which is connected to the gate wiring and which overlaps a side surface of the semiconductor layer, A data connection pattern which intersects and is connected to adjacent data lines along the second direction, Located in the region, located on the pixel electrode, and the pixel area to be electrically connected to the drain electrode, and includes a common electrode which is disposed above the pixel electrode and the offset.

Thin Film Transistor, Parasitic Capacity, Process Water, Mask

Description

[0001] The present invention relates to an array substrate for a liquid crystal display device,

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same.

Description of the Related Art [0002] A liquid crystal display device is a display device using optical anisotropy and polarization properties of a liquid crystal, and is widely used in a display portion of a portable electronic device, a computer monitor, or a television.

Liquid crystals have a long and elongated molecular structure, and they have a directionality in orientation. When placed in an electric field, the orientation of molecules is changed according to their size and direction. Therefore, the liquid crystal display device includes a liquid crystal panel in which a liquid crystal layer is positioned between two substrates, and electric field generating electrodes are formed on either or both of the substrates. Through the change of the electric field generated between the two electrodes, And various images are displayed by changing the light transmittance accordingly.

Generally, a liquid crystal display includes a color filter substrate on which an array substrate and a color filter are formed, on which a plurality of wirings and switching elements are formed. An array substrate of a liquid crystal display is formed by repeating a photolithographic process in which a thin film is deposited and a thin film is patterned using a mask. Usually, the number of masks represents the number of steps for manufacturing the array substrate, and the conventional array substrate has been manufactured by using five to six masks. The photolithography process includes various processes such as cleaning, photoresist application, exposure and development, and etching. This shortens the photolithography process by one time, significantly reducing manufacturing time and reducing manufacturing costs. In addition, the probability of failure can be reduced. Therefore, attempts have been made to reduce the manufacturing process and cost by manufacturing an array substrate by reducing the number of masks.

In order to reduce the number of masks, a method of manufacturing an array substrate by a 4-mask process has been proposed.

FIGS. 1A to 1F are diagrams for explaining a method of manufacturing an array substrate by the conventional four-mask process, and show cross-sectional views of the array substrate in each step.

As shown in FIG. 1A, a metal material is deposited on an insulating substrate 10 and then patterned through a first mask process to form a gate wiring 22 and a gate electrode 24.

A gate insulating film 30, a pure amorphous silicon layer 40, an impurity amorphous silicon layer 50, and a metal layer 60 are formed on the gate wiring 22 and the gate electrode 24, as shown in FIG. 1B do. Next, a photoresist layer is formed, and then the photosensitive film is exposed and developed using a mask to form a first photosensitive pattern 90 on the metal layer 60. The first photosensitive pattern 90 includes a first pattern 90a and a second pattern 90b. The first pattern 90a is located corresponding to the source and drain electrodes to be formed later and the data wiring and the storage electrode and the second pattern 90b is located between the source and drain electrodes, that is, the gate electrode 24 . The thickness of the second pattern 90b is smaller than that of the first pattern 90a. Here, the mask used includes a blocking portion for blocking light, a transmissive portion for transmitting light, and a semi-transmissive portion for partially transmitting light, and the transflective portion corresponds to the second pattern 90b. The semi-transmissive portion may include a slit or a semi-transmissive film. These masks are also referred to as half tone masks.

As shown in Fig. 1C, the metal layer (60 in Fig. 1B), the impurity amorphous silicon layer (50 in Fig. 1B) and the pure amorphous silicon layer (also shown in Fig. 1B) are patterned using the first and second patterns 90a and 90b as an etching mask 1b < / RTI > 40) are sequentially removed. An active layer 42, an ohmic contact pattern 52a and a source drain pattern 60a are formed on the gate electrode 24 and a pure amorphous silicon pattern 44 and impurity amorphous silicon A pattern 54 and a capacitor electrode 66 are formed.

Next, the second pattern 20b is removed to expose the source / drain pattern 62a above the gate electrode 24. Next, At this time, the first pattern 90a is also partially removed to reduce its thickness, and the edges of the source drain pattern 60a and the capacitor electrode 66 under the first pattern 90a are exposed.

1D, the exposed source drain pattern (60a in FIG. 1C) and the underlying ohmic contact pattern (52a in FIG. 1C) on the gate electrode 24 are removed so that the source and drain electrodes 62, 64 and the ohmic contact layer 52 are formed and the active layer 42 of the source and drain electrodes 62, 64 is exposed. At this time, the edges of the source drain pattern (60a in Fig. 1C), the ohmic contact pattern (52a in Fig. 1C), the capacitor electrode 66 and the impurity amorphous silicon pattern 52 are also removed, and the active layer 42 and pure amorphous The edges of the silicon pattern 44 are exposed.

Then, the remaining first pattern 90a is removed.

Thus, the source and drain electrodes 62 and 64 and the capacitor electrode 66, the ohmic contact layer 52, and the active layer 42 are formed through the second mask process. At this time, although not shown, a data line connected to the source electrode 62 is formed, and another impurity amorphous silicon pattern and a pure amorphous silicon pattern are formed under the data line. In addition, the edge of the pure amorphous silicon pattern under the data line is exposed.

The source and drain electrodes 62 and 64 and the active layer 42 and the ohmic contact layer 52 and the gate electrode 24 constitute a thin film transistor and the active layer 42 between the source and drain electrodes 62 and 64, Is a channel of the thin film transistor.

A protective layer 70 is formed on the source and drain electrodes 62 and 64 and the capacitor electrode 66 and the protective layer 70 is patterned through a third mask process as shown in FIG. The drain contact hole 72 exposing the drain electrode 64 and the storage contact hole 74 exposing the capacitor electrode 66 are formed.

Next, as shown in FIG. 1F, a transparent conductive material is deposited on the passivation layer 70 and then patterned through a fourth mask process to form the pixel electrode 82. The pixel electrode 82 is connected to the drain electrode 64 through the drain contact hole 72 and to the capacitor electrode 66 through the storage contact hole 74.

Here, the gate wiring 22 and the capacitor electrode 66 overlap each other and constitute the storage capacitor Cst with the gate insulating film 30 therebetween as a dielectric.

Thus, the array substrate can be manufactured by the four-mask process.

Further, in order to further reduce the number of mask processes, a method of manufacturing an array substrate by a three mask process using a liftoff method has been proposed.

2A to 2E are diagrams for explaining a method of manufacturing an array substrate by a conventional three-mask process, and show cross-sectional views of the array substrate in each step. Here, the array substrate has a structure similar to that of the array substrate by the above-mentioned four-mask process, and the same reference numerals are used for the same portions.

As shown in FIG. 2A, a metal material is deposited on the insulating substrate 10 and then patterned through a first mask process to form the gate wiring 22 and the gate electrode 24.

A gate insulating film 30 is formed on the gate wiring 22 and the gate electrode 24 and an active layer 42 and an ohmic contact layer 62, (62, 64), and a capacitor electrode (66). Here, the active layer 42, the ohmic contact layer 62, the source and drain electrodes 62 and 64, and the capacitor electrode 66 are formed through the second mask process previously mentioned in FIGS. 1B to 1D. At this time, the impurity amorphous silicon pattern 54 and the pure amorphous silicon pattern 44 are formed under the capacitor electrode 66, and the edges of the active layer 42 and the pure amorphous silicon pattern 44 are exposed.

On the other hand, a data line connected to the source electrode 62 is formed through a second mask process, and another impurity amorphous silicon pattern and a pure amorphous silicon pattern are formed under the data line. In addition, the edge of the pure amorphous silicon pattern under the data line is exposed.

A protective layer 70 is formed on the source and drain electrodes 62 and 64 and the storage electrode 66, as shown in FIG. 2C. Next, a photoresist layer is formed on the protective layer 70, and exposed and developed to form a second photoresist pattern 92. The protective layer 70 is patterned using the second photoresist pattern 92 as an etching mask so that the drain electrode 64 and the capacitor electrode 66 are partially exposed and the gate insulating film 30 As shown in FIG.

2D, a transparent conductive material is deposited on the substrate 10 including the photosensitive pattern 92, and a pixel electrode 80 is formed on the gate insulating film 30 exposed in the pixel region . The pixel electrode 80 is in contact with the exposed drain electrode 64 and the capacitor electrode 66. At this time, a transparent conductive material layer 82a is also formed on the photosensitive pattern 92. [

As shown in Fig. 2E, the photosensitive pattern (92 in Fig. 2D) and the transparent conductive material layer (82a in Fig. 2D) on the upper portion thereof are removed by a lift-off method.

Thus, the protective layer 70 and the pixel electrode 80 are formed through the third mask process.

Here, the gate wiring 22 and the capacitor electrode 66 overlap each other and constitute the storage capacitor Cst with the gate insulating film 30 therebetween as a dielectric.

Thus, the array substrate for a liquid crystal display can be manufactured by a three-mask process.

In the conventional array substrate manufactured by the 4-mask process or the 3-mask process, a pure amorphous silicon pattern is formed under the data line, so that a light leakage current is generated in the pure amorphous silicon pattern. Accordingly, a coupling capacitance is generated between the pure amorphous silicon pattern and the adjacent pixel electrode 82, resulting in an abnormal arrangement of the liquid crystal molecules. Therefore, wavy noise occurs in which a thin line of a wave pattern appears on the screen.

In addition, the source electrode 62 overlaps with the gate electrode 24 and a parasitic capacitance is generated. This parasitic capacitance causes a voltage drop of the pixel voltage charged in the pixel electrode 82. That is, a data signal is applied to the pixel electrode 82 to be charged to the pixel voltage, and the charged pixel voltage must maintain a constant value until the next signal is applied. However, the pixel voltage is reduced by the parasitic capacitance, which causes the image to be distorted. In the conventional array substrate for a liquid crystal display, since the overlapping area of the source electrode 62 and the gate electrode 24 is large, the parasitic capacitance is large. The capacitance of the storage capacitor Cst can be increased to reduce the voltage drop. In this case, the area of the capacitor electrode 66 and the gate wiring 22 overlapping with the capacitor electrode 66 must be increased.

In addition, since the pure amorphous silicon pattern 44 whose edge is exposed is formed under the capacitor electrode 66, the distance between the two electrodes is increased, and the area of the capacitor electrode 66 is reduced. Therefore, the capacitance of the storage capacitor Cst becomes small. However, in order to obtain a sufficient capacitance, the area of the capacitor electrode 66 must be increased.

Further, the channel length is increased by the mask process using the halftone mask, and the size of the thin film transistor is increased. As a result, the aperture ratio is lowered.

In addition, in the conventional three-mask process, the lift-off method has a somewhat lower yield and has a problem of reducing the degree of freedom of design.

On the other hand, the above-mentioned liquid crystal display device including the array substrate has a structure in which the color filter substrate on which the common electrode is formed is arranged on the array substrate and the liquid crystal layer is positioned between the two substrates. In such a liquid crystal display device, the liquid crystal molecules of the liquid crystal layer are driven by a vertical electric field generated between the two substrates. However, such a vertical electric field type liquid crystal display device is disadvantageous in that the viewing angle is narrow. Therefore, in order to improve the viewing angle, a horizontal electric field type liquid crystal display device parallel to the substrate has been proposed.

An object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same that can reduce the manufacturing process and cost.

It is still another object of the present invention to provide an array substrate for a liquid crystal display device and a method of manufacturing the same that can improve the aperture ratio and prevent the occurrence of the way noise.

Another object of the present invention is to provide an array substrate for a liquid crystal display device and a manufacturing method thereof that can minimize the generation of parasitic capacitance.

Another object of the present invention is to provide an array substrate for a liquid crystal display device capable of improving process yield and a manufacturing method thereof.

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display, including: a gate line extending in a first direction on a substrate; and a gate line extending in a second direction on the substrate, A first ohmic contact layer that is sequentially stacked and located over the source electrode, a data line that is located between adjacent gate lines, a source electrode that extends from the data line, and an active layer and a second ohmic contact layer A gate electrode overlying the gate electrode, a gate electrode overlying the gate electrode, a gate electrode overlying the gate electrode, a gate electrode overlying the gate electrode, a gate electrode overlying the gate electrode, And is connected to adjacent data lines along the second direction intersecting the gate line A data connection pattern, located in the pixel region, located in the pixel electrode, and the pixel area to be electrically connected to the drain electrode, and includes a common electrode which is disposed above the pixel electrode and the offset.

The array substrate includes a first capacitor electrode formed on the substrate and connected to the common electrode, a second capacitor electrode formed on the gate insulating film and connected to the drain electrode, the second capacitor electrode overlapping the first capacitor electrode, .

Here, the pixel electrode and the common electrode are formed of the same material as the gate electrode above the gate insulating film.

Wherein the pixel electrode includes first and second pixel electrode patterns extending in parallel with the data line and extending from the second capacitor electrode, the common electrode includes first to third common electrode patterns parallel to the data line, And a fourth common electrode pattern which is parallel to the gate wiring and connects the first to third common electrode patterns.

A second auxiliary common electrode extending from the first capacitor electrode is formed on the same layer of the same material as the gate wiring, the auxiliary common electrode includes a first auxiliary common electrode pattern overlapping the first common electrode pattern, A second auxiliary common electrode pattern overlapping the third common electrode pattern, and a third auxiliary common electrode pattern overlapping the fourth common electrode pattern.

Alternatively, the pixel electrode and the common electrode may be formed on the same layer with the same material as the gate wiring and the data wiring.

Here, the gate line and the data line have a double layer structure of a first conductive material and a second conductive material, and the pixel electrode and the common electrode have a single layer structure of the first conductive material.

Further, the gate insulating film has an opening for exposing the pixel electrode and the common electrode.

Wherein the pixel electrode includes first and second pixel electrode patterns parallel to the data lines and a third pixel electrode pattern connecting the first and second pixel electrode patterns, And the first to third common electrode patterns are parallel and extend from the first capacitor electrode.

A common electrode connection pattern is formed on the gate insulating layer so as to be in contact with the common electrodes of adjacent pixel regions.

Further, a common wiring which is parallel to the gate wiring and is connected to the common electrode is further formed.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display, comprising: forming a gate wiring extending in a first direction on a substrate; Forming a data line extending between adjacent gate wirings; forming a source electrode extending in the data line; forming a first ohmic contact layer sequentially stacked on the source electrode, Forming a semiconductor layer including a first ohmic contact layer and a second ohmic contact layer on the semiconductor layer; forming a drain electrode on the semiconductor layer; forming a gate insulating film on the drain electrode and the gate wiring; Forming a gate electrode connected to the gate wiring and overlapping a side surface of the semiconductor layer, Forming a data connection pattern that intersects the gate line and is connected to adjacent data lines along the second direction; forming a pixel electrode electrically connected to the drain electrode in the pixel region; And forming a common electrode alternating with the pixel electrode.

Here, the step of forming the drain electrode, the step of forming the semiconductor layer, the step of forming the source electrode, and the step of forming the data line are performed in the same photolithography process.

At this time, the photolithography process uses a mask including a transmissive portion, a transflective portion, and a blocking portion, and the transflective portion corresponds to the data wiring.

The method includes forming a first capacitor electrode on the substrate, the first capacitor electrode being connected to the common electrode, a second capacitor connected to the drain electrode and overlapping the first capacitor electrode, And forming an electrode.

Here, the step of forming the pixel electrode, the step of forming the common electrode, and the step of forming the gate electrode are performed in the same step.

Alternatively, the step of forming the pixel electrode, the step of forming the common electrode, the step of forming the gate wiring, and the step of forming the data wiring are performed in the same step.

In the array substrate for a liquid crystal display according to the present invention, the channel of the thin film transistor is formed along a direction substantially perpendicular to the substrate. Therefore, the channel length, that is, the distance between the source and drain electrodes is short, and the thin film transistor can be designed to be small. Thus, the aperture ratio can be increased.

In addition, since the overlapping area of the source electrode and the gate electrode can be minimized, the parasitic capacitance can be reduced and the voltage drop can be minimized. Therefore, it is not necessary to increase the area of the storage capacitor, and the aperture ratio can be prevented from lowering.

In addition, since only the gate insulating film exists between the first and second capacitor electrodes, the storage capacity can be maintained even if the area of the storage capacitor is reduced. Therefore, the aperture ratio can be increased.

Further, since the pure amorphous silicon pattern is not disposed under the data line or the first capacitor electrode, it is possible to solve such problems as a light leakage current, a ratio noise, and a reduction in the aperture ratio.

In addition, since it can be manufactured by the three-mask process, the number of processes can be reduced, the defect occurrence rate can be lowered, the productivity can be improved, and the cost can be reduced have.

In addition, since the liftoff method is not used, the process yield can be improved as compared with the conventional method of manufacturing the array substrate by the 3-mask process.

In addition, when the pixel electrode and the common electrode are formed on the same layer with the same material as the gate wiring, the gate insulating film is not formed in the pixel region where the liquid crystal is driven, and the transmittance can be improved. In this case, since the data connection pattern and the common electrode connection pattern above the gate insulating layer can be formed thick, the resistance of the connection between the data line and the common electrode can be minimized.

Hereinafter, an array substrate for a liquid crystal display according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a plan view showing an array substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along lines IVA-IVA, IVB-IVB and IVC- Sectional view.

As shown in FIGS. 3 and 4, a gate wiring 122 is formed on a substrate 110 along a first direction, and a data wiring 132 is formed along a second direction crossing the first direction . The gate wiring 122 and the data wiring 132 define a pixel region. The data line 132 is composed of discrete patterns corresponding to each pixel region, and each pattern is located between the adjacent gate lines 122. A gate pad 124 is formed at one end of the gate wiring 122. A data pad 134 is formed at one end of the data wiring 132 and more specifically at one end of the first pattern of the data wiring 132 have. And the source electrode 136 extends in the first direction in the pattern of the data line 132 corresponding to each pixel region.

A first capacitor electrode 146 is formed adjacent to the source electrode 136 on the substrate 110 of each pixel region and an auxiliary common electrode 148 connected to the first capacitor electrode 146 is formed. The auxiliary common electrode 148 includes first, second and third auxiliary common electrode patterns 148a, 148b and 148c. One end of the first and second auxiliary common electrode patterns 148a and 148b is connected to the third auxiliary common electrode pattern 148c and the other end of the first and second auxiliary common electrode patterns 148a and 148b is connected to the first capacitor And is connected to the electrode 146. The first capacitor electrode 146 and the first to third auxiliary common electrode patterns 148a, 148b and 148c are integrally formed to have a closed loop structure corresponding to the shape of the pixel region.

A semiconductor layer 142 is formed on the source electrode 136 and a drain electrode 144 is formed on the semiconductor layer 142. Although not shown, the semiconductor layer 142 includes a first ohmic contact layer of amorphous silicon doped with impurities, an active layer of pure amorphous silicon that is not doped with impurities, and a second ohmic contact layer of impurity-doped amorphous silicon sequentially As shown in Fig.

An upper portion of the gate wiring 122, the gate pad 124, the data wiring 132, the data pad 134, the drain electrode 144, the first capacitor electrode 146, (150). The gate insulating film 150 has first to ninth contact holes 150a to 150i. The first contact hole 150a corresponds to the gate wiring 122, the second contact hole 150b corresponds to the drain electrode 144, the third contact hole 150c corresponds to the gate pad 124 and the fourth contact hole The fifth contact hole 150e and the sixth contact hole 150f correspond to both ends of each pattern of the data line 132 and the seventh contact hole 150g corresponds to the first capacitor electrode 150b. And the eighth contact hole 150h and the ninth contact hole 150i partially expose both ends of the third auxiliary common electrode pattern 148c.

A gate electrode 162, a second capacitor electrode 164, a data connection pattern 138, a pixel electrode 166, a common electrode 168, a gate pad terminal 172, and a data pad terminal 172 are formed on the gate insulating film 150. (Not shown).

The gate electrode 162 contacts the gate wiring 122 through the first contact hole 150a and overlaps the side surface of the semiconductor layer 142. [ The gate electrode 162 overlaps the side surfaces of the source electrode 136 and the drain electrode 144 and partially overlaps the upper surface of the drain electrode 144. [ The gate electrode 162, the source electrode 136, the semiconductor layer 142, and the drain electrode 144 constitute a thin film transistor T. [ The side surface of the semiconductor layer 142 located between the source and drain electrodes 136 and 144 forms a channel of the thin film transistor T. [

And the second capacitor electrode 164 contacts the drain electrode 144 through the second contact hole 150b. The second capacitor electrode 164 overlaps the first capacitor electrode 146 to form a storage capacitor Cst.

The data connection pattern 138 overlaps the patterns of the data wiring 132 of the adjacent pixel region in the direction intersecting with the gate wiring 122. [ The data connection pattern 138 is in contact with the patterns of the data wiring 132 of the adjacent pixel region through the fifth and sixth contact holes 150e and 150f. At this time, the width of the portion of the gate wiring 122 intersecting with the data connection pattern 138 may be smaller than the other portion.

The pixel electrode 166 and the common electrode 168 are located within the pixel region. The pixel electrode 166 includes first and second pixel electrode patterns 166a and 166b and the first and second pixel electrode patterns 166a and 166b are formed on the second capacitor electrode 164 along the second direction . The first and second pixel electrode patterns 166a and 166b and the second capacitor electrode 164 are integrally formed.

The common electrode 168 includes the first to fourth common electrode patterns 168a, 168b, 168c, and 168d. The first to third common electrode patterns 168a, 168b and 168c extend in the second direction in the fourth common electrode pattern 168d and are staggered from the first and second pixel electrode patterns 166a and 166b. For example, the first pixel electrode pattern 166a is located between the first and second common electrode patterns 168a and 168b, and the second pixel electrode pattern 166b is located between the second and third common electrode patterns 168b and 168c . The first common electrode pattern 168a is located between the data line 132 and the first pixel electrode pattern 166a and the third common electrode pattern 168c is located between the second pixel electrode pattern 166b and another data And the wiring 132. The first and third common electrode patterns 168a and 168c partially overlap with the first and second auxiliary common electrode patterns 148a and 148b. The fourth common electrode pattern 168d is formed along the first direction and extends to the adjacent pixel region. The fourth common electrode pattern 168d overlaps the third auxiliary common electrode pattern 148c and is formed through the eighth and ninth contact holes 150h and 150i 3 auxiliary common electrode pattern 148c. The third common electrode pattern 168c overlaps the first capacitor electrode 146 through the seventh contact hole 150g. The seventh contact hole 150g is formed on the second auxiliary common electrode pattern 148b and the third common electrode pattern 168c is electrically connected to the second auxiliary common electrode pattern 148b through the seventh contact hole 150g. ). ≪ / RTI > And the third common electrode pattern 168c may extend to the adjacent pixel region along the second direction.

The first and second pixel electrode patterns 166a and 166b and the first to third common electrode patterns 168a to 168c and the first and second auxiliary common electrode patterns 148a and 148b are connected to the data line 132, And has at least one bent portion.

The gate pad terminal 172 contacts the gate pad 124 through the third contact hole 150c and the data pad terminal 174 contacts the data pad 134 through the fourth contact hole 150d.

In the array substrate for a liquid crystal display according to the first embodiment of the present invention, the channel of the thin film transistor T is formed along a direction substantially perpendicular to the substrate 110. Therefore, the length of the channel, that is, the distance between the source and drain electrodes 136 and 144 is short, and the thin film transistor T can be designed to be small. Thus, the aperture ratio can be increased.

In addition, since the overlapping area of the source electrode 136 and the gate electrode 162 can be minimized, the parasitic capacitance can be reduced and the voltage drop can be minimized. Therefore, it is not necessary to increase the area of the storage capacitor Cst, and it is possible to prevent the aperture ratio from being lowered.

In addition, since the gate insulating film 150 exists only between the first and second capacitor electrodes 146 and 164, the storage capacity can be maintained even if the area of the storage capacitor Cst is reduced. Therefore, the aperture ratio can be increased.

In addition, since the pure amorphous silicon pattern is not disposed under the data line 132 or the first capacitor electrode 146, problems such as light leakage current, weight ratio noise, and aperture ratio reduction can be solved.

The array substrate for a liquid crystal display according to the first embodiment of the present invention can be manufactured through a three-mask process.

5A to 5F are diagrams for explaining a method of manufacturing an array substrate for a liquid crystal display according to the first embodiment of the present invention, and show cross-sectional views of the array substrate in each step.

5A, a first metal layer 120, a silicon layer 130, and a second metal layer 140 are sequentially formed on a substrate 110. As shown in FIG. Next, a first photosensitive pattern 192 is formed on the second metal layer 140 by forming a photosensitive layer on the second metal layer 140, exposing the photosensitive layer using a mask, and developing the exposed photosensitive layer. The first photosensitive pattern 192 includes a first pattern 192a and a second pattern 192b and a thickness of the second pattern 192b is smaller than the first pattern 192a.

At this time, the mask used includes a blocking portion for blocking light, a transmitting portion for transmitting light, and a semi-transmitting portion for transmitting only a part of light. The blocking portion corresponds to the first pattern 192a, and the transflective portion corresponds to the second pattern 192b. The semi-transmissive portion may include a plurality of slits or semi-transmissive films.

On the other hand, an insulating substrate such as a glass substrate or a plastic substrate can be used as the substrate 110. The first metal layer 120 may be formed of an aluminum alloy such as aluminum or aluminum-neodymium (AlNd), a molybdenum alloy such as molybdenum (Mo), molybdenum-titanium (MoTi), copper (Cu) ), And the like. Although not shown, the silicon layer 130 includes a sequentially stacked impurity amorphous silicon layer, a pure amorphous silicon layer, and an impurity amorphous silicon layer. The second metal layer 140 is formed of a conductive material such as aluminum (Al), an aluminum alloy such as aluminum-neodymium (AlNd), a molybdenum alloy such as molybdenum (Mo), molybdenum-titanium (MoTi), or chrome .

The first and second metal layers 120 and 140 may be formed by a method such as sputtering and the silicon layer 130 may be formed by a method such as chemical vapor deposition.

5A) and the silicon layer (130 in FIG. 5A) and the first metal layer (FIG. 5A) using the first photosensitive pattern (192 in FIG. 5A) as an etching mask, 120) are sequentially removed. Thus, the gate wiring 122, the data wiring 132, the source electrode 136, the gate pad 124, the data pad 134 and the first capacitor electrode 146 are formed on the substrate 110. At this time, a silicon pattern 130a and a metal layer 130 are formed on the gate wiring 122, the data wiring 132, the source electrode 136, the gate pad 124, the data pad 134 and the first capacitor electrode 146, Patterns 140a are sequentially formed. On the other hand, an auxiliary common electrode (148 in FIG. 3) connected to the first capacitor electrode 146 is also formed on the substrate 110, though not shown. Here, the first metal layer (120 in FIG. 5A) can be removed by wet etching, and the second metal layer (140 in FIG. 5A) and the silicon layer (130 in FIG. 5A) can be removed by dry etching.

Subsequently, the second pattern (192b in FIG. 5A) is removed in the same manner as the ashing to form the data line 132 and the gate line 122, the gate pad 124, the data pad 134, Thereby exposing the metal pattern 140a on the electrode 146. [ At this time, the first pattern 192a is partially removed, and its thickness is thinned.

Next, the metal pattern 140a and the silicon pattern 130a are removed using the first pattern 192a as an etching mask, and the remaining first pattern 192a is removed.

5C, a semiconductor layer 142 and a drain electrode 144 are formed on the source electrode 136. In this case, Although not shown, the semiconductor layer 142 includes a first ohmic contact layer of impurity amorphous silicon, an active layer of pure amorphous silicon, and a second ohmic contact layer of impurity amorphous silicon. As described above, the gate wiring 122 and the data wiring 132, the source electrode 136, the gate pad 124, the data pad 134, the first capacitor electrode 146, The drain electrode 136, and the drain electrode 144, respectively.

Next, a gate insulating layer 150 is formed on the substrate 110 including the drain electrode 144. A gate insulating film 150 may be formed by chemical vapor deposition method, it may be an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiO _2).

5D, a photosensitive material is coated on the gate insulating layer 150 to form a photosensitive layer, and then exposed and developed to form a second photosensitive pattern 194 on the gate insulating layer 150. Referring to FIG. Next, the gate insulating layer 150 is selectively removed using the second photoresist pattern 194 as an etching mask to form the first to fourth contact holes 150a to 150d. The first contact hole 150a exposes the gate wiring 122 and the second contact hole 150b exposes the drain electrode 144 while the third contact hole 150c exposes the gate pad 124 , And the fourth contact hole 150d exposes the data pad 134. At this time, the fifth to ninth contact holes 150e to 150i of FIG. 3 are also formed. Here, the gate insulating film 150 can be removed by dry etching.

Then, the second photosensitive pattern 194 is removed.

Thus, the gate insulating film 150 having the first to ninth contact holes 150a to 150i in FIG. 3 is formed through the second mask process.

5E, a third metal layer 160 is formed on the gate insulating layer 150, a photosensitive material is coated on the third metal layer 160, a photosensitive layer is formed on the third metal layer 160, A third photosensitive pattern 196 is formed. The third metal layer 160 may be formed of an aluminum alloy such as aluminum or aluminum-neodymium (AlNd), a molybdenum alloy such as molybdenum (Mo), molybdenum-titanium (MoTi), copper (Cu) And may be formed of a conductive material such as indium tin oxide (ITO) or the like. The third metal layer 160 may be formed through a sputtering method.

As shown in FIG. 5F, the third metal layer (160 in FIG. 5E) is selectively removed using the third photosensitive pattern (196 in FIG. 5E) as an etching mask, and the third photosensitive pattern (196 in FIG. Remove. At this time, the third metal layer (160 in FIG. 5E) may be removed by wet etching.

Therefore, a gate electrode 162, a second capacitor electrode 164, a gate pad terminal 172, a data pad terminal 174, pixel electrodes 166a and 166b, and a common electrode (not shown) are formed on the gate insulating film 150 168b. At this time, though not shown, a data connection pattern (138 in FIG. 3) also occurs. The gate electrode 162 contacts the gate wiring 122 through the first contact hole 150a and overlaps the side surface of the semiconductor layer 142. [ The gate electrode 162 and the source electrode 136, the semiconductor layer 142 and the drain electrode 144 constitute a thin film transistor T. [ The second capacitor electrode 164 contacts the drain electrode 144 through the second contact hole 150b and overlaps the first capacitor electrode 146 to form a storage capacitor Cst. The gate pad terminal 172 contacts the gate pad 124 through the third contact hole 150c and the data pad terminal 174 contacts the data pad 134 through the fourth contact hole 150d. The pixel electrodes 166a and 166b and the common electrode 168b are staggered. More specifically, as shown in FIG. 3, the pixel electrode 166 includes first and second pixel electrode patterns 166a and 166b, and the common electrode 168 includes first to fourth common electrode patterns 166a and 166b. And the first and second pixel electrode patterns 166a and 166b and the first through third common electrode patterns 168a through 168c are staggered.

Therefore, the gate electrode 162, the second capacitor electrode 164, the gate pad terminal 172, the data pad terminal 174, the pixel electrode (shown in FIG. 3) 166, and the common electrode (168 in Fig. 3) can be formed.

As described above, the array substrate for a liquid crystal display according to the first embodiment of the present invention can be manufactured by a three-mask process. Therefore, compared with the conventional method of manufacturing an array substrate by the 4-mask process, the mask process is reduced once, the deposition and etching processes are reduced, and the productivity is improved. For example, the manufacturing method of the array substrate for a liquid crystal display according to the first embodiment of the present invention is reduced by about 25% compared with the conventional manufacturing method using the 4-mask process. Therefore, the defective occurrence rate is lowered and the productivity can be improved.

In addition, since the liftoff method is not used, the process yield can be improved as compared with the conventional method of manufacturing the array substrate by the 3-mask process.

In the first embodiment of the present invention, the pixel electrode and the common electrode are formed on the same layer with the same material as the gate electrode, but the pixel electrode and the common electrode of the present invention are formed on the same layer . The second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 is a plan view showing an array substrate for a liquid crystal display according to a second embodiment of the present invention, and Fig. 7 is a cross-sectional view taken along the line VIIA-VIIA, VIIB-VIIB and VIIC- Sectional view.

6 and 7, a gate wiring 222 is formed on a substrate 210 along a first direction, and a data wiring 232 is formed along a second direction crossing the first direction . The gate wiring 222 and the data wiring 232 define a pixel region. The data line 232 is formed of discrete patterns corresponding to each pixel region, and each pattern is located between the adjacent gate lines 222. A gate pad 224 is formed at one end of the gate wiring 222. A data pad 234 is formed at one end of the data line 232, more specifically, at one end of the first pattern of the data line 232 have. The source electrode 236 is formed in the first direction in the pattern of the data line 232 corresponding to each pixel region. A first capacitor electrode 246 is formed adjacent to the source electrode 236 on the substrate 210 of each pixel region.

The gate wiring 222 and the data wiring 232, the source electrode 236, the gate pad 224, the data pad 234 and the first capacitor electrode 246 are electrically connected to the first conductive material and the second conductive material Layer structure of a conductive material.

On the other hand, a pixel electrode 266 and a common electrode 268 are formed in the pixel region. The pixel electrode 266 includes first to third pixel electrode patterns 266a to 266c. The third pixel electrode pattern 266c extends along the first direction and is located at an upper portion of the pixel region. The first and second pixel electrode patterns 266a and 266b extend from the third pixel electrode pattern 266c in the second direction As shown in FIG.

The common electrode 268 includes first through third common electrode patterns 268a, 268b, and 268c. The first to third common electrode patterns 268a, 268b and 268c extend along the second direction at the first capacitor electrode 246 and are staggered from the first and second pixel electrode patterns 266a and 266b. For example, the first pixel electrode pattern 266a is located between the first and second common electrode patterns 268a and 268b, and the second pixel electrode pattern 266b is located between the second and third common electrode patterns 268b and 268c . The first common electrode pattern 268a is located between the data line 232 and the first pixel electrode pattern 266a and the third common electrode pattern 268c is located between the second pixel electrode pattern 266b and another data line 266b. And is located between the wirings 232.

Here, the first and third common electrode patterns 268a and 268c have protrusions facing each other at one end which is not connected to the first capacitor electrode 246. In addition, the third pixel electrode pattern 266c is located between the protruding portions of the first and third common electrode patterns 268a and 268c.

The pixel electrode 266 and the common electrode 268 may have a single layer structure of the first conductive material.

The first and second pixel electrode patterns 266a and 266b and the first through third common electrode patterns 268a through 268c are parallel to the data line 232 and have at least one bent portion.

A semiconductor layer 242 is formed on the source electrode 236 and a drain electrode 244 is formed on the semiconductor layer 242. Although not shown, the semiconductor layer 242 includes a first ohmic contact layer of an amorphous silicon doped with an impurity, an active layer of pure amorphous silicon not doped with an impurity, and a second ohmic contact layer of an impurity-doped amorphous silicon sequentially As shown in Fig.

A gate insulating film 250 is formed on the gate wiring 222, the gate pad 224, the data wiring 232, the data pad 234, the drain electrode 244, and the first capacitor electrode 246 . The gate insulating film 250 has first to tenth contact holes 250a to 250j. The first contact hole 250a has the gate wiring 222, the second contact hole 250b has the drain electrode 244, the third contact hole 250c has the gate pad 224 and the fourth contact hole The fifth contact hole 250e and the sixth contact hole 250f correspond to both ends of each pattern of the data line 232 and the seventh contact hole 250g corresponds to the second pixel electrode 250d. The eighth contact hole 250h and the ninth contact hole 250i form one end of the third common electrode pattern 268c and the tenth contact hole 250j forms one end of the pattern 266b, And partially exposes one end of the first electrode 268a. Here, the ninth contact hole 250i may be formed to expose one end of the first capacitor electrode 246. The eighth contact hole 250h may be formed to expose the protrusion of the third common electrode pattern 268c and the tenth contact hole 250j may be formed to expose the protrusion of the first common electrode pattern 268a .

A gate electrode 262 and a second capacitor electrode 264, a data connection pattern 238, a common electrode connection pattern 267, a gate pad terminal 272 and a data pad terminal 274 are formed on the gate insulating layer 250 Respectively.

The gate electrode 262 contacts the gate wiring 222 through the first contact hole 250a and overlaps the side surface of the semiconductor layer 242. [ The gate electrode 262 overlaps the side surfaces of the source electrode 236 and the drain electrode 244 and may partially overlap with the upper surface of the drain electrode 244. [ The gate electrode 262 and the source electrode 236, the semiconductor layer 242 and the drain electrode 244 constitute a thin film transistor T. [ The side surface of the semiconductor layer 242 located between the source and drain electrodes 236 and 244 forms a channel of the thin film transistor T. [

And the second capacitor electrode 264 contacts the drain electrode 244 through the second contact hole 250b. The second capacitor electrode 264 overlaps the first capacitor electrode 246 to form a storage capacitor Cst. Also, the second capacitor electrode 264 contacts the second pixel electrode pattern 266b through the seventh contact hole 250g.

The data connection pattern 238 intersects the gate wiring 222 and overlaps the patterns of the data wiring 232 of the adjacent pixel region. The data connection pattern 238 contacts the patterns of the data wiring 232 of the adjacent pixel region through the fifth and sixth contact holes 250e and 250f. At this time, the width of the portion of the gate wiring 222 intersecting with the data connection pattern 238 may be smaller than the other portion.

The common electrode connection pattern 267 has an L shape and crosses the gate wiring 222 and the data wiring 232. The common electrode connection pattern 267 is in contact with the third common electrode pattern 268c through the eighth contact hole 250h and is in contact with the third common Contacts the electrode pattern 268c, and contacts the first common electrode pattern 268a of the adjacent pixel region along the first direction through the tenth contact hole 250j.

The gate pad terminal 272 contacts the gate pad 224 through the third contact hole 250c and the data pad terminal 274 contacts the data pad 234 through the fourth contact hole 250d.

In the array substrate for a liquid crystal display according to the second embodiment of the present invention, the channel of the thin film transistor T is formed along a direction substantially perpendicular to the substrate 210. Therefore, the length of the channel, that is, the distance between the source and drain electrodes 236 and 244 is short, and the thin film transistor T can be designed to be small. Thus, the aperture ratio can be increased.

In addition, since the overlapping area of the source electrode 236 and the gate electrode 262 can be minimized, the parasitic capacitance can be reduced and the voltage drop can be minimized. Therefore, it is not necessary to increase the area of the storage capacitor Cst, and it is possible to prevent the aperture ratio from being lowered.

In addition, since only the gate insulating film 250 exists between the first and second capacitor electrodes 246 and 264, the storage capacity can be maintained even if the area of the storage capacitor Cst is reduced. Therefore, the aperture ratio can be increased.

In addition, since the pure amorphous silicon pattern is not formed under the data line 232 or the first capacitor electrode 246, problems such as light leakage current, weight ratio noise, and aperture ratio can be solved.

In addition, since the gate insulating film 250 is not formed in the pixel region where the liquid crystal is driven, the transmittance can be improved.

Since the pixel electrode 266 and the common electrode 268 are formed on the same layer with the same material as the gate wiring 222 and the data wiring 232, The common electrode connection pattern 267 can be formed thick. Therefore, the resistance of the connection of the data line 232 and the common electrode 268 can be minimized.

The array substrate for a liquid crystal display according to the second embodiment of the present invention can be manufactured through a three-mask process.

8A to 8F are views for explaining a method of manufacturing an array substrate for a liquid crystal display according to a second embodiment of the present invention, and show cross-sectional views of the array substrate in each step.

A first metal layer 220 and a silicon layer 230 and a second metal layer 240 are sequentially formed on a substrate 210 as shown in FIG. Here, the first metal layer 220 has a double layer structure of a lower layer 220a of the first conductive material and an upper layer 220b of the second conductive material. Next, a first photosensitive pattern 292 is formed on the second metal layer 240 by forming a photosensitive layer by coating a photosensitive material on the second metal layer 240, and then exposing and developing the exposed photosensitive layer using a mask. The first photosensitive pattern 292 includes a first pattern 292a and a second pattern 292b and a thickness of the second pattern 292b is smaller than that of the first pattern 292a.

At this time, the mask used includes a blocking portion for blocking light, a transmitting portion for transmitting light, and a semi-transmitting portion for transmitting only a part of light. The blocking portion corresponds to the first pattern 292a, and the transflective portion corresponds to the second pattern 292b. The semi-transmissive portion may include a plurality of slits or semi-transmissive films.

On the other hand, an insulating substrate such as a glass substrate or a plastic substrate can be used as the substrate 210. The first conductive material and the second conductive material of the first metal layer 220 may be aluminum alloy such as aluminum (Al) or aluminum-neodymium (AlNd), molybdenum such as molybdenum (Mo) or molybdenum- Alloy, copper (Cu), or chromium (Cr). Although not shown, the silicon layer 230 includes a sequentially stacked impurity amorphous silicon layer, a pure amorphous silicon layer, and an impurity amorphous silicon layer. The second metal layer 240 is formed of a conductive material such as aluminum (Al), an aluminum alloy such as aluminum-neodymium (AlNd), a molybdenum alloy such as molybdenum (Mo), molybdenum-titanium (MoTi), or chrome . In this case, the second metal layer 240 may be formed of a material different from the second conductive material.

The first and second metal layers 220 and 240 may be formed by a method such as sputtering and the silicon layer 230 may be formed by a method such as chemical vapor deposition.

As shown in FIG. 8B, the second metal layer (240 in FIG. 8A), the silicon layer (230 in FIG. 8A), and the first metal layer (FIG. 8A) are formed by using the first photosensitive pattern 220 of FIG. Thus, a double-layered gate wiring 222, a data wiring 232, a source electrode 236, a gate pad 224, a data pad 234, a first capacitor electrode 246, 1, the second pixel electrode patterns 266a and 266b, and the second common electrode pattern 268b. At this time, the gate wiring 222, the data wiring 232, the source electrode 236, the gate pad 224, the data pad 234, the first capacitor electrode 246, the first and second pixel electrode patterns 266a A silicon pattern 230a and a metal pattern 240a are sequentially formed on the first and second common electrode patterns 266a and 266b and the second common electrode pattern 268b, respectively. Although not shown, a third pixel electrode pattern 266c connected to the first and second pixel electrode patterns 266a and 266b and a first and a third common electrode pattern 266c connected to the first capacitor electrode 246, (268a, 268c in Fig. 6) are also formed. Here, the first metal layer (220 in FIG. 8A) may be removed by wet etching, and the second metal layer (240 in FIG. 8A) and the silicon layer (230 in FIG. 8A) may be removed by dry etching.

Then, the second pattern (292b in FIG. 8A) is removed by a method such as ashing to form the data line 232 and the gate line 222, the gate pad 224, the data pad 234, Exposes the metal pattern 240a on the electrode 246, the first and second pixel electrode patterns 266a and 266b, and the second common electrode pattern 268b. At this time, the first pattern 292a is partially removed, and its thickness is thinned.

Next, the metal pattern 240a and the silicon pattern 230a are removed using the first pattern 292a as an etching mask, and the remaining first pattern 292a is removed.

8C, a semiconductor layer 242 and a drain electrode 244 are formed on the source electrode 236. In this case, Although not shown, the semiconductor layer 242 includes a first ohmic contact layer of impurity amorphous silicon, an active layer of pure amorphous silicon, and a second ohmic contact layer of impurity amorphous silicon. As described above, the gate wiring 222, the data wiring 232, the source electrode 236, the gate pad 224, the data pad 234, the first capacitor electrode 246, the first The second pixel electrode patterns 266a and 266b, the second common electrode pattern 268b, the semiconductor layer 236, and the drain electrode 244 can be formed.

Next, a gate insulating layer 250 is formed on the substrate 210 including the drain electrode 244. The gate insulating layer 250 may be formed by a chemical vapor deposition method or may be an inorganic insulating layer such as a silicon nitride layer (SiNx) or a silicon oxide layer (SiO ₂ ).

As shown in FIG. 8D, a photosensitive layer is formed on the gate insulating layer 250 to form a photosensitive layer, followed by exposure and development to form a second photosensitive pattern 294 on the gate insulating layer 250. Next, the gate insulating layer 250 is selectively removed using the second photoresist pattern 294 as an etching mask to form the opening 252 of the pixel region and the first to fourth contact holes 250a to 250d. The opening 252 exposes the first and second pixel electrode patterns 266a and 266b and the second common electrode pattern 268b located in the pixel region. The first contact hole 250a exposes the gate wiring 222 and the second contact hole 250b exposes the drain electrode 244. The third contact hole 250c exposes the gate pad 224 And the fourth contact hole 250d exposes the data pad 234. As shown in FIG. At this time, the fifth to tenth contact holes 250e to 250j of FIG. 6 are also formed. The gate insulating layer 250 may be removed by dry etching. The gate insulating layer 250 may be removed through the first, third and fourth contact holes 250a, 250c and 250d, And the upper layer of the data pad 234 and the upper layer of the first and second pixel electrode patterns 266a and 266b and the second common electrode pattern 268b exposed through the opening 252 may be removed together. Accordingly, the first and second pixel electrode patterns 266a and 266b and the second common electrode pattern 268b may have a single layer structure of the first conductive material.

However, the first and second pixel electrode patterns 266a and 266b and the second common electrode pattern 268b may be formed to have a bilayer structure.

Next, the second photosensitive pattern 294 is removed.

Thus, a gate insulating film 250 having the first to tenth contact holes 250a to 250j and the opening 252 is formed through the second mask process.

8E, a third metal layer 260 is formed on the gate insulating layer 250, a photosensitive material is coated on the third metal layer 260, a photosensitive layer is formed on the third metal layer 260, The third photosensitive pattern 296 is formed. The third metal layer 260 may be formed of an aluminum alloy such as aluminum or aluminum-neodymium (AlNd), a molybdenum alloy such as molybdenum (Mo), molybdenum-titanium (MoTi), copper (Cu) May be formed of the same conductive material. The third metal layer 260 may be formed through a sputtering method.

As shown in FIG. 8F, the third metal layer (260 in FIG. 8E) is selectively removed using the third photosensitive pattern (296 in FIG. 8E) as an etching mask, and the third photosensitive pattern (296 in FIG. Remove. At this time, the third metal layer (260 in FIG. 8E) may be removed by wet etching. Thus, a gate electrode 262, a second capacitor electrode 264, a gate pad terminal 272, and a data pad terminal 274 are formed on the gate insulating film 250. At this time, although not shown, a data connection pattern (238 in FIG. 6) and a common electrode connection pattern (267 in FIG. 6) are also formed. The gate electrode 262 contacts the gate wiring 222 through the first contact hole 250a and overlaps the side surface of the semiconductor layer 242. [ The gate electrode 262 and the source electrode 236, the semiconductor layer 242 and the drain electrode 244 constitute a thin film transistor T. [ The second capacitor electrode 264 contacts the drain electrode 244 through the second contact hole 250b and overlaps the first capacitor electrode 246 to form a storage capacitor Cst. The gate pad terminal 272 contacts the gate pad 224 through the third contact hole 250c and the data pad terminal 274 contacts the data pad 234 through the fourth contact hole 250d. The gate electrode 262 and the gate pad terminal 272 and the data pad terminal 274 are in contact with the lower layer of the gate wiring 222 and the gate pad 224 and the data pad 234.

Thus, the gate electrode 262, the second capacitor electrode 264, the gate pad terminal 272, and the data pad terminal 274 can be formed through the third mask process.

As described above, the array substrate for a liquid crystal display according to the second embodiment of the present invention can be manufactured by a three-mask process. Therefore, compared with the conventional method of manufacturing an array substrate by the 4-mask process, the mask process is reduced once, the deposition and etching processes are reduced, and the productivity is improved. For example, the manufacturing method of the array substrate for a liquid crystal display according to the second embodiment of the present invention is reduced by about 20% compared with the conventional manufacturing method using the 4-mask process. Therefore, the defective occurrence rate is lowered and the productivity can be improved.

In addition, since the liftoff method is not used, the process yield can be improved as compared with the conventional method of manufacturing the array substrate by the 3-mask process.

On the other hand, a modification of the second embodiment of the present invention will be described with reference to Fig. 9 is a plan view of an array substrate for a liquid crystal display according to a modification of the second embodiment of the present invention. The modification has a difference in the structure of FIG. 6 and the common wiring and the common electrode connection pattern. The same reference numerals are given to the same parts as those in FIG. 6, and a description thereof will be omitted.

9, a common wiring 269 extends along the first direction and is formed in parallel with the gate wiring 222, and is connected to the first and third common electrode patterns 268a and 268c. The common electrode connection pattern 267a has an I-shape and contacts the common wiring 269 through the eighth contact hole 250h. The common electrode connection pattern 267a contacts the common wiring 269 through the ninth contact hole 250i, And contacts the first capacitor electrode 246 or the third common electrode pattern 268c.

The present invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit of the present invention.

1A to 1F are views for explaining a method of manufacturing an array substrate by a conventional four mask process.

2A to 2E are views for explaining an array substrate manufacturing method by a conventional three-mask process.

3 is a plan view showing an array substrate for a liquid crystal display according to a first embodiment of the present invention.

4 is a cross-sectional view corresponding to an IVA-IVA line, a line IVB-IVB and a line IVC-IVC in FIG.

5A to 5F are views for explaining a method of manufacturing an array substrate for a liquid crystal display according to the first embodiment of the present invention.

6 is a plan view showing an array substrate for a liquid crystal display according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view corresponding to a section cut along VIIA-VIIA line, VIIB-VIIB line and VIIC-VIIC line in FIG.

8A to 8F are views for explaining a method of manufacturing an array substrate for a liquid crystal display according to a second embodiment of the present invention.

9 is a plan view of an array substrate for a liquid crystal display according to a modification of the second embodiment of the present invention.

Claims (17)

A gate wiring extending in a first direction on the substrate; A data line extending in a second direction on the substrate to define a pixel region together with the gate line and located between adjacent gate lines; A source electrode extending in the data line; A first ohmic contact layer disposed on the source electrode and sequentially stacked, a semiconductor layer including an active layer and a second ohmic contact layer; A drain electrode on the semiconductor layer; A gate insulating film over the drain electrode and the gate wiring; A gate electrode located above the gate insulating layer and connected to the gate wiring, the gate electrode overlapping a side surface of the semiconductor layer; A data connection pattern located above the gate insulating film and crossing the gate wiring and connected to adjacent data lines along the second direction; A pixel electrode located in the pixel region and electrically connected to the drain electrode; And A common electrode disposed in the pixel region and staggered with the pixel electrode, And a plurality of pixel electrodes formed on the substrate. The method according to claim 1, A first capacitor electrode formed on the substrate and connected to the common electrode, and a second capacitor electrode formed on the gate insulating film and connected to the drain electrode, the second capacitor electrode overlapping the first capacitor electrode And a plurality of pixel electrodes formed on the substrate. The method of claim 2, Wherein the pixel electrode and the common electrode are formed of the same material as the gate electrode above the gate insulating film. The method of claim 3, Wherein the pixel electrode includes first and second pixel electrode patterns extending in parallel with the data line and extending from the second capacitor electrode, the common electrode includes first to third common electrode patterns parallel to the data line, And a fourth common electrode pattern which is parallel to the gate wiring and connects the first to third common electrode patterns. The method of claim 4, Wherein the auxiliary common electrode is formed on the same layer as the gate wiring and extends from the first capacitor electrode, the auxiliary common electrode includes a first auxiliary common electrode pattern overlapping the first common electrode pattern, A second auxiliary common electrode pattern overlapping the third common electrode pattern, and a third auxiliary common electrode pattern overlapping and connecting with the fourth common electrode pattern. The method of claim 2, Wherein the pixel electrode and the common electrode are formed on the same layer with the same material as the gate wiring and the data wiring. The method of claim 6, Wherein the gate line and the data line have a double layer structure of a first conductive material and a second conductive material, and the pixel electrode and the common electrode have a single layer structure of the first conductive material. Array substrate. The method of claim 6, Wherein the gate insulating film has an opening for exposing the pixel electrode and the common electrode. The method of claim 6, Wherein the pixel electrode includes first and second pixel electrode patterns parallel to the data line and a third pixel electrode pattern connecting the first and second pixel electrode patterns, And first to third common electrode patterns extending from the first capacitor electrode. The method of claim 6, And a common electrode connection pattern located above the gate insulating film and in contact with the common electrodes of neighboring pixel regions. The method of claim 6, And a common wiring which is parallel to the gate wiring and is connected to the common electrode. Forming a gate wiring extending in a first direction on the substrate; Forming a data line extending in a second direction on the substrate to define a pixel region together with the gate line and located between adjacent gate lines; Forming a source electrode extending in the data line; Forming a semiconductor layer including a first ohmic contact layer sequentially stacked on the source electrode and an active layer and a second ohmic contact layer; Forming a drain electrode on the semiconductor layer; Forming a gate insulating film on the drain electrode and the gate wiring; Forming a gate electrode over the gate insulating film, the gate electrode being connected to the gate wiring and overlapping a side surface of the semiconductor layer; Forming a data connection pattern on the gate insulating film, the data connection pattern being crossed with the gate wiring and connected to adjacent data wirings along the second direction; Forming a pixel electrode electrically connected to the drain electrode in the pixel region; Forming a common electrode in the pixel region so as to be shifted from the pixel electrode; And forming a plurality of pixel electrodes on the array substrate. The method of claim 12, Wherein the step of forming the drain electrode, the step of forming the semiconductor layer, the step of forming the source electrode, and the step of forming the data line are performed in the same photolithography process. ≪ / RTI > 14. The method of claim 13, Wherein the photolithography process uses a mask including a transmissive portion, a transflective portion, and a blocking portion, and the transflective portion corresponds to the data line. 14. The method of claim 13, Forming a first capacitor electrode connected to the common electrode on the substrate and forming a second capacitor electrode connected to the drain electrode and overlying the first capacitor electrode over the gate insulating film, And forming a second insulating film on the substrate. 14. The method of claim 13, Wherein the step of forming the pixel electrode, the step of forming the common electrode, and the step of forming the gate electrode are performed in the same step. Forming a gate wiring extending in a first direction on the substrate; Forming a data line extending in a second direction on the substrate to define a pixel region together with the gate line and located between adjacent gate lines; Forming a source electrode extending in the data line; Forming a semiconductor layer including a first ohmic contact layer sequentially stacked on the source electrode and an active layer and a second ohmic contact layer; Forming a drain electrode on the semiconductor layer; Forming a pixel electrode electrically connected to the drain electrode in the pixel region; Forming a common electrode in the pixel region so as to be shifted from the pixel electrode; Forming a gate insulating film on the drain electrode and the gate wiring; Forming a gate electrode over the gate insulating film, the gate electrode being connected to the gate wiring and overlapping a side surface of the semiconductor layer; Forming a data connection pattern on the gate insulating film, the data connection pattern being crossed with the gate line and connected to adjacent data lines along the second direction; Lt; / RTI > Wherein the step of forming the pixel electrode, the step of forming the common electrode, the step of forming the gate wiring, and the step of forming the data wiring are performed in the same step. Way.

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