KR101613115B1 - manufacturing method of stacked semiconductor package - Google Patents

manufacturing method of stacked semiconductor package Download PDF

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Publication number
KR101613115B1
KR101613115B1 KR1020140116676A KR20140116676A KR101613115B1 KR 101613115 B1 KR101613115 B1 KR 101613115B1 KR 1020140116676 A KR1020140116676 A KR 1020140116676A KR 20140116676 A KR20140116676 A KR 20140116676A KR 101613115 B1 KR101613115 B1 KR 101613115B1
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KR
South Korea
Prior art keywords
solder ball
photosensitive film
substrate
mask
mold
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KR1020140116676A
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Korean (ko)
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KR20160028116A (en
Inventor
유봉석
김은동
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주식회사 에스에프에이반도체
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Priority to KR1020140116676A priority Critical patent/KR101613115B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

More particularly, the present invention relates to a method of fabricating a multilayer semiconductor package, and more particularly, to a method of manufacturing a multilayer semiconductor package, which comprises forming an etching hole using a photosensitive film and forming a via hole by a dry or wet etching method, And a method of fabricating a stacked semiconductor package that can reduce cost and time required for forming via holes (TMV) through laser processing.

Description

[0001] The present invention relates to a method of manufacturing a stacked semiconductor package,

More particularly, the present invention relates to a method of fabricating a multilayer semiconductor package, and more particularly, to a method of manufacturing a multilayer semiconductor package, which comprises forming an etching hole using a photosensitive film and forming a via hole by a dry or wet etching method, And a method of fabricating a stacked semiconductor package that can reduce cost and time required for forming via holes (TMV) through laser processing.

Packaging technology for semiconductor integrated circuits has been continuously developed to meet the demands for miniaturization and mounting efficiency. Recently, various technologies for a "stack" have been developed due to the demand for miniaturization and high performance of electric / electronic products.

The term " stack " in the semiconductor industry refers to a technique of vertically stacking at least two chips or packages. According to this stacking technique, in the case of a memory device, a memory capacity two times or more And the efficiency of use of the mounting area can be increased.

5 is a view showing a state in which a conventional stacked semiconductor package is stacked.

Referring to FIG. 5, since a conventional TMV (Through-via Vias) formed in a lower package is formed by laser machining, the cost increases and the process becomes complicated. Further, there is a problem that an additional surface modification process is added to remove foreign substances after laser processing.

Korean Patent Laid-Open No. 10-2011-0032522 Package-on-package type semiconductor package and manufacturing method thereof (Published date: December 18, 2007)

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide an etching method and a manufacturing method thereof, which can reduce cost and time required for forming a via via (TMV) And a method of manufacturing a stacked semiconductor package.

It is another object of the present invention to provide an etching hole processing method and a multilayer semiconductor package manufacturing method capable of continuously performing a via hole and a surface modification process by forming an etching hole using a photosensitive film and forming a via hole by a dry or wet etching method Method.

To this end, a method for etching an etching hole according to the present invention includes: providing a substrate including a substrate, a semiconductor chip formed on the substrate, an upper terminal formed on an upper surface of the substrate, and a mold sealing the semiconductor chip and the upper terminal ; Depositing a photosensitive film made of a negative photosensitizer and a mask on the mold in sequence, the mask being stacked on a region directly above the upper terminal; Exposing the photosensitive film to ultraviolet light; And forming the etching hole by developing the photosensitive film with a developer in a state in which the mask is removed, wherein the etching hole is formed by selectively removing only the photosensitive film in the region directly above the upper terminal .

According to another aspect of the present invention, there is provided a method of processing an etching hole, the method including: providing a package including a substrate, a semiconductor chip formed on the substrate, an upper terminal formed on the upper surface of the substrate, and a mold sealing the semiconductor chip and the upper terminal ; Depositing a photosensitive film comprising a negative photosensitizer and a mask sequentially on the mold, wherein the mask is stacked on the remaining region except the region directly above the upper terminal; Exposing the photosensitive film to ultraviolet light; And forming the etching hole by developing the photosensitive film with a developer in a state in which the mask is removed, wherein the etching hole is formed by selectively removing only the photosensitive film in the region directly above the upper terminal .

According to another aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor package including a first substrate, a first semiconductor chip formed on the first substrate, a first lower terminal and a first upper terminal respectively formed on upper and lower surfaces of the first substrate, Providing a package including a first solder ball formed on the first upper terminal and a first mold sealing the first semiconductor chip and the first solder ball; Depositing a photosensitive film comprising a negative photoresist and a mask on the first mold in sequence, the mask being stacked on a region directly above the first solder ball; Exposing the photosensitive film to ultraviolet light; Forming an etching hole by selectively removing only a photosensitive film in a region directly above the first solder ball; developing the photosensitive film with a developer in a state where the mask is removed to form an etching hole; Forming a via hole by selectively etching only the first mold in the region directly above the first solder ball by dry or wet etching through the photosensitive film on which the etching hole is formed; A second semiconductor chip formed on the second substrate, a second lower terminal and a second upper terminal formed on the lower surface of the second substrate, and a second solder ball formed on the second lower terminal, And bonding the second solder ball to the first solder ball by inserting the second solder ball into the via hole.

The etching hole machining method and the method of fabricating a stacked semiconductor package according to the present invention having the above-described structure have the effect of reducing the cost and time required for forming a through mold via (TMV) through laser processing .

In the etching hole processing method and the laminate type semiconductor package manufacturing method according to the present invention, the etching hole is formed using the photosensitive film and the via hole is formed by a dry or wet etching method. Therefore, the via hole processing and the surface modification process can be continuously performed There is an effect.

1 is a cross-sectional view showing an embodiment of a stacked semiconductor package according to the present invention.
2A to 2D are sectional views showing respective steps of an etching hole machining method according to the present invention.
3A to 3D are cross-sectional views showing respective steps of another embodiment of the etching hole machining method according to the present invention.
4A to 4B are cross-sectional views showing respective steps of the method for manufacturing a stacked semiconductor package according to the present invention.
5 is a view showing a state in which a conventional stacked semiconductor package is stacked.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention of the user, the operator, or the precedent. Therefore, the definition should be based on the contents throughout this specification.

1 is a cross-sectional view showing an embodiment of a stacked semiconductor package according to the present invention.

Referring to FIG. 1, a stacked semiconductor package according to the present invention includes a lower package 100 and an upper package 200 stacked on the lower package 100.

First, the lower package 100 includes a first substrate 110, a first semiconductor chip 130 formed on the first substrate 110, a first semiconductor chip 130 formed on the first substrate 110, A first solder ball 115 formed on the first upper terminal 113 and a second solder ball 115 formed on the first upper terminal 113 to seal the first semiconductor chip 130 and the first solder ball 115 And a via hole 151 formed in the first mold 150 so as to pass through the first solder ball 115 in a region directly above the first solder ball 115. The first mold may be made of an insulating material, for example, an epoxy mold compound material.

Next, the upper package 200 includes a second substrate 210, a second semiconductor chip 230 formed on the second substrate 210, a second semiconductor chip 230 formed on the lower surface of the second substrate 210, A second solder ball 215 formed on the second lower terminal 211 and inserted in the via hole 151 to be coupled to the first solder ball 115, And a second mold 250 made of an EMC (epowy mold compound) for sealing the second semiconductor chip 230 and the second solder ball 215. [

That is, the first solder ball is exposed to the outside through the via hole to be electrically connected to the second solder ball and physically coupled.

In another embodiment, the first solder ball may be omitted on the first upper terminal. In this case, the via hole may be filled with a conductive material and the second solder ball may be configured to be coupled to the conductive material, And may be directly coupled to the first upper terminal.

FIGS. 2A to 2D are cross-sectional views showing respective steps of the etching hole machining method according to the present invention, and can largely be performed in steps S1 to S4.

Referring to FIG. 2A, the step S1 includes a first substrate 110, a first semiconductor chip 130 formed on the first substrate 110, a first semiconductor chip 130 formed on a top surface of the first substrate 110, A lower package 100 including a terminal 113 and a first mold 150 for sealing the first semiconductor chip 130 and the first upper terminal 113 are provided.

Referring to FIG. 2B, in step S2, a photosensitive film 160 and a mask 170 are sequentially stacked on the first mold 150 and the mask 170 is electrically connected to the first upper terminal 113). ≪ / RTI >

Here, the negative photosensitizer has a property of being changed into a material that is insoluble in a developer upon absorption of light (UV).

Referring to FIG. 2C, in step S3, the photosensitive film 160 is exposed in ultraviolet (UV) state in a state where a mask is formed in a region directly above the first upper terminal 113 of the photosensitive film 160 to be. When the photosensitive film is exposed with ultraviolet rays, exposure is not performed on the photosensitive film in the region directly below the mask 170, and exposure is performed only on the photosensitive film in the region where the mask 170 is not present.

Referring to FIG. 2D, in step S4, the photosensitive film 160 is developed with a developer in the state where the mask 170 is removed, thereby forming an etching hole 161. Referring to FIG.

At this time, only a region which is not exposed by the mask is melted in the photosensitive film made of the negative photosensitive agent, and the photosensitive mold is removed through the cleaning process.

Hereinafter, another embodiment of the method for machining a via hole according to the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 3A to 3D are cross-sectional views showing respective steps of another embodiment of the etching hole machining method according to the present invention, and may largely consist of steps S1 to S4.

Referring to FIG. 3A, step S1 includes a first substrate 110, a first semiconductor chip 130 formed on the first substrate 110, a first semiconductor chip 130 formed on a top surface of the first substrate 110, A lower package 100 including a terminal 113 and a first mold 150 for sealing the first semiconductor chip 130 and the first upper terminal 113 are provided.

Referring to FIG. 3B, in step S2, a photosensitive film 160 and a mask 170 are sequentially stacked on the first mold 150 and the mask 170 is electrically connected to the first upper terminal 113). ≪ / RTI >

Herein, the positive photoresist has a property of being changed into a material soluble in a developer upon absorption of light (UV).

Referring to FIG. 3C, in step S3, the photosensitive film 160 is exposed in ultraviolet (UV) state in a state where a mask is formed in a region directly above the first upper terminal 113 of the photosensitive film 160 to be. When the photosensitive film is exposed with ultraviolet rays, exposure is not performed on the photosensitive film in the region directly below the mask 170, and exposure is performed only on the photosensitive film in the region where the mask 170 is not present.

Referring to FIG. 3D, in step S4, the photosensitive film 160 is developed with a developer in the state where the mask 170 is removed, thereby forming an etching hole 161. FIG.

At this time, only the area exposed to the mask among the photosensitive mold made of the positive photosensitive agent is melted, and the photosensitive mold is removed through the cleaning process.

Hereinafter, a method for fabricating a stacked semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings. However, the same or similar components as those described above will not be described in detail.

FIGS. 4A and 4B are cross-sectional views showing respective steps of the method for fabricating a stacked semiconductor package according to the present invention. Referring to FIGS. 2A to 2D and FIGS. 4A and 4B, To S6.

A method of manufacturing a stacked semiconductor package according to the present invention includes a first substrate 110, a first semiconductor chip 130 formed on the first substrate 110, A first solder ball 115 formed on the first upper terminal 113 and a second solder ball 115 formed on the first semiconductor chip 130 and the first solder ball 115, A step of providing a lower package 100 including a first mold 150 to be sealed and a photosensitive film 160 and a mask 170 made of a negative photosensitizer sequentially on the first mold 150 , The mask 170 is stacked on a region directly above the first upper terminal 113, and a state in which a mask is formed in a region directly above the first upper terminal 113 of the photosensitive film 160 Exposing the photosensitive film 160 to ultraviolet light in a state where the mask 170 is removed, Forming an etching hole (161) to develop a name 160,

The first mold 150 is selectively removed by dry or wet etching through the photosensitive film 160 on which the etching hole 161 is formed to selectively form the via hole 151 A second semiconductor chip 230 formed on the second substrate 210 and a second lower terminal 211 formed on a lower surface of the second substrate 210; The upper package 200 includes the second upper terminal 213 and the second solder ball 215 formed on the second lower terminal 211. The second solder ball 215 is electrically connected to the via hole 151, And coupling the first solder ball 115 with the first solder ball 115.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100, 200: package
110, 210: substrate
111, 211: Lower terminal
113, 213: upper terminal
115, 215: Solder ball
130 and 230: semiconductor chips
150, 250: Mold
151: Via hole
160: Photosensitive film
161: Etching hole
170: Mask

Claims (3)

A semiconductor device comprising: a first substrate; a first semiconductor chip formed on the first substrate; a first lower terminal and a first upper terminal respectively formed on upper and lower surfaces of the first substrate; a first solder ball formed on the first upper terminal; Providing a lower package including a first mold sealing the first semiconductor chip and a first solder ball;
Depositing a photosensitive film comprising a negative photoresist and a mask on the first mold in sequence, the mask being stacked on a region directly above the first solder ball;
Exposing the photosensitive film to ultraviolet light;
Forming an etching hole by selectively removing only a photosensitive film in a region directly above the first solder ball; developing the photosensitive film with a developer in a state where the mask is removed to form an etching hole;
Forming a via hole by selectively etching only the first mold in the region directly above the first solder ball by dry or wet etching through the photosensitive film on which the etching hole is formed;
A second semiconductor chip formed on the second substrate, a second lower terminal and a second upper terminal formed on the lower surface of the second substrate, and a second solder ball formed on the second lower terminal, And inserting the second solder ball into the via hole to couple the first solder ball with the first solder ball;
Wherein the semiconductor package is a semiconductor package. delete delete
KR1020140116676A 2014-09-03 2014-09-03 manufacturing method of stacked semiconductor package KR101613115B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129262A (en) 2010-12-13 2012-07-05 Sumitomo Bakelite Co Ltd Manufacturing method of semiconductor element sealing body and manufacturing method of semiconductor package

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KR101624973B1 (en) 2009-09-23 2016-05-30 삼성전자주식회사 Package on package type semiconductor package and method for fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012129262A (en) 2010-12-13 2012-07-05 Sumitomo Bakelite Co Ltd Manufacturing method of semiconductor element sealing body and manufacturing method of semiconductor package

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