KR101607259B1 - Passive device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a passive device and a method for manufacturing the same. A metal insulator metal (MIM) capacitor of the present invention includes: a capacitor thin film pattern which is formed on one plane of a substrate; a trench which is formed by etching the substrate where the capacitor thin film pattern is formed; an insulation layer which is formed on the substrate while filling the trench, and has wire grooves for a capacitor which expose metal layers constituting the capacitor; and a capacitor electrode wire which is formed by filling a conductive material into the wire grooves for an IM capacitor. The other plane of the substrate is polished so that the insulation layer formed on the trench can be exposed. According to the present invention, since the insulation layer formed in the trench as the other plane of the substrate, which is an opposite plane to one plane of the substrate where the passive device is formed, has a structure where the insulation layer is exposed, the apparatus can block electrical loss by fundamentally blocking a passage of electrical leakage to an adjacent unit device, and therefore, can improve electrical characteristics in a high frequency region of the passive device which is a final product.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a passive device,

The present invention relates to a passive element and a manufacturing method thereof. More particularly, the present invention relates to a passive element including a capacitor, a capacitor, and an inductor, which shields electrical loss by originally blocking a path of electrical leakage to adjacent unit elements and greatly improves electrical characteristics in a high frequency region, and a manufacturing method thereof .

In the case of highly integrated IC technology using a conventional silicon substrate, a metal insulator metal (MIM) capacitor structure is commonly used for RFIC design and fabrication.

1 shows a conventional MIM capacitor.

Referring to FIG. 1, a MIM capacitor has a structure in which a substrate insulating layer such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ) is formed on the surface of a substrate, that is, a passive element In a state in which it is formed in a lower portion of a position where the electrode is to be formed.

The substrate insulating layer must be formed to a thickness of several micrometers or less in consideration of the process cost and the wafer warpage. Such thickness is insufficient to electrically insulate the passive element from the substrate having the lower lossy characteristic.

Therefore, when a MIM capacitor having a relatively large capacitance is integrated in a high-frequency circuit, a large area of the lower electrode (the first metal layer in FIG. 1) constituting the MIM capacitor is adhered to the silicon substrate having the oil- There is a problem that electric loss occurs.

Korean Unexamined Patent Publication No. 1999-0016810 (Published Date: March 15, 1999, titled: Method of Manufacturing Capacitor of Semiconductor Device) Korean Patent Laid-Open Publication No. 10-2004-0086705 (Published Date: October 12, 2004, name: Method of manufacturing capacitor of semiconductor device)

The present invention polishes the other surface of the substrate, that is, the opposite surface opposite to the one surface of the substrate on which the passive element is formed, so that the insulating layer formed on the trench is exposed, thereby shielding the path of electrical leakage to the adjacent unit element And to provide a passive element which cuts off an electrical loss and greatly improves electrical characteristics in a high frequency region, and a manufacturing method thereof.

It is another object of the present invention to provide a passive element and a method of manufacturing the passive element which can greatly improve the electrical loss characteristics of the passive element in a silicon-based high-frequency circuit, thereby improving the performance of the entire system IC.

It is another object of the present invention to provide a passive element and a method of manufacturing the same that enable a SoC (System on a Chip) implementation that integrates all RF circuits.

It is another object of the present invention to provide a passive device capable of mass production of a large diameter IPD (Integrated Passive Device) and an interposer based on lossy silicon for high frequency package applications and a method for manufacturing the same. .

According to an aspect of the present invention, there is provided a capacitor including: a capacitor thin film pattern formed on one surface of a substrate; a trench formed by etching a substrate on which the capacitor thin film pattern is formed to define a unit area of the capacitor; An insulating layer formed on the substrate and having capacitor wiring holes exposing the metal layers constituting the capacitor, and a capacitor electrode wiring formed by filling a conductive material in the capacitor wiring holes, And the other surface of the trench is polished to expose the insulating layer formed on the trench.

In the capacitor according to the present invention, the substrate is made of silicon, and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern.

A method of manufacturing a capacitor according to the present invention includes forming a thin film pattern on a surface of a substrate, forming a trench defining a unit area of the capacitor by etching the substrate having the capacitor thin film pattern formed thereon, Forming an insulating layer on the trench and the substrate; forming a wiring hole for the capacitor to expose the metal layers constituting the capacitor to the insulating layer; forming a wiring hole in the capacitor wiring hole, And a substrate polishing step of polishing the other surface of the substrate to expose the insulating layer formed on the trench.

In the method of manufacturing a capacitor according to the present invention, the substrate is made of silicon, and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern.

In the method of manufacturing a capacitor according to the present invention, the insulating layer may be formed on the trench and the substrate using organic lamination, spin coating, or chemical vapor deposition And the insulating layer is formed.

A passive element including a capacitor and an inductor according to the present invention includes a capacitor thin film pattern formed on one surface of a substrate, a thin metal pattern for wiring the inductor, a capacitor thin film pattern and a thin metal pattern for wiring the inductor, Capacitor interconnecting holes formed on the substrate while filling the trench and exposing the metal layers constituting the capacitor, and inductor wiring holes for exposing the inductor wiring thin metal pattern are formed An inductor thin film made of a conductive material formed on the surface of the insulating layer and in the wiring holes for inductors formed in the insulating layer, a capacitor electrode wiring formed by filling a conductive material into the wiring holes for capacitor formed in the insulating layer, Pattern, And the other surface of the substrate is polished to expose the insulating layer formed on the trench.

In the passive element including the capacitor and the inductor according to the present invention, the substrate is made of silicon, and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern and the inductor wiring thin film metal pattern. do.

In the passive element including the capacitor and the inductor according to the present invention, the inductor thin film pattern formed on the surface of the insulating layer has a spiral shape.

A passive device manufacturing method including a capacitor and an inductor according to the present invention includes a thin film pattern forming step of forming a capacitor thin film pattern and an inductor wiring thin film metal pattern on one surface of a substrate, a step of forming the capacitor thin film pattern and the thin film metal pattern for inductor wiring A trench forming step of forming a trench defining a unit area of a capacitor and an inductor by etching the substrate, an insulating layer forming step of forming an insulating layer on the trench and the substrate, the metal layers constituting the capacitor being exposed A wiring hole forming step of forming inductor wiring holes so as to expose the capacitor wiring wirings and the inductor wiring thin film metal layer so as to expose the capacitor wiring wirings and the capacitor wiring wirings to form the capacitor electrode wirings by filling the capacitor wiring wirings with a conductive material , An inductor-forming vessel Filling the conductive material in the holes, and comprises a substrate polishing step of polishing the other surface of the substrate such that the surface of the exposed insulating layer formed on the thin film inductor pattern forming step and the trench forming a pattern on the thin film inductor of the insulating layer.

In the passive element manufacturing method according to the present invention, the substrate is made of silicon, and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern and the inductor wiring thin film metal pattern .

In the passive element manufacturing method including the capacitor and the inductor according to the present invention, the insulating layer forming step may be performed by using organic lamination, spin coating, or chemical vapor deposition And the insulating layer is formed on the trench and the substrate.

In the passive device manufacturing method including the capacitor and the inductor according to the present invention, the step of forming the capacitor electrode wiring and the step of forming the inductor thin film pattern are performed in the same process.

The inductor thin film pattern formed on the surface of the insulating layer in the step of forming the inductor thin film pattern has a spiral shape in the passive element manufacturing method including the capacitor and the inductor according to the present invention.

According to the present invention, since the other surface of the substrate, that is, the surface opposite to the one surface of the substrate on which the passive element is formed is polished and the insulating layer formed on the trench is exposed, the path of electrical leakage to the adjacent unit So that the electrical loss in the high-frequency region of the passive device, which is a final product, can be greatly improved.

In addition, there is an effect that a passive element and a manufacturing method thereof capable of greatly improving the electrical loss characteristic of a passive element in a silicon-based high-frequency circuit and improving the performance of the entire system IC are provided.

Further, there is an effect that a passive element and a manufacturing method thereof capable of implementing an SoC (System on a Chip) that integrates all RF circuits are provided.

Also, there is an effect that a passive device capable of mass production of a large-diameter IPD (Integrated Passive Device) and an interposer based on a lossy silicon for high frequency package application and a manufacturing method thereof are provided.

1 is a view showing a conventional MIM (Metal Insulator Metal) capacitor.
2 is a cross-sectional view of a capacitor according to an embodiment of the present invention.
3 is a plan view of a capacitor according to an embodiment of the present invention.
4 is a process flow diagram of a method of manufacturing a capacitor according to an embodiment of the present invention.
5 to 10 are process sectional views of a method of manufacturing a capacitor according to an embodiment of the present invention.
11 is a cross-sectional view of a passive device including a capacitor and an inductor in accordance with an embodiment of the present invention.
12 is a top view of a passive device including a capacitor and an inductor in accordance with an embodiment of the present invention.
13 is a process flow diagram of a passive device manufacturing method including a capacitor and an inductor according to an embodiment of the present invention.
FIGS. 14 to 19 are process sectional views of a passive device manufacturing method including a capacitor and an inductor according to an embodiment of the present invention.
FIGS. 20 and 21 are graphs comparing experimental values of S (Scattering) parameters when a conventional capacitor and a capacitor according to an embodiment of the present invention have a cross sectional area of 150 × 150 μm ² .
FIGS. 22 and 23 are graphs comparing experimental values of the S parameter for a conventional capacitor and a capacitor according to an embodiment of the present invention when the cross-sectional area of the capacitor is 300 × 300 μm ² .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, preferred embodiments of the present invention will be described by exemplifying the case where the capacitor is a metal insulator metal (MIM) capacitor. However, the capacitor may be an interdigital capacitor, an SIS (Silicon Insulator Silicon) Metal Insulator Semiconductor) capacitors.

FIG. 2 is a cross-sectional view of a capacitor according to an embodiment of the present invention, and FIG. 3 is a plan view of a capacitor according to an embodiment of the present invention.

2 and 3, a capacitor according to an embodiment of the present invention includes a substrate 10, a lower insulating layer 20, a capacitor thin film pattern 30, trenches 402 and 404, an insulating layer 50, And capacitor electrode wirings 602 and 604.

The substrate 10 may be a silicon substrate having lossy characteristics. One surface of the substrate 10 is a surface on which a capacitor thin film pattern 30 to be described later is formed, and the other surface of the substrate 10 is a surface opposite thereto.

The lower insulating layer 20 is formed on one surface of the substrate 10 and functions to reduce the electrical loss of the silicon having the oil loss characteristic. For example, the lower insulating layer 20 may be a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ), and may be formed to a thickness of several micrometers in consideration of the process cost and wafer warpage. This lower insulating layer 20 is an optional component. That is, the trenches 402 and 404 are formed in the substrate 10 and the trenches 402 and 404 are filled with the insulating layer 50, as described later, without the lower insulating layer 20, The end face of the substrate 10 is polished so as to expose the insulating layer 50 filled in the unit cells 402 and 404 so that the electrical leakage can be cut off by blocking the electrical leakage path to the adjacent unit devices, The electric characteristics in the high-frequency region of the semiconductor device are greatly improved.

The capacitor thin film pattern 30 is formed on one surface of the substrate 10. For example, when the present embodiment includes the lower insulating layer 20, the capacitor thin film pattern 30 is formed on the upper surface of the lower insulating layer 20, and the present embodiment does not include the lower insulating layer 20 The capacitor thin film pattern 30 is formed directly on one surface of the substrate 10. [

The capacitor thin film pattern 30 includes a first metal layer 310, a capacitor insulating layer 324, and a second metal layer 334. Since this structure is general, a detailed description thereof will be omitted. Reference numeral 322 denotes an insulating layer formed together in the process of forming the capacitor insulating layer 324 and reference numeral 332 denotes an insulating layer formed together in the process of forming the second metal layer 334. [

The trenches 402 and 404 are formed by etching the substrate 10 on which the capacitor thin film pattern 30 is formed to define the unit area of the capacitor according to the present embodiment. Since the insulating layer 50 filled in the trenches 402 and 404 is for securing electrical insulation, the wider the trenches 402 and 404, the more favorable the insulating property is. For example, in the case of application band of several GHz, sufficient insulation can be ensured if the condition that the width of the trenches 402 and 404 is about 10um or more is satisfied.

The insulating layer 50 is formed on the substrate 10 while filling the trenches 402 and 404 and the metal layers constituting the capacitor, that is, the first metal layer 310 and the second metal layer 310, Capacitor wiring wirings 502 and 504 are formed to expose the capacitor wiring 334.

The capacitor electrode wirings 602 and 604 are formed by filling the capacitor wiring wirings 502 and 504 with a conductive material.

The capacitor according to an embodiment of the present invention is formed by polishing a surface of the substrate 10 opposite to the one surface of the substrate 10 on which the capacitor thin film pattern 30 is formed to form trenches 402 and 404 The insulating layer 50 is exposed. According to this structure, it is possible to block the electrical leakage to the adjacent unit devices to block the electrical loss, thereby greatly improving the electrical characteristics in the high frequency region of the capacitor, which is the final product. More specifically, it is possible to improve the performance of the entire system IC by greatly improving the electrical loss characteristic of the capacitor in the silicon-based high-frequency circuit, and it is possible to implement a SoC (System on a Chip) It is possible to mass-produce large diameter IPD (Integrated Passive Device) and interposer based on lossy silicon for application.

FIG. 4 is a process flow chart of a method of manufacturing a capacitor according to an embodiment of the present invention, and FIGS. 5 to 10 are process sectional views of a method of manufacturing a capacitor according to an embodiment of the present invention.

4, a method of manufacturing a capacitor according to an embodiment of the present invention includes forming a thin film pattern (S110), forming a trench (S120), forming an insulating layer (S130), forming a wiring hole (S140) An electrode wiring forming step S150 and a substrate polishing step S160.

5, in the thin film pattern formation step S110, a process of forming the capacitor thin film pattern 30 on one surface of the substrate 10 is performed.

The substrate 10 may be a silicon substrate having lossy characteristics. One surface of the substrate 10 is a surface on which the capacitor thin film pattern 30 is formed, and the other surface of the substrate 10 is opposite to the surface.

A process of forming the lower insulating layer 20 on one surface of the substrate 10 may be performed before the capacitor thin film pattern 30 is formed. The lower insulating layer 20 functions to reduce the electrical loss of the silicon having the oil loss characteristic. For example, the lower insulating layer 20 may be a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ), and may be formed to a thickness of several micrometers in consideration of the process cost and wafer warpage. This lower insulating layer 20 is an optional component. That is, even if the lower insulating layer 20 is not provided, the trenches 402 and 404 are formed in the substrate 10, and the insulating layer 50 is filled in the trenches 402 and 404, The end face of the substrate 10 is polished so as to expose the insulating layer 50 filled in the unit cells 402 and 404 so that the electrical leakage can be cut off by blocking the electrical leakage path to the adjacent unit devices, The electric characteristics in the high-frequency region of the semiconductor device are greatly improved.

The capacitor thin film pattern 30 is formed on one side of the substrate 10. For example, when the present embodiment includes forming the lower insulating layer 20, the capacitor thin film pattern 30 is formed on the upper surface of the lower insulating layer 20 and the present embodiment is formed on the lower insulating layer 20, The capacitor thin film pattern 30 is formed directly on one surface of the substrate 10. In this case,

The capacitor thin film pattern 30 is formed by sequentially forming a patterned first metal layer 310, a capacitor insulating layer 324, and a second metal layer 334 in the form of a thin film. Since these processes are general, a detailed description thereof will be omitted.

6, in the trench formation step S120, a process of forming the trenches 402 and 404 defining the unit area of the capacitor by etching the substrate 10 on which the capacitor thin film pattern 30 is formed is performed . Since the insulating layer 50 filled in the trenches 402 and 404 through the insulating layer forming step S130 to be described later is for securing the electrical insulation property, the insulating property is ensured as the width of the trenches 402 and 404 becomes wider It becomes advantageous. For example, in the case of application band of several GHz, sufficient insulation can be ensured if the condition that the width of the trenches 402 and 404 is about 10um or more is satisfied.

7, in the insulating layer forming step S130, a process of forming the insulating layer 50 on the trenches 402 and 404 and the substrate 10 is performed. For example, in the insulating layer forming step S130, the trenches 402 and 404 and the substrate 10 are patterned using organic lamination, spin coating or chemical vapor deposition, The insulating layer 50 may be formed on the insulating layer 50. An organic lamination method which is advantageous from the viewpoint of cost for forming the insulating layer 50 is preferable, but a spin coating method or a chemical vapor deposition method is also applicable according to the width and depth of the trenches 402 and 404.

8, in the wiring hole forming step S140, the metal layer constituting the capacitor, that is, the first metal layer 310 and the second metal layer 334 are exposed in the insulating layer 50, The process of forming the grooves 502 and 504 is performed.

9, in the capacitor electrode wiring formation step S150, a process of forming the capacitor electrode wirings 602 and 604 by filling the capacitor wiring wirings 502 and 204 with a conductive material is performed.

10, polishing of the other surface of the substrate 10 is performed so that the insulating layer 50 formed on the trenches 402 and 404 is exposed in the substrate polishing step S160. This process can be performed by chemical polishing or mechanical polishing.

When the method of manufacturing a capacitor according to an embodiment of the present invention is performed as described above, the other surface of the substrate 10, that is, the opposite surface of the substrate 10 on which the capacitor thin film pattern 30 is formed is polished, 402, and 404 are exposed. According to this structure, it is possible to block the electrical leakage to the adjacent unit devices to block the electrical loss, thereby greatly improving the electrical characteristics in the high frequency region of the capacitor, which is the final product. More specifically, it is possible to improve the performance of the entire system IC by greatly improving the electrical loss characteristic of the capacitor in the silicon-based high-frequency circuit, and it is possible to implement a SoC (System on a Chip) It is possible to mass-produce large diameter IPD (Integrated Passive Device) and interposer based on lossy silicon for application. In addition, the electric characteristics of the capacitor can be effectively oriented through a simple process such as trench formation, formation of an insulating layer, and polishing of the substrate 10. [

FIG. 11 is a cross-sectional view of a passive element including a capacitor and an inductor according to an embodiment of the present invention, and FIG. 12 is a plan view of a passive element including a capacitor and an inductor according to an embodiment of the present invention.

11 and 12, a passive device including a capacitor and an inductor according to an embodiment of the present invention includes a substrate 10, a lower insulating layer 20, a capacitor thin film pattern 30, The insulating layer 50, the capacitor electrode wirings 602 and 604, and the inductor thin film pattern 606. The trenches 402, 404, 406,

The substrate 10 may be a silicon substrate having lossy characteristics. One surface of the substrate 10 is a surface on which a capacitor thin film pattern 30 and an inductor thin film pattern 606 to be described later are formed and the other surface of the substrate 10 is opposite to the surface.

The lower insulating layer 20 is formed on one surface of the substrate 10 and functions to reduce the electrical loss of the silicon having the oil loss characteristic. For example, the lower insulating layer 20 may be a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ), and may be formed to a thickness of several micrometers in consideration of the process cost and wafer warpage. This lower insulating layer 20 is an optional component. That is, the trenches 402, 404, 406 and 408 are formed in the substrate 10 and the insulating layer 50 (not shown) is formed in the trenches 402, 404, 406 and 408, The other surface of the substrate 10 is polished so that the insulating layer 50 filled in the trenches 402, 404, 406 and 408 is exposed to block the path of electrical leakage to the adjacent unit devices, And the electrical characteristics in the high frequency region of the passive element including the capacitor and the inductor, which are the final products, are greatly improved.

The capacitor thin film pattern 30 and the inductor wiring thin metal pattern 336 are formed on one surface of the substrate 10 and can be formed simultaneously through the same process.

For example, when the present embodiment includes the lower insulating layer 20, the capacitor thin film pattern 30 and the inductor wiring thin film metal pattern 336 are formed on the upper surface of the lower insulating layer 20, The capacitor thin film pattern 30 and the thin film metal pattern 336 for inductor wiring are formed on one surface of the substrate 10 when the insulating layer 20 is not included.

The capacitor thin film pattern 30 includes a first metal layer 310, a capacitor insulating layer 324, and a second metal layer 334 patterned in a thin film form. The inductor wiring thin metal pattern 336 may be formed together with the second metal layer 334 in the second metal layer forming process and the inductor insulating layer 326 may be formed under the inductor wiring thin metal pattern 336 . The inductor insulation layer 326 may be formed together with the capacitor insulation layer 324 in the capacitor insulation layer formation process.

The trenches 402, 404, 406 and 408 are formed by etching the substrate 10 on which the capacitor thin film pattern 30 and the inductor wiring thin metal pattern 336 are formed to define unit areas of the capacitor and the inductor. Since the insulating layer 50 filled in the trenches 402, 404, 406 and 408 is intended to secure electrical insulation, the wider the trenches 402, 404, 406 and 408, the more favorable the insulation is. For example, in the case of application band of several GHz, sufficient insulation can be ensured if the condition that the width of the trenches 402, 404, 406, 408 is about 10um or more is satisfied.

The insulating layer 50 is formed on the substrate 10 while filling the trenches 402, 404, 406 and 408. The insulating layer 50 is formed with metal layers, that is, a first metal layer 310, Capacitor wiring holes 502 and 504 for exposing the second metal layer 334 and inductor wiring holes 506 and 508 for exposing the inductor wiring thin metal pattern 336 are formed.

The capacitor electrode wirings 602 and 604 are formed by filling the capacitor wiring wirings 502 and 504 formed in the insulating layer 50 with a conductive material.

The inductor thin film pattern 606 is made of a conductive material formed on the surface of the insulating layer 50 and the wiring holes 506 and 508 for inductors formed in the insulating layer 50. The inductor thin film pattern 606 formed on the surface of the insulating layer 50 has a spiral shape.

A passive element including a capacitor and an inductor according to an exemplary embodiment of the present invention includes a passive element including a capacitor and an inductor connected to one surface of a substrate 10 on which a capacitor thin film pattern 30 and an inductor thin film pattern 606 are formed, And the insulating layer 50 formed on the trenches 402, 404, 406, and 408 is exposed. According to this structure, the electrical leakage can be blocked by blocking the electrical leakage to the adjacent unit devices, thereby greatly improving the electrical characteristics in the high frequency region of the passive element including the final product, the capacitor and the inductor. More specifically, it is possible to improve the performance of the entire system IC by greatly improving the electrical loss characteristic of the passive element in the silicon-based high-frequency circuit, and it is possible to implement the SoC (System on a Chip) which integrates all the RF circuits, It is possible to mass-produce large diameter IPD (Integrated Passive Device) and interposer based on lossy silicon for package application.

FIG. 13 is a process flow diagram of a passive device manufacturing method including a capacitor and an inductor according to an embodiment of the present invention, and FIGS. 14 to 19 illustrate a passive device manufacturing method including a capacitor and an inductor according to an embodiment of the present invention Fig.

Referring to FIG. 13, a passive device manufacturing method including a capacitor and an inductor according to an embodiment of the present invention includes a thin film pattern forming step S210, a trench forming step S220, an insulating layer forming step S230, A capacitor electrode wiring formation step S250, an inductor thin film pattern formation step, and a substrate polishing step S270.

14, the process of forming the capacitor thin film pattern 30 and the inductor wiring thin film metal pattern 336 on one side of the substrate 10 is performed in the thin film pattern formation step (S210).

The substrate 10 may be a silicon substrate having lossy characteristics. One surface of the substrate 10 is a surface on which a capacitor thin film pattern 30 and an inductor wiring thin film metal pattern 336 are formed and the other surface of the substrate 10 is a surface opposite to the other surface.

A process of forming the lower insulating layer 20 on one surface of the substrate 10 may be performed before forming the capacitor thin film pattern 30 and the thin metal pattern 336 for wiring the inductor. The lower insulating layer 20 functions to reduce the electrical loss of the silicon having the oil loss characteristic. For example, the lower insulating layer 20 may be a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _x ), and may be formed to a thickness of several micrometers in consideration of the process cost and wafer warpage. This lower insulating layer 20 is an optional component. That is, even if the lower insulating layer 20 is not provided, the trenches 402, 404, 406, and 408 are formed in the substrate 10, The other surface of the substrate 10 is polished so that the insulating layer 50 filled in the trenches 402, 404, 406 and 408 is exposed to block the path of electrical leakage to the adjacent unit devices, And the electrical characteristics in the high frequency region of the passive element including the capacitor and the inductor, which are the final products, are greatly improved.

The capacitor thin film pattern 30 and the thin metal pattern 336 for wiring the inductor are formed on one surface of the substrate 10 and can be simultaneously formed through the same process.

For example, when the present embodiment includes the lower insulating layer 20, the capacitor thin film pattern 30 and the thin film metal pattern 336 for wiring the inductor are simultaneously formed on the upper surface of the lower insulating layer 20 through the same process The capacitor thin film pattern 30 and the inductor wiring thin film metal pattern 336 are simultaneously formed on one side of the substrate 10 through the same process when the lower insulating layer 20 is not included in the present embodiment.

The capacitor thin film pattern 30 includes a first metal layer 310, a capacitor insulating layer 324, and a second metal layer 334 patterned in a thin film form. The inductor wiring thin metal pattern 336 may be formed together with the second metal layer 334 in the second metal layer forming process and the inductor insulating layer 326 may be formed under the inductor wiring thin metal pattern 336 . The inductor insulation layer 326 may be formed together with the capacitor insulation layer 324 in the capacitor insulation layer formation process.

15, in the trench forming step S220, the substrate 10 on which the capacitor thin film pattern 30 and the inductor wiring thin film metal pattern 336 are formed is etched to form a capacitor and a trench 402, 404, 406, and 408 are formed. The insulating layers 50 filled in the trenches 402, 404, 406 and 408 through the insulating layer forming step S230 to be described later are for securing the electrical insulation. Therefore, the trenches 402, 404, 406, The wider the width, the better the insulation is secured. For example, in the case of application band of several GHz, sufficient insulation can be ensured if the condition that the width of the trenches 402, 404, 406, 408 is about 10um or more is satisfied.

16, the insulating layer 50 is formed on the trenches 402, 404, 406, and 408 and the substrate 10 in the insulating layer forming step S230. For example, in the insulating layer forming step S230, the trenches 402, 404, 406, and 408 are formed by using organic lamination, spin coating, or chemical vapor deposition And may be configured to form an insulating layer 50 on the substrate 10. An organic lamination method which is advantageous from the viewpoint of cost for forming an insulating layer is preferable, but a spin coating method or a chemical vapor deposition method is also applicable according to the width and depth of the trenches 402, 404, 406, 408.

17, in the wiring hole forming step S240, the metal layer constituting the capacitor, that is, the first metal layer 310 and the second metal layer 334 are exposed in the insulating layer 50, And the inductor wiring holes 506 and 508 are formed so as to expose the inductor wiring thin film metal layer.

18, a process of forming the capacitor electrode wirings 602 and 604 by filling the capacitor wiring wirings 502 and 504 with a conductive material is performed in the capacitor electrode wiring formation step S250, In the thin film pattern formation step S260, the inductor wiring holes 506 and 508 formed in the insulating layer 50 are filled with a conductive material while the insulating layer 50 has a spiral shape, for example, The process of forming the inductor thin film pattern 606 having the inductor thin film pattern 606 is performed.

19, polishing of the other surface of the substrate 10 is performed so that the insulating layer 50 formed on the trenches 402, 404, 406, and 408 is exposed in the substrate polishing step S270. This process can be performed by chemical polishing or mechanical polishing.

The passive element manufacturing method including the capacitor and the inductor according to the embodiment of the present invention described above can be applied to the substrate 10 in which the capacitor thin film pattern 30 and the inductor thin film pattern 606 are formed, The opposite surface opposite to the one surface of the trenches 10 is polished so that the insulating layer 50 formed on the trenches 402, 404, 406, and 408 is exposed. According to this structure, the electrical leakage can be blocked by blocking the electrical leakage to the adjacent unit devices, thereby greatly improving the electrical characteristics in the high frequency region of the passive element including the capacitor as the final product. More specifically, it is possible to improve the performance of the entire system IC by greatly improving the electrical loss characteristic of the passive element in the silicon-based high-frequency circuit, and it is possible to implement the SoC (System on a Chip) which integrates all the RF circuits, It is possible to mass-produce large diameter IPD (Integrated Passive Device) and interposer based on lossy silicon for package application.

Hereinafter, the performance characteristics of a capacitor according to an embodiment of the present invention will be described with reference to FIGS. 20 to 23, in comparison with a conventional capacitor.

Capacitors In particular, since MIM capacitors are mainly used for filtering or blocking DC signals or low frequency signals in a circuit, they are recognized as circuit shorts in a sufficiently high frequency region as compared to the capacitance of capacitors No loss should occur. However, MIM capacitors integrated on a lossy substrate such as silicon have very high insertion loss compared to commonly used capacitors because of the electrical loss to the substrate region located below the capacitor in the high frequency region There is a problem that application of the circuit is difficult.

However, according to the embodiment of the present invention described above, it has been confirmed through experiments that the insertion loss characteristics of the device can be improved by at least 10 times in the same capacitance value and area as compared with the conventional capacitor, The results are as follows.

FIGS. 20 and 21 are graphs comparing experimental values of S (Scattering) parameters when a conventional capacitor and a capacitor according to an embodiment of the present invention have a cross sectional area of 150 × 150 μm ² .

As is generally known, the S parameter is the most widely used circuit performance judgment value in RF, which means the ratio of the input signal to the output signal on the frequency distribution. For example, S (2,1) means the ratio of the signal input from port 1 to the signal output from port 2. That is, it is a numerical value indicating how much the signal inputted to the first port is outputted to the second port.

First, referring to FIG. 20, an S parameter in a conventional capacitor is disclosed when the frequency is 2.022 GHz and the cross-sectional area of the capacitor is 150 × 150 μm ² . In Fig. 20, dB (S (5,5)) is the reflection value and dB (S (6,5)) is the transmission value.

21, an S parameter in a capacitor according to an embodiment of the present invention is disclosed when the frequency is 2.022 GHz and the cross-sectional area of the capacitor is 150 x 150 um ² . In Fig. 21, dB (S (3,3)) is the reflection value and dB (S (4,3)) is the transmission value.

FIGS. 22 and 23 are graphs comparing experimental values of the S parameter for a conventional capacitor and a capacitor according to an embodiment of the present invention when the cross-sectional area of the capacitor is 300 × 300 μm ² .

Referring first to FIG. 22, S-parameters in a conventional capacitor are disclosed when the frequency is 2.022 GHz and the cross-sectional area of the capacitor is 300 × 300 μm ² . In Fig. 22, dB (S (7,7)) is the reflection value and dB (S (8,7)) is the transmission value.

Referring now to FIG. 23, an S parameter in a capacitor according to an embodiment of the present invention is disclosed when the frequency is 2.022 GHz and the cross-sectional area of the capacitor is 300 × 300 μm ² . 23, dB (S (1,1)) is a reflection value, and dB (S (2,1)) is a transmission value.

As described above in detail, according to the present invention, the other surface of the substrate 10, that is, the surface opposite to the one surface of the substrate 10 on which the passive element is formed is polished and formed in the trenches 402, 404, 406, Since the insulating layer 50 is exposed, the passage of electrical leakage to the adjacent unit devices can be cut off from the source, thereby preventing electrical loss. As a result, the electrical characteristics of the passive device in the high- There is an effect to be improved.

In addition, there is an effect that a passive element and a manufacturing method thereof capable of greatly improving the electrical loss characteristic of a passive element in a silicon-based high-frequency circuit and improving the performance of the entire system IC are provided.

Further, there is an effect that a passive element and a manufacturing method thereof capable of implementing an SoC (System on a Chip) that integrates all RF circuits are provided.

Also, there is an effect that a passive component passive component enabling mass production of a large-diameter IPD (Integrated Passive Device) and an interposer based on a lossy silicon for a high frequency package application is provided.

While the present invention has been described in connection with what is presently considered to be preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. In addition, it is a matter of course that various modifications and variations are possible without departing from the scope of the technical idea of the present invention by anyone having ordinary skill in the art.

10: substrate
20: Lower insulating layer
30: capacitor thin film pattern
310: first metal layer
324: Capacitor insulating layer
326: Inductor insulation layer
334: second metal layer
336: Thin metal pattern for inductor wiring
402, 404, 406, 408: trenches
50: insulating layer
502, 504: wiring hole for capacitor
506, 508: wiring hole for inductor
602, 604: Capacitor electrode wiring
606: Inductor thin film pattern
S110, S210: thin film pattern formation step
S120, S220: Trench forming step
S130, S230: Insulating layer forming step
S140, S240: wiring hole forming step
S150, S250: capacitor electrode wiring formation step
S260: Inductor thin film pattern formation step
S160, S270: Substrate polishing step

Claims (13)

A capacitor thin film pattern formed on one surface of a substrate;
A trench formed by etching a substrate on which the capacitor thin film pattern is formed to define a unit area of the capacitor;
An insulating layer formed on the substrate while filling the trenches, the insulating interlayer being formed with capacitor wiring holes exposing the metal layers constituting the capacitor; And
And a capacitor electrode wiring formed by filling a conductive material into the capacitor wiring holes,
And the other surface of the substrate is polished to expose an insulating layer formed on the trench. The method according to claim 1,
Wherein the substrate is made of a silicon material, and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern. A thin film pattern forming step of forming a capacitor thin film pattern on one surface of a substrate;
A trench forming step of forming a trench defining a unit area of the capacitor by etching the substrate on which the capacitor thin film pattern is formed;
Forming an insulating layer on the trench and the substrate;
A wiring hole forming step of forming capacitor wiring holes so that metal layers constituting the capacitor are exposed to the insulating layer;
Forming a capacitor electrode wiring by filling the capacitor wiring holes with a conductive material to form a capacitor electrode wiring; And
And polishing a second surface of the substrate such that an insulating layer formed on the trench is exposed. The method of claim 3,
Wherein the substrate is made of silicon, and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern. The method of claim 3,
Wherein the insulating layer is formed on the trench and the substrate by using organic lamination, spin coating or chemical vapor deposition in the insulating layer forming step , A method of manufacturing a capacitor. A capacitor thin film pattern formed on one surface of a substrate and a thin film metal pattern for inductor wiring;
A trench formed by etching the substrate on which the capacitor thin film pattern and the thin film metal pattern for inductor wiring are formed to define unit areas of the capacitor and the inductor;
An insulating layer formed on the substrate while filling the trenches, wherein the capacitor wiring holes expose the metal layers constituting the capacitor and the inductor wiring holes expose the inductor wiring thin metal pattern;
A capacitor electrode wiring formed by filling a conductive material into capacitor wiring holes formed in the insulating layer; And
And an inductor thin film pattern made of a conductive material formed on a surface of the insulating layer and wiring holes for inductors formed in the insulating layer,
Wherein the other surface of the substrate is polished to expose an insulating layer formed on the trench. The method according to claim 6,
Wherein the substrate is made of silicon and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern and the inductor wiring thin film metal pattern. The method according to claim 6,
Wherein the inductor thin film pattern formed on the surface of the insulating layer has a spiral shape. A thin film pattern forming step of forming a capacitor thin film pattern and a thin film metal pattern for inductor wiring on one surface of a substrate;
A trench forming step of forming a trench defining a unit area of the capacitor and the inductor by etching the substrate on which the capacitor thin film pattern and the thin film metal pattern for inductor wiring are formed;
Forming an insulating layer on the trench and the substrate;
A wiring hole forming step of forming inductor wiring holes such that the capacitor wiring holes and the inductor wiring thin film metal layer are exposed so that the metal layers constituting the capacitor are exposed to the insulating layer;
Forming a capacitor electrode wiring by filling the capacitor wiring holes with a conductive material to form a capacitor electrode wiring;
Forming an inductor thin film pattern on the surface of the insulating layer by filling the inductor wiring holes formed in the insulating layer with the conductive material; And
And polishing the other surface of the substrate so that the insulating layer formed on the trench is exposed. 10. The method of claim 9,
Wherein the substrate is made of a silicon material and a lower insulating layer is formed between one surface of the substrate and the capacitor thin film pattern and the inductor wiring thin film metal pattern. 10. The method of claim 9,
Wherein the insulating layer is formed on the trench and the substrate by using organic lamination, spin coating or chemical vapor deposition in the insulating layer forming step , A capacitor and an inductor. 10. The method of claim 9,
Wherein the step of forming the capacitor electrode wiring and the step of forming the inductor thin film pattern are performed in the same process. 10. The method of claim 9,
Wherein the inductor thin film pattern formed on the surface of the insulating layer in the step of forming the inductor thin film pattern has a spiral shape.

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