KR101599835B1 - Auxiliary power supply and user device including the same - Google Patents

Abstract

The auxiliary power supply device according to the embodiment of the present invention includes a power supply line, a power storage device, and a current limiter. The power storage device receives external power through a power line and stores auxiliary power. The current limiter reduces the overcurrent from the power supply line to the power storage device. The current limiter uses a variable resistor circuit to regulate the amount of current flowing to the power storage device. The variable resistance circuit reduces the overcharge current to the power storage device by increasing the resistance value during the initial operation, and reduces the charging time of the power storage device by decreasing the resistance value after a certain period of time.

Description

[0001] AUXILIARY POWER SUPPLY AND USER DEVICE INCLUDING THE SAME [0002]

The present invention relates to a user device, and more particularly to a user equipment including an auxiliary power supply.

A user device includes storage devices such as memory cards as well as electronic devices such as personal computers, digital cameras, camcorders, cellular phones and the like. Most of these user devices include a memory device for internally storing data.
The memory devices include volatile memories such as DRAM and SRAM, and nonvolatile memories such as EEPROM, FRAM, PRAM, MRAM, and Flash Memory. The volatile memory loses the stored data when the power is turned off, but the nonvolatile memory preserves the stored data even when the power is turned off.
The user equipment is powered from a power supply inside or outside. Here, the power source device may be a domestic or business power source such as 110V, 220V, etc., or may be an adapter or a charging device inside the user device. The user equipment may suffer catastrophic damage, such as data loss, due to sudden power off of the power supply (hereinafter referred to as Sudden Power Off).
For example, Flash memory-based SSD storage devices need to safeguard metadata and cache data, which can be lost due to power off. To solve this problem, manufacturers are developing various user devices to prepare for power-off of the power supply.

It is an object of the present invention to provide an auxiliary power supply device capable of reducing an overcurrent that can flow to a supercapacitor when an external power supply is supplied and shortening a charging time of the supercapacitor, and a user apparatus including the auxiliary power supply device.

The auxiliary power unit according to an embodiment of the present invention includes a power line for receiving external power; A power storage device that receives external power and stores auxiliary power; And a current limiter for reducing an overcurrent flowing from the power supply line to the power storage device, wherein the current limiter adjusts an amount of current flowing to the power storage device using a variable resistance circuit. The variable resistor circuit reduces the overcurrent flowing to the power storage device by raising the resistance value during the initial operation and decreases the resistance value after a predetermined time to reduce the charging time of the power storage device.
In an embodiment, the current limiter may further include a unidirectional device for reducing the reverse current flowing from the power storage device. The unidirectional device may be a diode.
In another embodiment, the variable resistor circuit includes: a resistor connected between the power supply line and the resistor node; A comparator for comparing a reference voltage and a voltage level of the resistor node; And a PMOS transistor coupled between the resistor node and the unidirectional device and controlled according to a voltage comparison of the comparator.
In yet another embodiment, the current limiter may further include a discharge circuit for discharging a parasitic capacitor of the power supply line. The discharge circuit may be a voltage distribution circuit connected between the power supply line and the ground terminal. Wherein the variable resistor circuit comprises: a resistor connected between the power supply line and the resistor node; A comparator for comparing a voltage level of the resistor node with a voltage distributed across the voltage divider circuit; And a PMOS transistor coupled between the resistor node and the unidirectional device and controlled according to a voltage comparison of the comparator.
A user apparatus according to an embodiment of the present invention includes an auxiliary power supply unit for providing auxiliary power; And a storage device for performing a power-off operation regardless of whether the auxiliary power is received when the main power is turned off. The auxiliary power supply includes a supercapacitor for storing the auxiliary power supply; And a variable resistor circuit for increasing the resistance value during the initial operation to increase the amount of current flowing to the storage device from the supercapacitor and for decreasing the resistance value after a predetermined time to shorten the charging time of the supercapacitor. The auxiliary power supply may increase the resistance value during the initial operation to reduce the overcurrent flowing to the supercapacitor.
As an embodiment, the resistance value of the variable resistance circuit may be determined by the power management unit. The power management unit may adjust an amount of auxiliary power of the power storage device according to an operation mode.

According to the present invention, it is possible to reduce the overcurrent and increase the boot efficiency during the initial operation. In addition, the present invention can reduce the charging time of the supercapacitor by lowering the resistance after a predetermined time elapses. Further, since the present invention further includes a discharge circuit, it is possible to effectively cope with the power-off operation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.
1 is a block diagram illustrating a user device according to an embodiment of the present invention. Referring to FIG. 1, a user device 100 includes an auxiliary power supply 110 and a storage device 120.
The user device 100 may be implemented as a personal computer (PC) or a portable electronic device such as a notebook computer, a mobile phone, a PDA (Personal Digital Assistant), and a camera. The user device 100 may operate using the auxiliary power stored in the auxiliary power supply 110 at the time of sudden power off (SPO) of the power supply. Hereinafter, a power supply will be used as a main power supply or an external power supply to distinguish it from the auxiliary power supply 110.
The main power supply (not shown) provides the external power required for operation of the user equipment 100. For example, the main power supply provides the power necessary for the storage device 120 to perform write, read, erase, or data backup operations. On the other hand, the main power supply may suddenly be cut off due to unforeseen circumstances such as user carelessness or device defects. This phenomenon is called sudden power off (SPO).
If the main power supply is turned off or off, the user device 100 is at risk of losing data stored in the storage device 120. In particular, if the data being processed at the storage device 120 is critical information, such as cache data or metadata, the user device 100 may suffer catastrophic damage due to power off.
The user device 100 shown in FIG. 1 includes an auxiliary power supply 110 to reduce losses due to power-off. Referring to FIG. 1, the auxiliary power supply 110 includes a supercapacitor 111, a power detector 112, a current limiter 113, a unidirectional element 114, and a switch 115.
The supercapacitor 111 is a power storage device capable of holding a high-capacity charge, and is used for storing an auxiliary power supply. The supercapacitor 111 provides auxiliary power to the user device 100 using the stored charge when the main power supply is turned off. The supercapacitor 111 may charge the charge when the user device 100 is powered up or in normal operation.
The power detector 112 is connected to the first power line PL1 and detects the power level of the main power unit. The power detector 112 detects the power supply level of the first power supply line PL1 at any power-off time, and generates the first control signal CTRL1 as a detection result.
The storage device 120 receives the first control signal CTRL1 and performs a power-off operation. The storage device 120 generates a second control signal CTRL2 to perform a constant power-off operation. The switch 115 is turned on in response to the second control signal CTRL2. When the switch 115 is turned on, the storage device 120 performs a power-off operation (SPO operation) using the auxiliary power of the supercapacitor 111. On the other hand, the user device 100 may be implemented such that the switch 115 is turned on in response to the first control signal CTRL1.
The current limiter 113 is connected between the supercapacitor 111 and the first power supply line PL1. The current limiter 113 is a protection device for protecting the supercapacitor 111. The current limiter 113 may limit an overcurrent flowing to the supercapacitor 111 or an overvoltage applied to the supercapacitor 111. [ In addition, the current limiter 113 can prevent reverse current that may flow from the supercapacitor 111 to the first power supply line PL1.
The current limiter 113 may be implemented as a diode, a resistor, a voltage clamp, or the like. The diode is used to prevent reverse current of the supercapacitor 111. The resistor is used to prevent the overcurrent flowing to the supercapacitor 111. The voltage clamp can prevent damage due to overvoltage when the super capacitor 111 is charged. FIG. 2 shows an example in which the current limiter 113a is implemented by a diode D, and FIG. 3 shows an example in which the current limiter 113b is implemented by a resistor Rc.
Referring to FIG. 2, the diodes 113a and 113b are connected between the first power line PL1 and the supercapacitor 111. The diodes 113a and 113b are turned on when the supercapacitor 111 is charged and unidirectional when the supercapacitor 111 is discharged. The diodes 113a and 113b cut off the reverse current that may flow from the supercapacitor 111 to the first power line PL1.
Referring to FIG. 3, the resistors 113b and Rc are connected between the first power supply line PL1 and the supercapacitor 111. FIG. Resistors 113b and Rc are passive resistors having a constant resistance. The resistors 113b and 113c may protect the supercapacitor 111 by blocking an in-rush current that may flow to the supercapacitor 111 when external power is supplied.
Referring again to FIG. 1, the unidirectional device 114 is connected to the main power supply through the first power supply line PL1 and to the storage device 120 via the second power supply line PL2. The unidirectional element 114 forms a current path from the first power supply line PL1 to the second power supply line PL2 according to the voltage difference between the first and second power supply lines PL1 and PL2 . That is, the unidirectional element 114 forms a current path if the voltage difference between the first and second power supply lines PL1 and PL2 is equal to or greater than a reference voltage, and blocks the current path if the voltage difference is less than the reference voltage. The unidirectional element 114 may be implemented through a diode.
The switch 115 is connected between the supercapacitor 111 and the second power supply line PL2. The switch 115 provides the auxiliary power of the supercapacitor 111 to the storage device 120 via the second power line PL2 in response to the second control signal CTRL2.
1, the storage device 120 may include a volatile memory (not shown) and a non-volatile memory (not shown). Volatile memory is a storage device that can lose data when power is turned off, including DRAM, SRAM, and the like. The nonvolatile memory is a storage device capable of storing data even when the power is turned off, and includes an EEPROM, a FRAM, a PRAM, a MRAM, and a flash memory. The volatile memory and the nonvolatile memory are supplied with power from the main power supply unit or the auxiliary power supply unit 110.
In general, a nonvolatile memory has a disadvantage in that data can be saved even if the power is turned off, but data processing speed is slow. To overcome this drawback, the storage device 120 reads the data stored in the nonvolatile memory into the volatile memory, and then processes the data using the volatile memory. The user device 100 backs up the data processed in the volatile memory to the nonvolatile memory.
The user device 100 shown in FIG. 1 can prevent reverse current by using a diode as the current limiter 113. The user device 100 may use a resistor as the current limiter 113 to reduce the stress of the supercapacitor that may be caused by the overcurrent.
4 is a block diagram illustrating a user device according to another embodiment of the present invention. Referring to FIG. 4, the user device 200 includes an auxiliary power supply 210 and a storage device 220. The auxiliary power supply 210 includes a supercapacitor 211, a power detector 212, a current limiter 213, a unidirectional element 214, and a switch 215. Here, the operation of the remaining elements except the current limiter 213 is as described in FIG. Hereinafter, the configuration and operation principle of the current limiter 213 will be described in detail.
The current limiter 213 is connected between the supercapacitor 211 and the first power supply line PL1. 4, the current limiter 213 includes a variable resistance circuit 231 and a unidirectional element 232. The variable resistance circuit 231 is used to prevent an overcurrent, and the unidirectional element 232 is used to prevent reverse current. The current limiter 213 shown in FIG. 4 can be implemented using various elements. 5 shows an example in which a current limiter 213a is implemented using a variable resistor Rv and a diode D and FIG. 7 shows an example in which a resistor R, a PMOS transistor P, a comparator C, And the current limiter 213b is implemented using the current limiter (D).
5, the current limiter 213a is connected between the first power supply line PL1 and the supercapacitor 211, and includes a variable resistor Rv and a diode D. As shown in FIG. The resistance value of the variable resistor Rv varies with time. 6 is a graph showing a change in resistance value of the variable resistor Rv shown in FIG. 5 over time.
Referring to FIG. 6, the resistance value of the variable resistor Rv is high during the initial operation of the user device (see FIG. 4, 200) and goes down over time. Here, the initial operation is performed when the user device 200 is powered on and for a predetermined time. The time required for performing the initial operation (for example, 13 seconds) is the time required for the booting operation or the ID command exchange operation. The initial operating time is often set in the user's manual of the user equipment.
Unlike the variable resistor Rv, the general resistor Rc has a constant value regardless of the time. If the general resistor Rc has a high resistance value, the supercapacitor 211 can reduce the stress due to the overcurrent. However, the time for charging the supercapacitor 211 may be long. Conversely, if the general resistor (Rc) is low, the charging time is reduced, but the stress due to the overcurrent may increase.
The variable resistor Rv can compensate for the disadvantage of the general resistor Rc. Since the variable resistor Rv has a high resistance value during the initial operation, the overcurrent flowing to the supercapacitor 211 can be prevented. Also, since the variable resistor Rv sends most of the current supplied from the external power supply to the storage device 220 during the initial operation, the boot efficiency of the user device 200 can be increased. Also, since the variable resistor Rv lowers the resistance value over time, the charging time of the supercapacitor 211 can be reduced.
Referring again to FIG. 5, the diode D is a unidirectional element that turns on when the supercapacitor 211 is charged and turns off when discharging. The diode D can prevent a reverse current that may flow from the supercapacitor 211 to the first power line PL1.
7, the current limiter 213b includes a resistor R, a PMOS transistor P, a comparator C, and a diode D. Here, the resistor R is connected between the first power supply line PL1 and the resistor node N. [ The resistor R has a constant resistance value. The resistor R has a smaller resistance value than the general resistor (see FIG. 3, Rc) and reduces the overcurrent during the initial operation. According to an embodiment of the invention, resistor R may not be used.
The PMOS transistor P is connected between the resistor node N and the diode D and is controlled according to the output value of the comparator C. [ The comparator C has a (+) terminal for receiving the reference voltage Vref, a (-) terminal for receiving the voltage of the resistor node N, and an output terminal for providing the output voltage to the PMOS transistor P. The diode D is connected between the PMOS transistor P and the supercapacitor 211 and is controlled according to the output voltage of the comparator C. [
During the initial operation, most of the current is provided to the storage device (see FIG. 4, 220), and a small amount of trickle current is provided to the supercapacitor 211. The trickle current occurs in a section where the level of the resistance node N is smaller than the reference voltage Vref. That is, when the level of the resistance node N is smaller than the reference voltage Vref, the output voltage of the comparator C becomes high level. At this time, a small amount of trickle current flowing through the PMOS transistor P charges the supercapacitor 211.
If the level of the resistance node N becomes higher than the reference voltage Vref after a predetermined time, the output voltage of the comparator C becomes low level. At this time, the PMOS transistor P is turned on. When the PMOS transistor P is turned on, a large amount of current flows to the supercapacitor 211. [ By such a mechanism, the current limiter 213b shown in FIG. 7 not only can increase the charging time while reducing the overcurrent, but also can increase the boot efficiency during the initial operation.
8 is a block diagram illustrating a user device in accordance with another embodiment of the present invention. Referring to FIG. 8, the user device 300 includes an auxiliary power supply 310 and a storage device 320. The auxiliary power supply 310 includes a supercapacitor 311, a power detector 312, a current limiter 313, a unidirectional element 314, and a switch 315. Here, the operation of the remaining elements except the current limiter 313 is as described in FIG. Hereinafter, the configuration and operation principle of the current limiter 313 will be described in detail.
8, the current limiter 313 further includes a discharging circuit 333 in addition to the variable resistance circuit 331 and the unidirectional element 332. [ The variable resistance circuit 331 is used to prevent an overcurrent, and the unidirectional element 332 is used to prevent reverse current. The variable resistance circuit 331 and the unidirectional element 332 are as described in FIG. Hereinafter, the discharge circuit 333 will be described in detail.
Upon power-off, the power detector 312 detects the level of the first power supply line PL1 and provides the first control signal CTRL1 to the storage device 320. [ The power detector 312 must detect the level of the first power supply line PL1 within a short time to properly perform the power off operation regardless of the storage device 220. [
However, at the time of power-off, the first power supply line PL1 may have a parasitic capacitance. The parasitic capacitor PL1 may interfere with the operation of the power detector 312. [ When the parasitic capacitance is present in the first power supply line PL1, the power detector 312 can not accurately detect the power supply level when the level of the first power supply line PL1 suddenly drops. If the power detector 312 fails to detect a power-off instant, it will not be able to perform a power-off operation.
The discharging circuit 333 forms a discharging path between the first power line PL1 and the ground terminal. The discharge circuit 333 can remove the parasitic capacitance through the discharge path. The discharge circuit 333 can be implemented through various devices. 9 shows an example in which a discharge circuit is constituted by using a voltage distribution circuit.
9, the current limiter 313a includes a resistor R, a PMOS transistor P, a comparator C, a diode D, and a voltage divider circuit R1, R2. Here, the voltage dividing circuits R1 and R2 provide the divided voltage Vdvd to the (+) terminal of the comparator C.
During the initial operation, most of the current is provided to the storage device (see FIG. 8, 320), and a small amount of trickle current is provided to the supercapacitor 311. During the initial operation, the trickle current occurs in a section where the level of the resistance node N is less than the divided voltage Vdvd. That is, when the level of the resistance node N is smaller than the divided voltage Vdvd, the output voltage of the comparator C becomes high level. At this time, a small amount of trickle current flowing through the PMOS transistor P charges the supercapacitor 311.
After a certain time has elapsed, if the level of the N-node becomes higher than the distribution voltage Vdvd, the output voltage of the comparator C becomes low level. At this time, the PMOS transistor P is turned on. When the PMOS transistor P is turned on, a large amount of current flows to the supercapacitor 311. [ With such a mechanism, the current limiter 313a shown in FIG. 9 not only can speed up the charging time while reducing the overcurrent, but also can increase the boot efficiency during the initial operation.
A user device according to an embodiment of the present invention may be applied to or applied to various products. The user device may be a memory card, a USB memory, a solid state drive (SSD), or the like, as well as electronic devices such as a personal computer, a digital camera, a camcorder, a mobile phone, MP3, PMP, , A hard disk (HDD), or the like.
FIG. 10 is a block diagram illustrating an example in which a user device according to an embodiment of the present invention is implemented as an SSD. Referring to FIG. 10, an SSD system 1000 includes a host 1100 and an SSD 1200. The SSD 1200 exchanges signals with the host 1100 through a signal connector 1211 and receives power through a power connector 1221. The SSD 1200 includes a plurality of memory devices 1201 to 120n, an SSD controller 1210, and an auxiliary power supply 1220.
The plurality of memory devices 1201 to 120n are used as the storage medium of the SSD 1200. The plurality of memory devices 1201 to 120n may be implemented as a nonvolatile memory device (NVM) having a large storage capacity. The SSD 1200 mainly uses a flash memory, but a nonvolatile memory device such as PRAM, MRAM, ReRAM, and FRAM may be used in addition to the flash memory. In addition, the SSD 1200 may be implemented as a volatile memory device such as a DRAM or SRAM.
The plurality of memory devices 1201 to 120n may be connected to the SSD controller 1210 through a plurality of channels CH1 to CHn. One channel may be connected to one or more memory devices. The memory devices connected to one channel can be connected to the same data bus.
The SSD controller 1210 sends and receives the signal SGL to and from the host 1100 through the signal connector 1211. Here, the signal SGL may include a command, an address, data, and the like. The SSD controller 1210 writes data to the memory device or reads data from the memory device according to a command of the host 1100. The internal configuration of the SSD controller 1210 will be described in detail with reference to FIG.
The auxiliary power supply 1220 is connected to the host 1100 through a power connector 1221. [ The auxiliary power supply 1220 receives the power supply PWR from the host 1100 and can charge the supercapacitor (not shown). Meanwhile, the auxiliary power supply 1220 may be located in the SSD 1200 or may be located outside the SSD 1200. For example, the auxiliary power supply 1220 may be located on the main board and may provide auxiliary power to the SSD 1200. The auxiliary power supply 1220 can reduce the overcurrent during the initial operation and reduce the charging time of the supercapacitor after a certain period of time has elapsed.
11 is a block diagram illustrating an exemplary configuration of the SSD controller 1210 shown in FIG. Referring to FIG. 11, the SSD controller 1210 includes a central processing unit (CPU) 1211, a host interface 1212, a volatile memory 1213, and an NVM interface 1214.
The central processing unit 1211 analyzes and processes the signal SGL input from the host 1100 (see Fig. 10). The central processing unit 1211 controls the host 1100 or the nonvolatile memories 1201 to 120n through the host interface 1212 or the NVM interface 1214. [ The central processing unit 1211 controls the operation of the nonvolatile memories 1201 to 120n in accordance with the firmware for driving the SSD 1200.
The host interface 1212 provides interfacing with the SSD 1200 in response to the host 1100 protocol. The host interface 1212 is connected to the host 1212 by using a USB (Universal Serial Bus), a SCSI (Small Computer System Interface), a PCI express, an ATA, a PATA (Parallel ATA), a SATA (Serial ATA) 1100). The host interface 1212 may perform a disk emulation function to support the host 1100 to recognize the SSD 1200 as a hard disk drive (HDD).
The volatile memory (VM) 1213 temporarily stores write data provided from the host 1100 or data read from the nonvolatile memory. The volatile memory 1213 may store metadata or cache data to be stored in the nonvolatile memories 1201 to 120n. During the sudden power-off operation, the metadata and the cache data stored in the volatile memory 1213 are stored in the nonvolatile memories 1201 to 120n. The volatile memory (VM) 1213 may include DRAM, SRAM, and the like.
The NVM interface 1214 scatters the data transferred from the volatile memory 1213 to each of the channels CH1 to CHn. The NVM interface 1214 transfers the data read from the nonvolatile memories 1201 to 120n to the volatile memory 1213. Here, the NVM interface 1214 can use the interface method of the NAND flash memory. In other words, the SSD controller 1210 may be configured according to the NAND flash memory interface scheme
12 is a block diagram showing an example in which a user device is implemented as a semiconductor memory device. 12, the semiconductor memory device 2000 includes a memory controller 2100 and a flash memory 2200. The semiconductor memory device 2000 may store both volatile memory and storage devices including nonvolatile memory such as a memory card (e.g., SD, MMC, etc.) or a removable removable storage device .
12, the memory controller 2100 includes a central processing unit (CPU) 2110, a host interface 2120, a random access memory (RAM) 2130, a flash interface 2140, and an auxiliary power supply 2150 . The auxiliary power supply 2150 may be located in the memory controller 2100 or may be located outside. The auxiliary power supply 2150 has the same configuration and operation principle as the previous embodiments.
The semiconductor memory device 2000 is used in connection with a host. The semiconductor memory device 2000 exchanges data with the host through the host interface 2120 and exchanges data with the flash memory 2200 via the flash interface 2140. [ The semiconductor memory device 2000 receives power from a host to perform an internal operation. The auxiliary power supply 2150 can reduce the overcurrent during the initial operation and reduce the charging time of the supercapacitor after a certain period of time has elapsed.
13 is a block diagram illustrating an example of implementing a user device as an electronic device. The electronic device 3000 may be implemented as a personal computer (PC) or a portable electronic device such as a notebook computer, a mobile phone, a PDA (Personal Digital Assistant), and a camera.
13, the user device 3000 includes a semiconductor memory device 3100, a power supply device 3200, an auxiliary power supply device 3250, a central processing unit 3300, a RAM 3400, and a user interface 3500. [ . Semiconductor memory device 3100 includes flash memory 3110 and memory controller 3120. The auxiliary power supply 3250 can reduce the overcurrent during the initial operation and reduce the charging time of the supercapacitor after a certain period of time has elapsed.
14 is a block diagram illustrating a power management system including a power management unit and an auxiliary power source. Referring to FIG. 14, the power management system 4000 includes a host 4100 and a user device 4200. The user device 4200 includes an auxiliary power supply 4210, a power management unit 4220, and a storage device 4230.
The auxiliary power supply 4210 may reduce the overcurrent and increase the boot efficiency during the initial operation. The auxiliary power supply 4210 can reduce the charging time of the supercapacitor by lowering the resistance after a predetermined time has elapsed. Further, the auxiliary power supply 4210 further includes a discharging circuit, so that the auxiliary power supply 4210 can effectively cope with any power-off operation.
The power management unit 4220 is a device for managing the power consumption of the user device 4200. [ The power management unit 4220 can adjust the amount of charge of the supercapacitor according to the operation mode of the host 4100 (for example, active, idle, standby, sleep, etc.). The power management unit 4220 adjusts the amount of charge of the supercapacitor according to the operation mode, so that the voltage stress of the supercapacitor can be mitigated and the life of the supercapacitor can be increased.
The power management unit 4220 can receive a command (e.g., a power management command) from the host 4100 to adjust the amount of charge of the supercapacitor. In addition, the power management unit 4220 may generate a power management command by itself or adjust an amount of charge of the supercapacitor in response to an instruction from the internal controller without the host 4100 command. The operation method of the power management unit 4220 will be described in detail with reference to FIG.
On the other hand, the power management unit 4220 can adjust the variable resistance of the current limiter. Referring again to Figures 4 and 5, the current limiter 213 includes a variable resistance circuit. The variable resistor Rv in Fig. 5 can adjust the resistance value under the control of the power source management unit 4220. Fig.
Storage device 4230 may include a controller (not shown) and storage means (not shown). The storage means may include an SSD, a HDD, a flash memory, and the like. The storage device 4230 may perform a power-off operation using an auxiliary power source of the auxiliary power source 4210 during a power-off operation.
15 is a graph for explaining an operation method of the power management unit shown in FIG. Referring to FIG. 15, the horizontal axis represents time (T) and the vertical axis represents charged amount (Q) of the supercapacitor.
When the power management system 4000 is powered on in the interval t0 to t1, the auxiliary power supply 4210 charges the supercapacitor. The period from t1 to t2 represents an active working state or a working state in which the user device 4200 normally operates. In the working state, the supercapacitor is charged to such a degree that it can sufficiently perform the power-off operation.
The period from t2 to t3 represents an idle state in which the user device 4200 does not normally operate. The power management unit 4220 discharges part of the charge of the supercapacitor in the idle state, so that the charge amount can be adjusted. The power management unit 4220 can adjust the charge amount of the supercapacitor in a standby state or a sleep state in addition to the idle state. The power management unit 4220 may vary the charge amount according to each state.
The period from t3 to t4 indicates that the user device 4200 is put into the working state again. The power management unit 4220 prepares for power-off operations by recharging the supercapacitor. In a period from t4 to t5, when the power management system 4000 is powered off, the auxiliary power supply 4210 discharges the supercapacitor.
It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

1 is a block diagram illustrating a user device in accordance with an embodiment of the present invention.
Figures 2 and 3 are block diagrams illustrating the current limiter shown in Figure 1 by way of example.
4 is a block diagram illustrating a user device in accordance with another embodiment of the present invention.
5 is a block diagram illustrating an exemplary current limiter shown in FIG.
6 is a graph schematically showing a change in resistance value with time of the variable resistor shown in Fig.
7 is a block diagram illustrating an exemplary current limiter shown in FIG.
8 is a block diagram illustrating a user device in accordance with another embodiment of the present invention.
FIG. 9 is a block diagram illustrating the current limiter shown in FIG. 8 by way of example.
10 is a block diagram showing an example in which the auxiliary power unit is applied to a solid state drive.
11 is a block diagram illustrating an exemplary SSD controller shown in FIG.
12 is a block diagram showing an example in which the auxiliary power supply is applied to the semiconductor memory device.
13 is a block diagram showing an example in which the auxiliary power unit is applied to a user apparatus.
14 is a block diagram illustrating a power management system including a power management unit and an auxiliary power source.
15 is a graph for explaining an operation method of the power management unit shown in FIG.

Claims (20)

A power supply line for receiving external power; A power storage device that receives external power and stores auxiliary power; And And a current limiter for reducing an overcurrent flowing from the power supply line to the power storage device upon external power supply, Wherein the current limiter adjusts an amount of current flowing to the power storage device using a variable resistance circuit, The variable resistor circuit includes: A resistor coupled between the power supply line and the resistor node; A comparator for comparing a reference voltage and a voltage level of the resistor node; A unidirectional element for reducing a reverse current flowing from the power storage device; And And a transistor coupled between the resistor node and the unidirectional element, the transistor being controlled according to a voltage comparison of the comparator. The method according to claim 1, Wherein the variable resistor circuit reduces an overcurrent flowing to the power storage device by raising a resistance value during an initial operation and decreases a resistance value after a predetermined time to reduce a charging time of the power storage device. delete The method according to claim 1, Wherein the unidirectional element is a diode. delete The method according to claim 1, Wherein the current limiter further comprises a discharge circuit for discharging a parasitic capacitor of the power supply line. The method according to claim 6, Wherein the discharge circuit is a voltage distribution circuit connected between the power supply line and the ground terminal. 8. The method of claim 7, Wherein the comparator compares the voltage level of the resistor node with the distribution voltage of the voltage divider circuit, Wherein the transistor is a PMOS transistor coupled between the resistor node and the unidirectional device and controlled according to a voltage comparison of the comparator. The method according to claim 1, Wherein the power storage device is a supercapacitor. Auxiliary power supply providing auxiliary power; And And a storage device for performing a power-off operation regardless of whether the auxiliary power is received when the main power is turned off, The auxiliary power supply A power storage device for storing the auxiliary power; And And a current limiter for controlling an amount of current flowing to the power storage device using a variable resistance circuit, The variable resistor circuit includes: A resistor connected between the power supply line and the resistor node; A comparator for comparing a reference voltage and a voltage level of the resistor node; An echo element for reducing a reverse current flowing from the power storage device to a power supply line; And And a transistor coupled between the resistor node and the unidirectional element, the transistor being controlled according to a voltage comparison of the comparator. 11. The method of claim 10, Wherein the variable resistor circuit increases the resistance value during the initial operation to increase the amount of current flowing to the storage device from the power storage device and decreases the resistance value after a predetermined time to shorten the charging time of the power storage device. delete delete 11. The method of claim 10, Wherein the current limiter further comprises a discharge circuit for discharging the parasitic capacitor of the power supply line. 12. The method of claim 11, Further comprising a power management unit for managing power consumption of the storage device. 16. The method of claim 15, Wherein the power management unit adjusts the resistance value of the variable resistor circuit. 16. The method of claim 15, Wherein the power management unit adjusts the amount of auxiliary power of the power storage device according to an operation mode of the host. 16. The method of claim 15, Wherein the power management unit receives an instruction from the host and adjusts the amount of auxiliary power of the power storage device. 12. The method of claim 11, Wherein the auxiliary power supply and the storage device are implemented as a solid state drive (SSD). 12. The method of claim 11, Wherein the auxiliary power supply and the storage device are implemented as a removable storage device.

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