KR101593703B1 - Apparatus for performing Universal Variable-length 8-Parallel Reed-Solomon Encoder, decoder and method therefor - Google Patents

Abstract

A variable-length 8-parallel Reed-Solomon code apparatus according to an embodiment of the present invention includes a variable length 8-parallel message symbol for each cycle determined by a code length information signal, A rearrangement determination unit for rearranging the input message symbols into variable length Reed-Solomon codes based on the code length information signal, and a rearranged variable-length Reed-Solomon code in a partial generation polynomial A partial generation polynomial operation unit; a parity symbol storage unit for storing operation result values of the partial generation polynomial; And an output unit for outputting the stored operation result value or the input variable length 8 parallel message symbol according to the control signal generated by the reordering unit.

Description

[0001] The present invention relates to a variable-length 8-parallel reed-solomon code device and a decoding method thereof, and more particularly to a variable length 8-parallel reed-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Reed-Solomon multiplexing apparatus and method, and more particularly, to a Reed-Solomon multiplexing apparatus and method applicable to a variable length codeword.

The invention disclosed in this specification is derived from the research carried out as part of the IT original technology development project of the Ministry of Knowledge Economy and Industrial Technology Evaluation and Management. [Project Number: 2009-F-047-01, Title: Open mmWave Wireless Interface Platform Technology development].

WPAN is a wireless network technology that enables identification of digital devices and providing various application services within the range of mobile or stationary communication. mmWAVE is generally a band of 30 to 300 GHz and means an electromagnetic wave having a wavelength in millimeters (mm). The advantage of mmWAVE is that the wavelength is short due to the nature of the radio wave, the antenna and the device can be made small and light, and the bandwidth can be widely used, thereby securing a high data transmission rate and being suitable for short distance communication and high frequency reuse rate . On the other hand, mmWAVE is not suitable for long-distance wireless communication because it has strong linearity of signal and interference with various environmental factors. However, it is highly useful as point-to-point wireless fixed communication and near-distance communication within 100m. Due to the characteristics of mmWAVE, the system needs FEC architecture to reduce bit error rate (BER) at a high speed while guaranteeing high data rate. In 802.15.3c, Reed-Solomon decoder is a standard for Forward Error Correction .

However, in the prior art, only fixed-length data codewords can be processed through a Reed-Solomon encoder / decoder. Therefore, research on a Reed-Solomon encoder / decoder capable of processing all variable-length data codeword symbols must be continuously performed.

The present invention provides a general-purpose variable-length 8-parallel-structured Reed-Solomon encoder, decoder and method capable of processing all variable-length codes in a conventional structured system capable of processing only fixed-length codes.

In addition, the present invention employs an arithmetic method for using an 8-parallel structure of a Reed-Solomon encoder, a structure / operation method of a rearrangement block for processing variable-length data symbols, and an 8-parallel structure of a Reed- A structure and calculation method of a rearrangement block for processing variable length data symbols, and an 8-parallel error correction structure / calculation method of an error correction block.

The variable length 8 parallel Reed-Solomon code apparatus according to an embodiment of the present invention includes an input unit for receiving a variable length 8 parallel message symbol every cycle of a cycle determined by a code length information signal, A rearrangement determination unit for rearranging the rearranged variable-length Reed-Solomon codes into variable length Reed-Solomon codes based on the length information signal, a partial generation polynomial calculation unit for calculating the rearranged variable-length Reed-Solomon codes using eight partial generation polynomials, A parity symbol storage unit for storing a result value and an output unit for outputting the stored operation result value or the inputted variable length 8 parallel message symbol according to a control signal generated by the reordering unit.

In addition, the variable-length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention includes the steps of receiving a variable length 8 parallel message symbol every clock cycle during a cycle determined by a code length information signal, Rearranging the variable length Reed-Solomon code based on the code length information signal, performing an XOR operation on the reordered message value and the value stored in the register, calculating an arithmetic operation using the partial generator polynomial Storing a result of the calculation in a register, checking whether a message is received for the code length information signal with respect to the stored value, and outputting a parity symbol if the message is received by the code length information signal .

In the present invention, it is possible to design a general-purpose Reed-Solomon encoder and a decoder by designing to use a variable length code in a system in which only a conventional fixed length code can be used.

The present invention further improves data throughput by using an 8-parallel structure, which is useful for high-speed data processing.

1 is a diagram showing a structure of a conventional Reed-Solomon decoder.
2 is a diagram illustrating a structure of a Shortened RS (n, k) code based on RS (255, 239) codes.
FIG. 3 is a flowchart of a variable length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention.
4 is a diagram illustrating a process of rearranging eight types of variable length messages according to a code length information signal and encoding according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a structure of a variable-length 8-parallel Reed-Solomon code apparatus according to an embodiment of the present invention.
6 is a diagram illustrating a structure of a variable-length 8-parallel RS-Solomon decoding apparatus according to an embodiment of the present invention.
7 is a diagram illustrating a structure of an 8-parallel syndrome calculation unit according to an embodiment of the present invention.
8 is a diagram illustrating an 8-parallel error correction unit according to an embodiment of the present invention.
9 is a diagram illustrating an 8-parallel error correcting cell structure of an 8-parallel error correcting unit according to an embodiment of the present invention.
10 is a diagram illustrating a structure of a FIFO output unit according to an embodiment of the present invention.
11 is a diagram illustrating a data flow for an output latency and a reception wait time depending on a received codeword according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Reed-Solomon code is a FEC technology widely used in various applications such as magnetic, optical storage media, wired and satellite communication, and is a channel coding method capable of correcting random errors and burst errors occurring in communication channels. A Reed-Solomon code is a non-binary cyclic code consisting of symbols made up of m bits when m is a positive integer greater than 2, and a typical form is RS (n, k, t). The RS (n, k) code for the m-bit symbol is present at all n and k values satisfying the following conditions.

0 < k < n < 2m + 2

Where k is the number of data symbols to be coded and n is the number of coded symbols in the coded block. Most existing RS (n, k) codes are as follows.

(n, k) = (2 ^m-1 , 2 ^m-1 -2t)

Where t is the symbol error correction capability of the code, and n-k = 2t is the number of parity symbols.

The generation polynomial of the Reed-Solomon code in the Reed-Solomon coding algorithm takes the following form.

[Equation 1]

The order of the generator polynomial is equal to the number of parity symbols. Since the order of the generator-polynomial is 2t, the root of the polynomial must be exactly 2t consecutive powers of a. Since the Reed-Solomon code is a cyclic code, the systematic form of coding multiplies the message polynomial M (X) by X ^{n -k} and adds the parity polynomial p (X). That is, p (X) is the remainder obtained by dividing M (X) · X ^{n -k} by g (X).

&Quot; (2) &quot;

The encoded polynomial U (X) is represented by Equation (3).

&Quot; (3) &quot;

The encoded polynomial U (X) means that the root of g (X) is zero.

Since the encoded polynomial obtained through encoding can be contaminated by noise during transmission, if the received symbol includes an error, the error pattern can be expressed by Equation (4).

&Quot; (4) &quot;

Then, the encoded polynomial r (X) received as a contamination can be expressed by Equation (4) as the sum of the transmission encoding polynomial and the error pattern polynomial as follows.

&Quot; (5) &quot;

1 is a diagram showing a structure of a conventional Reed-Solomon decoder.

A commonly used Reed-Solomon decoder consists of three main parts that detect and correct errors. The result of the Syndrome Computation block S (x) is used in the Key Equation Solver (KES) block. The two polynomials of the outputs σ (x) and ω (x) It is used to find the magnitude value of the errors corresponding to the position. The received message is error corrected through the Reed-Solomon decoder. In addition, the FIFO memory is used as a buffer while the decoder performs error detection and correction. The depth of the FIFO memory is related to the total latency of the decoder.

The syndrome calculation value is a value that determines whether or not the received r (X) is contaminated with an error and can find an error pattern when it is contaminated by an error. The syndrome calculation is performed by substituting all the roots of g (X) into the received polynomial r (X). If r (X) is a legitimate encoded polynomial, then the result of syndrome computation is 0 since r (X) is U (X) and U (X) is divided by g (X). If the calculated result of the syndrome is not zero, it indicates that the received polynomial is contaminated from the error. The syndrome S consists of n-k symbols Si (i = 0, ..., n-k-1), and the calculation of the syndrome symbols can be expressed as:

&Quot; (6) &quot;

Since the calculation result of the syndrome symbol for U (X) is 0, the syndrome symbol can be expressed in the form of Equation (7).

&Quot; (7) &quot;

는 오류의 위치를 나타내고,

는 오류의 값을 나타낸다고 가정하면

는 다음 수학식 8와 같이 표현할 수 있다.If v errors in the channel

Indicates the location of the error,

Assuming that it represents the value of the error

Can be expressed by the following equation (8).

&Quot; (8) &quot;

이라고 하면

는 다음 수학식 9과 같이 표현할 수 있다.In Equation (8)

If you say

Can be expressed by the following equation (9).

&Quot; (9) &quot;

은 오류의 위치를 나타내고

은 오류의 값을 나타낸다.At this time

Indicates the location of the error

Represents the value of the error.

와 오류 값 다항식

을 구하기 위해 초기값을 정한다.

는 앞서 언급한 신드롬 다항식이다.The KES (Key Equation Solver) block can be implemented using the Euclidean algorithm, modified Euclidean or Berlekamp-Massey algorithms, and a division-free Euclidean algorithm and fast Euclidean structures are proposed . Among them, the modified Euclidean algorithm is easy to implement with a high-speed pipeline structure. The modified Euclidean algorithm eliminates the best-order term and reduces the order repeatedly.

And error value polynomial

To determine the initial value.

Is the above-mentioned syndrome polynomial.

의 값을 알아야 어떤 연산을 할지를 결정할 수 있다. 기존의 수정 유클리드 알고리즘 블록은

를 구하는 차수 비교 연산이 포함되었지만, pDCME (pipelined degree computationless modified Euclidean) 알고리즘 블록은 수정 유클리드 알고리즘 블록에서 차수 비교 연산을 제거한 형태이다.The operation of the modified Euclidean algorithm

To determine which operation to perform. The existing modified Euclidean algorithm block

The pipelined degree computationless modified Euclidean (pDCME) algorithm block is a form in which the degree comparison operation is removed from the modified Euclidean algorithm block.

Since the pDCME algorithm has an initial input and can estimate the range of the calculation result when knowing the input polynomial, it is possible to perform the order comparison by the input pattern and the relative degree depending on the result instead of the direct order comparison. That is, the control signal of the KES block can be generated without performing the order comparison operation. Equation (10) selectively performs the operation of pDCME according to the four patterns depending on the input values of C and D input in synchronization with the start signal.

&Quot; (10) &quot;

와 오류 값 다항식

를 구할 수 있다. 오류 위치 다항식은 오류의 위치를 나타내는

의 역수를 근으로 가지는 다항식이고 수학식 11와 같은 형태가 된다.The error location polynomial

And error value polynomial

Can be obtained. The error location polynomial represents the location of the error.

Is a polynomial having the inverse number of &lt; EMI ID = 11.0 &gt;

&Quot; (11) &quot;

의 미분다항식

는 수학식 12과 같이 표현할 수 있다. The value of the error can be obtained by the error polynomial and the differential polynomial of the error location polynomial. Error location polynomial

Differential polynomial of

Can be expressed by Equation (12).

&Quot; (12) &quot;

와

를 이용하여 오류 값

을 구할 수 있다.

Wow

Error value

Can be obtained.

&Quot; (13) &quot;

이면 실제 오류가 발생한 위치는 x^255-i이 된다.In Equation (13), the reciprocal of the root of the error locator polynomial represents the location where the actual error occurred,

, The position where the actual error occurred is x ^255-i .

It is possible to determine whether or not an error has occurred in the corresponding position in the error location polynomial and to obtain the final output whose error is corrected through the XOR operation of the error value and the output symbol passed through the FIFO.

2 is a diagram illustrating a structure of a Shortened RS (n, k) code based on RS (255, 239) codes.

Referring to FIG. 2, the shortened Reed-Solomon code is an RS (255, 239) based error correcting capability t = 8 code. In the RS (n, k) code, d number of zero symbols are added in front of a codeword . The shortened Reed-Solomon code generates n-k = 16 parity symbols and can use the same codeword type as RS (255,239) code.

In case of shortened RS code, the code symbol which is less than 2 ^m-1 is adjusted to 2 ^{m- 1} code length by using a zero symbol. Therefore, in the shortened RS code, the error location is found from the position after zero padding.

FIG. 3 is a flowchart of a variable length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention.

In step 310, the variable-length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention receives a variable length 8 parallel message symbol every clock cycle during a cycle determined by the code length information signal.

In step 320, a variable length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention receives a code length information signal.

In step 330, the variable-length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention rearranges the inputted message symbols into variable length Reed-Solomon codes based on the code length information signal.

In step 340, a variable-length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention performs an XOR operation on the reordered message values and the values stored in the registers.

In step 350, a variable length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention performs an operation using a partial generation polynomial for the computed value.

In step 360, the variable-length 8-parallel Reed-Solomon coding method according to an embodiment of the present invention stores the operation result in a register.

In step 370, the variable length 8 parallel Reed-Solomon coding method according to an embodiment of the present invention checks whether a message is received by a code length information signal with respect to a stored value.

In step 380, the variable length 8 parallel Reed-Solomon coding method according to an embodiment of the present invention outputs a parity symbol if a message is received as much as a code length information signal.

Variable-length Reed-Solomon codes are variable in length of received message / codeword symbols, unlike Reed-Solomon codes, which only process fixed length message / codewords. In the above-described RS (n, k), the n, k parameters can be changed into various forms, but the number of parity symbols is not changed for nk = 2t. The 8-parallel architecture can improve data throughput because eight message / codeword symbols are received and processed at a time and eight error corrected codewords are output.

When a variable length message symbol is received, the role of the code length information signal is important. Since the code length information signal is used for controlling the PERMUTATION and the operation execution time, if an incorrect code length information signal is input to the received message polynomial, an incorrect encoding process is performed.

The 8-parallel reed-solomon encoder can modify the equations to apply the parity polynomial p (x) to the 8-parallel structure. The 8-parallel structure for obtaining the parity polynomial p (x) can be expressed by Equation (14).

&Quot; (14) &quot;

Equation (14) is a set of 16 consecutive roots [? 0,? 1,? 2, ... g2 (x), g2 (x), g3 (x), g4 (x), g5 (x), and g5 (x) are calculated as shown in Equation (15) g6 (x), and g7 (x).

&Quot; (15) &quot;

Since derivation and expansion of partial generation polynomials are applied to parallel processing, the above equations can be applied to other parallel structures.

When a variable length message is received, a correct encoding equation must be calculated by rearranging the order of the message polynomial by inserting a zero symbol according to the variable length. The inserted zero symbol is determined by the received code length information signal together with the message polynomial. The received variable-length message polynomials are classified into 8 types, and 8 types can be classified into a case of a multiple of 8 and a case of not a multiple of 8. In the 8-parallel encoder structure, the insertion of a zero symbol is not necessary for a multiples of 8, but if a multiples of 8 are not multiples of 8, a correct calculation in an 8-parallel structure by inserting a zero symbol that can be filled with a multiple of 8 The rearrangement must be made. Possible variable-length Reed-Solomon codes can be classified into eight types as shown in Table 1.

type RS (n, k) Rearrangement process Yes One [8 (p + 2), 8p] No Zero Symbol Required RS (255, 239) 2 [8 (p + 2) -1, 8p-1] 1 Zero-Symbol required RS (254, 238) 3 [8 (p + 2) -2, 8p-2] Requires 2 Zero-Symbol RS (253, 237) 4 [8 (p + 2) -3, 8p-3] Requires 3 Zero-Symbol RS (252, 236) 5 [8 (p + 2) -4, 8p-4] Requires 4 Zero-Symbol RS (251, 235) 6 [8 (p + 2) -5, 8p-5] Requires 5 Zero-Symbol RS 250, 7 [8 (p + 2) -6, 8p-6] Requires 6 Zero-Symbol RS (249,233) 8 [8 (p + 2) -7, 8p-7] Requires 7 Zero-Symbol RS (248,232)

In Table 1, p denotes parallel, and variable length Reed-Solomon codes of types 1 to 8 can be expressed by the following equations (16) to (23).

&Quot; (16) &quot;

&Quot; (17) &quot;

&Quot; (18) &quot;

&Quot; (19) &quot;

&Quot; (20) &quot;

&Quot; (21) &quot;

&Quot; (22) &quot;

&Quot; (23) &quot;

The eight types of variable-length Reed-Solomon codes represented in Table 1 are determined by the code length information signal input as the first message polynomial. Therefore, in the variable length 8-parallel Reed-Solomon code device, the code length information signal plays an important role in the rearrangement process.

4 is a diagram illustrating a process of rearranging eight types of variable length messages according to a code length information signal and encoding according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a structure of a variable-length 8-parallel Reed-Solomon code apparatus according to an embodiment of the present invention.

5, a variable length 8-parallel Reed-Solomon coding apparatus according to an embodiment of the present invention includes an input unit 500, a reordering unit 510, a partial generation polynomial calculation unit 520, an output unit 530, .

The input unit 500 receives the variable-length 8 parallel message symbols every cycle of a cycle determined by the code length information signal. The input unit 500 receives eight inputs (M0, M1, M2, M3, M4, M5, M6, and M7) every clock cycle and inputs the input data for a cycle determined by the code length information signal.

The reordering unit 510 rearranges the input message symbols into variable length Reed-Solomon codes based on the code length information signal. The input message symbols are input to the respective partial generator polynomial calculators 520 via the reordering unit 510 using the code length information signal.

In addition, the partial generation polynomial calculation unit 520 computes each rearranged variable-length Reed-Solomon code with eight partial generation polynomials to expand it into an 8-parallel structure. At this time, the operation result value of the partial generation polynomial is stored in the parity symbol storage unit 521.

The output unit 530 outputs the operation result value stored by the control signal generated by the reordering unit 510 or the input variable length 8 parallel message symbol. The input message symbols are stored in the register unit 533 for outputting the parity symbols and then output to the output of the encoder after passing through the output unit 530. When the last message symbol is input and the calculation is completed, the calculated parity symbol is output through the output unit 530. At this time, the control signal of the multiplexer is controlled by the output of the control signal generator 511, which receives the code length information signal. In the operation of the partial generation polynomial, the addition operations of the terms are stored in the parity symbol storage unit 521 via the XOR circuit. When the calculation process is completed after receiving the last message symbol, the value stored in the register is transferred to the multiplexer 531 of the output unit 530 and outputted as an output. The multiplexer 531 in the output unit 530 determines whether to output the delayed input message symbol or the value stored in the parity symbol register according to the control signal generated by the reordering unit 510. [

The encoded codeword is transmitted to the decoder through the channel. The code length information signal received together with the variable length codeword plays an important role in enabling a correct decoding process to be performed.

6 is a diagram illustrating a structure of a variable-length 8-parallel RS-Solomon decoding apparatus according to an embodiment of the present invention.

6, the variable-length 8-parallel RS-Solomon decoding apparatus includes an 8-parallel syndrome calculation unit 610, a KES unit 620, an 8-parallel error correction unit 630, a FIFO output 640 &lt; / RTI &gt;

The 8-parallel syndrome calculation unit 610 calculates an error pattern of the received variable-length 8-parallel codeword and outputs a syndrome polynomial.

Also, the KES unit 620 outputs the error location polynomial and the error value polynomial based on the output syndrome polynomial.

The 8-parallel error correcting unit 630 detects the error position based on the error location polynomial, calculates an error value corresponding to the error location based on the error value polynomial, and outputs an error of the received variable-length 8 parallel codeword Correct.

The FIFO output unit 640 stores a symbol including an error and outputs the stored symbol according to a control signal.

Since the syndrome calculation unit 610 of the variable-length 8-parallel reed-solomon decoding apparatus processes eight symbols simultaneously in one clock cycle, Equation (8) can be expressed as Equation (24).

&Quot; (24) &quot;

The received codeword is a variable length and is divided into a case of being a multiple of 8 and a case of not being a multiple of 8. As in the variable length 8-parallel Reed-Solomon encoder, insertion of a zero symbol is not necessary when the syndrome calculation block is a multiple of 8, but when a non-multiple of 8 is inserted, a zero symbol that can be filled with a multiple length of 8 is inserted Should be. As shown in Table 1, eight types of variable length RS codes can be expressed as Equations 25 to 32 using a code length information signal received together with a code word.

&Quot; (25) &quot;

&Quot; (26) &quot;

&Quot; (27) &quot;

&Quot; (28) &quot;

&Quot; (29) &quot;

&Quot; (30) &quot;

&Quot; (31) &quot;

(32)

The variable-length 8-parallel syndrome calculation unit based on equations (25) to (32) has a structure as shown in FIG.

7 is a diagram illustrating a structure of an 8-parallel syndrome calculation unit according to an embodiment of the present invention.

Referring to FIG. 7, the 8-parallel syndrome calculation unit according to an embodiment of the present invention may include a reordering unit 710 and a syndrome cell unit 720.

The rearrangement determination unit 710 rearranges the received variable-length 8 parallel code words based on the code length information signal.

In addition, the syndrome cell unit 720 calculates an error pattern for each of the rearranged codewords and outputs a syndrome polynomial. The rearranged codewords are input to the syndrome cell unit 720 and transmitted to the arithmetic unit 723 for calculating the error patterns by eight. The code length information signal is used to rearrange the codewords received by the rearrangement determination unit 710 and controls the codeword to be input to the syndrome calculation unit.

와 오류 값 다항식

을 구하고 친서치 부와 포니알고리즘 수행부로 전달된다. 이때 신드롬 계산부에서 KES 부로 전달된 코드길이 정보신호도 오류 위치 다항식

와 오류 값 다항식

과 같이 전달된다. 가변길이 8-병렬 친서치 부와 포니 알고리즘 수행부는 한번에 8개의 심볼을 검사한다.The control signal of the syndrome calculation unit multiplexer 721 is controlled by the output of the control signal generation unit 711 in the reordering unit 710. The computed syndrome values are passed to the shift register, S0, S1, ... , S15 are continuously output. The output syndrome polynomial passes through the KES block using the pDCME algorithm,

And error value polynomial

And transmitted to the parent search unit and the pony algorithm execution unit. At this time, the code length information signal transmitted from the syndrome calculation unit to the KES unit is also an error location polynomial

And error value polynomial

. The variable length 8-parallel search unit and the pony algorithm performing unit check eight symbols at a time.

8 is a diagram illustrating an 8-parallel error correction unit according to an embodiment of the present invention.

8, the 8-parallel error correcting unit includes a correlator 810, a pony algorithm executing unit 820, a control signal generating unit 830, and a FIFO output unit 840 can do.

The pupil tooth portion 810 detects error positions by eight based on the error location polynomial.

In addition, the pony algorithm performing unit 820 calculates an error value corresponding to the detected error position based on the error value polynomial. The pony algorithm performing unit 820 may calculate an error value corresponding to the error position using the result of the parent search unit 810 and correct the error by eight.

In addition, the control signal generator 830 receives the code length information signal and generates a signal for controlling the reader unit, the pony algorithm executing unit, and the FIFO output unit. The control signal generator 830 receives the code length information signal and generates a signal for controlling the FIFO output unit control signal, the error search cell Ci in the Pony search unit 810 and the Pony algorithm execution unit 820.

In addition, the FIFO output unit 840 stores a symbol including an error, and outputs the stored symbol according to a control signal.

9 is a diagram illustrating an 8-parallel error correcting cell structure of an 8-parallel error correcting unit according to an embodiment of the present invention.

The control signal received from the control signal generator 830 is transmitted to the control block 911 and the ROM 912 in the error correction cell Ci 910. The ROM 912 determines the root to be initially substituted in the error correcting cell Ci. The length of the codeword received in the decoder is variable, and thus the substituted root must be changed according to the codeword length. When decoding the RS (255,239) code, all the roots are substituted in order to correct the error. However, in the case of decoding the shortened RS (n, k) code based on the RS (255, 239) code, the part where the zero-padding is inserted by the correlator 810 and the pony algorithm performing unit 820 is excluded The unnecessary calculation time can be reduced and the processing speed can be improved. The output of the control block 911 in the error correction cell Ci controls the multiplexer of the arithmetic unit 913 using eight roots so that error correction can be performed by the received code word. Since the variable length codeword differs from codeword to codeword, the delay time of the received codeword transmitted through the FIFO output unit 840 must be changed.

10 is a diagram illustrating a structure of a FIFO output unit according to an embodiment of the present invention.

The memory size of the FIFO output used as a buffer during the process of detecting and correcting errors is determined based on the RS (255,239) code. Since the output of the memory depends on the length of the code word, it is determined by the control signal generated by the control signal generator 830.

11 is a diagram illustrating a data flow for an output latency and a reception wait time depending on a received codeword according to an embodiment of the present invention.

In the decoding process, the calculation time varies depending on the length of the received codeword. A decoding device that processes a codeword of fixed length can receive a continuous codeword and correct the error, but a decoding device that processes a codeword of variable length needs a waiting time of a certain time before receiving the next codeword Do.

The reception wait time is required in order to prevent the codewords, which are already received and are in the process of being decrypted, from coming into the codewords to be received, because the decoding method of the decoding apparatus is changed according to the codeword length. The reception wait time can be determined by considering the case where the longest code and the shortest code among the receivable codes are successively received.

에서 가장 짧은 코드워드의

을 뺀다면 이것이 바로 수신 대기시간이 된다. 예를 들어 수신 가능한 코드 중에서 가장 긴 코드가 RS(239,223)코드이고 가장 짧은 코드가 RS(28,12)코드일 경우 가변길이 8-병렬 리드-솔로몬 복호기는 수신 대기시간이 26 클럭이다.The reception latency can be determined by calculating the processing time of the syndrome calculation block. If the longest codeword is received and then the shortest codeword is received, the longest codeword

Of the shortest codeword

If this is subtracted, this is the waiting time. For example, when the longest code among the receivable codes is the RS (239,223) code and the shortest code is the RS (28,12) code, the variable length 8-parallel reed-solomon decoder has a reception waiting time of 26 clocks.

11 (1) is a data flow chart in the case of receiving the longest codeword and the shortest codeword. The second RS (28,12) codeword must be received after the reception wait time set to 26 clocks after the first RS (239,223) codeword is received, so that the decoding processes of the two codewords do not affect each other.

)만큼 더 늘어난다. 그래서 첫 번째 코드워드의 출력 latency는 74 클럭이고 두 번째 코드워드의 latency는 100클럭으로 계산된다. FIG. 11 (2) is a data flow chart in the case where the length of a received codeword gradually increases. If the second RS (88,80) codeword is received after the first RS (28,12) codeword has been received and the waiting time has elapsed, the decoding time of the second codeword is longer. Thus, the latency of the second codeword is computed (

). Thus, the output latency of the first codeword is 74 clocks and the latency of the second codeword is calculated to be 100 clocks.

) 계산시간만큼 줄어든다. 그래서 첫 번째 코드워드의 출력 latency는 100클럭이고 두 번째 코드워드의 latency는 87클럭으로 계산된다. 11 (3) is a data flow chart in the case where the length of the received codeword is gradually smaller. If the second RS (136,120) codeword is received after the first RS (239,223) codeword is received and after the waiting time, the decoding time of the second codeword is shorter. Thus, the latency of the second code word is (

) Is reduced by the calculation time. Thus, the output latency of the first codeword is 100 clocks and the latency of the second codeword is calculated to be 87 clocks.

11 (4) is a data flow chart when the length of the received codeword is the same. When the length of the received codeword is the same, the same operation as that of the decoder for the fixed length is performed. Therefore, the waiting time is not required and the output latency does not change.

The methods according to embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

Claims (1)

An input unit for receiving variable length 8 parallel message symbols every cycle of a cycle determined by the code length information signal;
A rearrangement determination unit for rearranging the input message symbols into variable length Reed Solomon codes based on the code length information signal;
A partial generator polynomial calculator for calculating each of the rearranged variable-length Reed-Solomon codes using eight partial generator polynomials;
A parity symbol storage unit for storing a result of the operation of the partial generation polynomial;
An output unit for outputting the stored operation result value or the input variable length 8 parallel message symbol according to the control signal generated by the reordering unit;
A syndrome cell unit for calculating an error pattern for the rearranged variable-length Reed-Solomon code and outputting a syndrome polynomial; And
Calculating an error value corresponding to the detected error position based on the syndrome polynomial, excluding the zero-fading inserted portion from the calculation process, and performing error correction based on the code length information signal using the multiplexer [0034]
Lt; / RTI &gt;
Wherein the rearrangement determination unit includes a control signal generation unit,
The multiplexer in the output unit receives the code length information signal and outputs a control signal for controlling the multiplexer in the output unit. The multiplexer in the output unit determines whether to output the input message symbol delayed by the control signal generated in the reordering unit, Determines whether to output the value stored in the parity symbol register
Variable length 8 parallel lead-solomon code device.

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