KR101590701B1 - Digital Loop Filter and Digital Phase Lock Loop Using the Same - Google Patents

Abstract

The digital phase locked loop according to the present embodiment includes a digital controlled oscillator in which the frequency of an output signal is controlled by a digital control code, a frequency divider for dividing and outputting an output signal frequency of the digital controlled oscillator, Digital converter (Time to Digital Converter) for detecting the frequency and phase difference between the input signal and the output signal, and a digital loop filter for receiving the error signal and forming a digital control code, The digital loop filter has an integration path having an integration gain and a negative feedback path for negatively feedbacking a signal of an integration path and the negative feedback path has an integration path having an integration gain, Which scales the output signal of gain < RTI ID = 0.0 > caler.

Description

[0001] The present invention relates to a digital loop filter and a digital phase locked loop using the same,

The present invention relates to a digital loop filter and a digital phase locked loop.

Conventionally, a digital PLL (Digital Phase Locked Loop) includes a digitally controlled oscillator (DCO) in which the frequency of a signal output as a digital control code is controlled, and a digital controlled oscillator A time-to-digital converter (TDC) that detects the frequency and phase difference of the reference signal and the frequency-divided output signal and outputs an error signal corresponding thereto, and an error signal And a digital loop filter that forms a digital control code of the digitally controlled oscillator.

Japanese Patent Application Laid-Open No. 2009-027581 Patent Publication No. 2012-0072200 Japanese Laid-Open Patent Publication No. 2011-015167

로 표현될 수 있다(K_P: 프로포셔널 이득, K_I: 인테그럴 이득, K = K_TDCK_DCO/N, K_TDC: TDC 이득, K_DCO: DCO 이득). 이 전달함수의 영점의 주파수는

로 정해지며, 위상 고정루프의 대역폭에 해당하는 주파수 인근에 위치한다. 영점과 극점들의 위치관계를 살펴보면, 영점은 극점들 중 낮은 주파수를 가지는 극점에 비하여도 낮은 주파수를 가지는데, 이와 같은 영점과 극점 사이의 위치관계에 의하여 위상 고정 루프에는 그 대역폭(bandwidth) 인근의 주파수에서 피킹(peaking)이 발생한다. The transfer function of the conventional phase locked loop is

(K _P : Proportional gain, K _I : Integral gain, K = K _TDC K _DCO / N, K _TDC : TDC gain, K _DCO : DCO gain). The frequency of the zero point of this transfer function is

And is located near the frequency corresponding to the bandwidth of the phase locked loop. The zero point has a lower frequency than the pole having the lower frequency among the poles. Due to the positional relationship between the zero point and the pole, the phase locked loop has a bandwidth close to the bandwidth Peaking occurs at the frequency.

으로 표시할 수 있다. 피킹값을 감소시키기 위하여 댐핑비(

)가 1보다 큰 오버 댐핑의 형태를 가지도록 회로를 설계할 수 있으나, 이 경우 피킹 특성은 양호하게 유지할 수 있으나, 지터 특성과 안정화 시간(settling time) 특성이 열화된다. 반대로 댐핑비를 1보다 작은 언더 댐핑의 형태로 회로를 설계하는 경우에는 지터 특성과 안정화 시간 특성은 양호하게 유지할 수 있으나, 피킹값이 크게 상승하고, 해당 주파수 대역의 지터를 증폭시키게 된다. 나아가, 댐핑비를 1로 하여 오버 댐핑과 언더 댐핑 사이 임계점인 크리티컬 댐핑(critical damping)으로 회로를 설계한다 하더라도 최대 피킹값은 1.25이므로 결국 위상 고정 루프의 대역폭 내 잡음(in-band noise)이 증폭되는 결과를 초래한다. When the peaking value of the phase locked loop is displayed

As shown in FIG. To reduce the peaking value, the damping ratio (

Can be designed to have a form of overdamping greater than 1, but in this case the picking characteristics can be kept good, but the jitter characteristics and settling time characteristics are degraded. On the other hand, when the circuit is designed in the form of under damping in which the damping ratio is less than 1, the jitter characteristic and the stabilization time characteristic can be maintained satisfactorily, but the peak value greatly increases and the jitter of the frequency band is amplified. In addition, even if the circuit is designed with critical damping, which is a critical point between overdamping and under-damping, with a damping ratio of 1, the maximum peaking value is 1.25, which means that the in-band noise of the phase- Lt; / RTI >

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital phase locked loop which minimizes a peaking value and does not degrade jitter characteristics and stabilization time characteristics.

The digital phase locked loop according to the present embodiment includes a digital controlled oscillator in which the frequency of an output signal is controlled by a digital control code, a frequency divider for dividing and outputting an output signal frequency of the digital controlled oscillator, Digital converter (Time to Digital Converter) for detecting the frequency and phase difference between the input signal and the output signal, and a digital loop filter for receiving the error signal and forming a digital control code, The digital loop filter has an integration path having an integration gain and a negative feedback path for negatively feedbacking a signal of the integration path and the negative feedback path has an integration path having an integration gain, Which scales the output signal of gain < RTI ID = 0.0 > caler.

The digital loop filter according to the present embodiment is a digital loop filter that forms a control code for controlling a digital controlled oscillator in a digital phase locked loop, and the digital loop filter has an integration path having an integration gain an integration path and a negative feedback path for negatively feedbacking a signal of an integration path and a negative feedback path includes a gain scaler for scaling an output signal of the integration path to a scaling gain value, .

Embodiments of the present invention provide the advantage of being able to effectively prevent peaking occurring near the bandwidth of the phase locked loop and to maintain good jitter and stabilization time characteristics.

According to the embodiments of the present invention, the effect of picking occurring near the band width frequency is minimized and the influence of the in-band noise, which is noise in the phase locked loop bandwidth, is minimized. It is possible to prevent the occurrence of phase difference overshoot due to jitter accumulation and to reduce the fixing time of the phase locked loop.

1 is a block diagram showing an outline of a phase locked loop according to an embodiment of the present invention.
2 is a block diagram illustrating an outline of a phase locked loop according to another embodiment of the present invention.
3 is a photomicrograph of a chip in which a phase locked loop according to the present embodiment is implemented using a 65 nm LP CMOS process.
FIGS. 4A and 4B are diagrams each showing the phase response of the output signal when the clock phase input to the conventional phase locked loop and the phase locked loop implemented according to the present embodiment changes stepwise.
5 is a graph showing that jitter generation is suppressed in the vicinity of the bandwidth of the phase locked loop implemented according to the present embodiment.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas.

It should be understood that the singular " include "or" have "are to be construed as including a stated feature, number, step, operation, component, It is to be understood that the combination is intended to specify that it is present and not to preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

Each step may take place differently from the stated order unless explicitly stated in a specific order in the context. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

The drawings referred to for explaining embodiments of the present disclosure are exaggerated in size, height, thickness, and the like intentionally for convenience of explanation and understanding, and are not enlarged or reduced in proportion. In addition, any of the components shown in the drawings may be intentionally reduced, and other components may be intentionally enlarged.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms such as those defined in commonly used dictionaries should be interpreted to be consistent with the meanings in the context of the relevant art and can not be construed as having ideal or overly formal meaning unless explicitly defined in the present application .

Hereinafter, a digital phase locked loop according to the present embodiment will be described with reference to the accompanying drawings. The present specification does not distinguish types of signal lines, and each line can be interpreted as a single signal or a bus signal composed of one or more analog signals or digital signals.

The digital phase locked loop according to the present embodiment includes a digital controlled oscillator in which the frequency of an output signal is controlled by a digital control code, a frequency divider for dividing and outputting an output signal frequency of the digital controlled oscillator, Digital converter (Time to Digital Converter) for detecting the frequency and phase difference between the input signal and the output signal, and a digital loop filter for receiving the error signal and forming a digital control code, The digital loop filter has an integration path having an integration gain and a negative feedback path for negatively feedbacking a signal of the integration path and the negative feedback path has an integration path having an integration gain, Which scales the output signal of gain < RTI ID = 0.0 > sc aler).

FIG. 1 is a block diagram showing an outline of a digital phase locked loop according to the present embodiment. A digitally controlled oscillator (DCO) 100 outputs a frequency and a phase of an output signal, which are controlled by a digital control code Dctr provided from the digital loop filter 400, And outputs the signal CKout.

The frequency divider 200 receives the output signal CKout output from the digital controlled oscillator (DCO) 200 and outputs a feedback clock signal CKfb divided by a predetermined frequency division ratio. The frequency divider included in the PLL adjusts the phase and frequency of the output signal CKout by adjusting the frequency division ratio.

The TDC 300 detects the frequency and phase difference of the feedback clock signal CKfb and the reference clock signal CKref and outputs an error signal Derr corresponding thereto in operation S200. For example, the error signal Derr includes an up signal for increasing the phase and frequency of the output signal CKout output from the digital controlled oscillator when the frequency and phase of the feedback clock signal are lower than the reference signal, And a down signal for reducing the phase and frequency of the output signal in the reverse case.

The digital loop filter 400 receives the error signal Derr to form a digital control code for controlling the digital controlled oscillator (DCO) 100 and provides the digital control code to the digital controlled oscillator. The conventional digital loop filter filters a proportional gain signal that controls the frequency of a signal output from the digital controlled oscillator (DCO) 100 by filtering the error signal Derr provided by the time-digital signal, And an integration gain signal for controlling the integration gain. When a conventional digital loop filter is used, the shape of the phase-locked loop transfer function becomes a form of having a first order in a molecule and a quadratic form in a denominator to form a zero. Therefore, the influence of the peaking due to the zero point near the frequency corresponding to the bandwidth of the phase locked loop can not be avoided as described above.

The digital loop filter 400 used in the digital phase locked loop according to the present embodiment includes an integration path 410 and a negative feedback path 420. In one embodiment, the integration path 410 includes an integrator 412 that receives the error signal Derr and multiplies the integration gain K _I to perform an integration operation, and the integrator 412 includes an integration gain K _I ) to perform phase compensation of the reference signal and the feedback clock signal CKfb.

The negative feedback path 420 receives a digital control code (Dctr) signal and scales it by multiplying the scaling gain K _D. In one example, the negative feedback path 420 includes a gain scaler 422 that receives a digital control code Dctr and scales it with a scaling gain K _D. The negative feedback path 420 subtracts the scaled signal from the error signal Derr using the adder 500 and is fed back to the input of the digital loop filter.

The present embodiment can be implemented as a discrete time digital circuit, and the z-domain transfer function of the digital loop filter 400 can be expressed by Equation (1) below.

The z-region open loop transfer function of the phase locked loop is obtained using Equation (2) below.

으로 근사될 수 있다. 이러한 근사를 이용하여 위상 고정 루프(PLL)의 개방 루프(open loop) s 영역 전달함수는 아래의 수학식 3과 같다.The Nyquist frequency of the digital loop filter is 1/2 of the digital loop filter sampling frequency. If the Nyquist frequency f _N is larger than the bandwidth of the _PLL (B _PLL ) , f _N &_gt; 10 x B _PLL )

. ≪ / RTI > Using this approximation, the open loop s region transfer function of the phase locked loop (PLL) is given by Equation 3 below.

The closed loop s-domain transfer function of the phase locked loop is obtained by using the open loop s-domain transfer function expressed by Equation (3).

As can be seen from Equation (4), unlike the transfer function of the conventional digital phase locked loop, the transfer function of the digital phase locked loop according to the present embodiment has no zero point because there is no first order s of the molecules, And a low pass filter (LPF). Therefore, unlike the phase locked loop of the related art, it can be confirmed mathematically that peaking near the node frequency disappears.

The digital loop filter 400 according to the present embodiment having the integration path and the negative feedback path does not form a zero point that has occurred near the bandwidth frequency generated in the conventional phase locked loop and therefore does not form peaking near the bandwidth frequency . Therefore, the peaking can be prevented from occurring while the jitter characteristic and the stabilization time characteristic are maintained satisfactorily.

The digital loop filter 400 applies the digital control code Dctr thus formed to the digitally controlled oscillator 100. The digitally controlled oscillator to which the digital control code Dctr is applied forms and outputs a signal having a desired frequency.

Another embodiment of the present invention will be described with reference to Fig. However, for the sake of brevity and clarity, the description of the contents overlapping with the embodiment described above can be omitted. The digital loop filter 400 according to the present embodiment further includes a high pass filter (HPF) 424 in the negative feedback path 420. The digital control code Dctr is a superposition of codes for controlling the frequency and phase of the digital controlled oscillator 100. [ For example, if the frequency set for output by the digital controlled oscillator (DCO) 100 is 2 GHz, the digital loop filter 400 generates a code for controlling the digital controlled oscillator (DCO) 100 to continuously output a signal having a frequency of 2 GHz And the reference signal in a relatively short time so as to compensate for the phase difference.

The code that controls the digital controlled oscillator (DCO) 100 to maintain a constant frequency does not change after the phase locked loop is fixed, or changes to a low frequency. However, the code that compensates for the phase difference changes to a higher frequency than the code that controls to maintain the frequency.

In the case where only the gain scaler is included in the negative feedback path, a code for controlling the output of the signal having the frequency of 2 GHz is scaled by the gain scaler and is continuously fed back to the loop filter. Therefore, the reference signal (CKref) A continuous phase difference can be formed between the oscillator (DCO, 100) output signal (CKout).

Therefore, if a high pass filter (HPF) 424 is provided on the negative feedback path 420 and high pass filtering is performed on the digital control code Dctr provided on the negative feedback path, the high pass filter can be a digital controlled oscillator ) Passes through a code that changes in a short time so as to compensate the phase difference from the reference signal, and provides the gain scaler 420 with the code. The gain scaler 422 scales the code provided by the high-pass filter with a scaling gain, subtracts it from the error signal using the adder 500, and feeds back the result to the digital loop filter.

According to the present embodiment including the high-pass filter, the phase difference caused by the passage of the code for controlling the digital controlled oscillator (DCO) 100 to output the signal having the predetermined frequency does not occur, Can output the output signal CKout synchronized with the reference signal CKref.

The operation of this embodiment will be described mathematically as follows. For example, if the high-pass filter 424 is a first-order high-pass filter, the z-domain transfer function of the loop filter including the high-pass filter 424 can be expressed by Equation (5) below.

In the phase locked loop including the phase locked loop of Equation (5), the s region open loop transfer function of the phase locked loop is obtained using the same approximation as in the previous embodiment, as shown in Equation (6) below.

The s-domain closed-loop transfer function H (s) of the phase-locked loop is obtained by using the open-loop transfer function G (s) of Equation (6).

As can be seen from the transfer function expressed by Equation (7), it can be seen that the zero point is formed because the first order term of s is formed in the molecule. However, if the gain κ of the high-pass filter is sufficiently smaller than the product of α and β, Equation (6) can be approximated as Equation (8) below.

That is, if the gain κ of the high-pass filter 424 is sufficiently small compared with the product of α and β, the first order term of the transfer function is removed and approximated by the following equation (8). Therefore, a substantially zero point is not formed and no peaking occurs near the band width frequency.

As described above, according to embodiments of the present invention, peaking occurring near the bandwidth of the phase locked loop can be effectively removed. Therefore, it is possible to prevent amplification of noise in the bandwidth, which is noise in the phase locked loop bandwidth, to prevent occurrence of phase difference overshoot due to jitter accumulation, and to reduce the fixing time of the phase locked loop.

Example  And Test Example

The phase locked loop according to this embodiment is implemented as shown in FIG. 3 using a 65 nm LP CMOS process. Table 1 below shows the characteristics of the chip that implements this.

fair 65nm 1p8m CMOS LP Supply voltage 1.2V Input signal frequency 139 to 148.44 MHz Output signal frequency 8.9 to 9.5 GHz Bandwidth 0.3 to 1.5 MHz accumulate Jitter 1.2 ps _rms (0.1 to 100 MHz) Phase noise -92.8dBc / Hz at 1MHz offset -114dBc / Hz at 10MHz offset Clock Jitter
(÷ 8 Clock ) 3.477 ps _rms at 1.15 GHz 24 ps _pp Stabilization time 1.58 μs at 0.7 MHz BW Power consumption 63.9 mW

FIGS. 4A and 4B are diagrams each showing the phase response of the output signal when the clock phase input to the conventional phase locked loop and the phase locked loop implemented according to the present embodiment changes stepwise. As shown in FIG. 4A, it can be seen that the conventional phase locked loop generates overshoot due to jitter accumulation. However, as shown in FIG. 4B, the phase locked loop according to the present embodiment is phase locked And thus it can be confirmed that the phase fixing time is 2.68 times faster than that of the conventional phase locked loop. Also, as can be seen from FIG. 5, it can be seen that jitter generation is suppressed in the vicinity of the bandwidth of the phase locked loop.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It will be appreciated that other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the appended claims.

100: digital controlled oscillator 200: frequency divider
300: time-to-digital converter 400: digital loop filter
410: Integration path 412: Integrator
420: Negative feedback path 422: Gain scaler
424: high pass filter 500: adder

Claims (19)

A digital controlled oscillator in which the frequency of the output signal is controlled by a digital control code;
A frequency divider for dividing and outputting an output signal frequency of the digitally controlled oscillator;
A time to digital converter for detecting a frequency and a phase difference between the reference signal and the frequency divider output signal and outputting an error signal corresponding thereto; And
And a digital loop filter for receiving the error signal and forming the digital control code,
Wherein the digital loop filter has an integration path for integrating the error signal and a negative feedback path for negatively feedbacking an output signal of the digital loop filter, And a gain scaler for scaling the output signal of the digital loop filter to a scaling gain value,
Wherein the negative feedback path further comprises a high pass filter for receiving a signal of the integration path and outputting a high pass signal to the gain scaler for compensating for a phase difference from the reference signal. The method according to claim 1,
The digital phase locked loop further comprising an adder for subtracting the signal output by the gain scaler from the error signal. delete delete delete delete The method according to claim 1,
Wherein the integration path includes an integrator that receives the error signal and integrates the integration signal with a predetermined integration gain. delete delete The method according to claim 1,
The z-domain transfer function of the loop filter is

Digital phase locked loop. The method according to claim 1,
The open-loop s-domain transfer function of the phase-locked loop

Digital phase locked loop. The method according to claim 1,
The closed-loop s-domain transfer function of the phase locked loop

Digital phase locked loop. The method according to claim 1,
The closed-loop s-domain transfer function of the phase locked loop

Digital phase locked loop. A digital loop filter (Digital Loop Filter) for forming a control code for controlling a digitally controlled oscillator in a digital phase locked loop,
An integration path having an integration gain; And
And a negative feedback path for negatively feeding a signal of the integration path,
The negative feedback path comprising a gain scaler for scaling the output signal of the integration path to a scaling gain value,
Wherein the negative feedback path further comprises a high pass filter for receiving a signal of the integration path and outputting a high pass signal for compensating for a phase difference from the reference signal to the gain scaler. 15. The method of claim 14,
The z-domain transfer function of the digital loop filter

In digital loop filter. delete delete 15. The method of claim 14,
The z-domain transfer function of the loop filter is

In digital loop filter. 15. The method of claim 14,
The s-domain transfer function of the digital loop filter is

Digital loop filter.

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