KR101585962B1 - Structure of bonding pad and manufacturing method thereof for semiconductor device - Google Patents

Structure of bonding pad and manufacturing method thereof for semiconductor device Download PDF

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KR101585962B1
KR101585962B1 KR1020090037756A KR20090037756A KR101585962B1 KR 101585962 B1 KR101585962 B1 KR 101585962B1 KR 1020090037756 A KR1020090037756 A KR 1020090037756A KR 20090037756 A KR20090037756 A KR 20090037756A KR 101585962 B1 KR101585962 B1 KR 101585962B1
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bonding pad
semiconductor device
bonding
present
concentric circles
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KR20100118845A (en
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김태호
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주식회사 동부하이텍
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  • Wire Bonding (AREA)

Abstract

본 발명은 반도체 소자의 본딩 패드 구조 및 패드 형성 방법에 관한 것으로, 더욱 상세하게는 와이어 본딩 공정 또는 프로브 테스트 공정에서 크랙을 방지할 수 있는 반도체 소자의 본딩 패드 구조 및 패드 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a bonding pad structure and a pad forming method of a semiconductor device, and more particularly, to a bonding pad structure and a pad forming method of a semiconductor device capable of preventing a crack in a wire bonding process or a probe test process.

본 발명의 반도체 소자의 본딩 패드 구조는 다수의 동심원 형상으로 이루어지고, 상기 동심원의 중심을 관통하는 다수의 방사형 홈을 갖는 본딩 패드; 그리고 상기 본딩 패드의 가장자리 부분을 둘러싸면서 패터닝되는 보호막;을 포함하여 이루어진 것을 특징으로 한다.The bonding pad structure of the semiconductor device of the present invention includes a bonding pad having a plurality of concentric circles and a plurality of radial grooves passing through the center of the concentric circles; And a protection layer surrounding the edge of the bonding pad and patterned.

본 발명에 따른 반도체 소자의 본딩 패드 구조 및 패드 형성 방법에 의하면 본딩 패드의 모양을 변경함으로써 와이어 본딩 공정 또는 프로브 테스트 공정에서 크랙을 방지할 수 있는 효과가 있다. According to the bonding pad structure and pad forming method of a semiconductor device according to the present invention, cracks can be prevented in a wire bonding process or a probe test process by changing the shape of the bonding pad.

본딩 패드, 크랙(crack), 프로브 테스트, 와이어 본딩 Bonding pad, crack, probe test, wire bonding

Description

반도체 소자의 본딩 패드 구조 및 패드 형성 방법{Structure of bonding pad and manufacturing method thereof for semiconductor device}BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a bonding pad structure,

본 발명은 반도체 소자의 본딩 패드 구조 및 패드 형성 방법에 관한 것으로, 더욱 상세하게는 와이어 본딩 공정 또는 프로브 테스트 공정에서 크랙을 방지할 수 있는 반도체 소자의 본딩 패드 구조 및 패드 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a bonding pad structure and a pad forming method of a semiconductor device, and more particularly, to a bonding pad structure and a pad forming method of a semiconductor device capable of preventing a crack in a wire bonding process or a probe test process.

일반적으로 반도체 제품은 웨이퍼 가공 공정을 마친 후에, 프로브 테스트(probe test)를 수행한 후 소정의 패키지(package) 형태로 조립되어 완성된다. 여기서, 패키지의 이너 리드(inner lead)와 반도체 소자의 본딩 패드(bonding pad)를 전기적으로 연결시키기 위하여, 상기 반도체 소자의 본딩 패드로부터 패키지 리드 프레임(lead frame)의 이너 리드로 연장된 와이어 본드(wire bond)가 형성된다. Generally, a semiconductor product is subjected to a probe test after completion of a wafer processing process, and then assembled in a predetermined package. Here, in order to electrically connect the inner lead of the package and the bonding pad of the semiconductor device, a wire bond (not shown) extending from the bonding pad of the semiconductor device to the inner lead of the package lead frame wire bonds are formed.

도 1은 일반적인 반도체 소자의 본딩 패드의 모양을 보여주는 평면도이고, 도 2는 도 1의 A-A'선을 따라서 잘라서 본 단면도이다.FIG. 1 is a plan view showing the shape of a bonding pad of a general semiconductor device, and FIG. 2 is a sectional view cut along the line A-A 'in FIG.

첨부된 도 1 내지 도 2를 함께 참조하면, 반도체 기판상에 하부 금속층(10) 및 층간절연막(20)이 순차적으로 형성되어 있다. 상기 하부 금속층(10)은 상기 층간절연막(20)을 관통하는 다수의 비아 콘택 플러그(30)에 의하여 상기 층간절연 막(20)상의 상부 금속층(40)과 전기적으로 연결된다. Referring to FIGS. 1 and 2, a lower metal layer 10 and an interlayer insulating film 20 are sequentially formed on a semiconductor substrate. The lower metal layer 10 is electrically connected to the upper metal layer 40 on the interlayer insulating layer 20 by a plurality of via contact plugs 30 penetrating the interlayer insulating layer 20.

상기 비아 콘택 플러그(30)를 형성하기 위해서는, 상기 층간절연막(20)을 관통하는 다수의 비아 콘택홀을 패터닝한 다음, 도전성 물질을 증착하여 상기 비아 콘택홀을 매립하고, 평탄화 공정, 예컨대 화학적 기계적 연마(Chemical Mechanical Polishing) 또는 에치백(etch back) 공정을 수행한다.In order to form the via contact plug 30, a plurality of via contact holes passing through the interlayer insulating film 20 are patterned, a conductive material is deposited to deposit the via contact holes, and a planarization process such as a chemical mechanical A polishing process (Chemical Mechanical Polishing) or an etch back process is performed.

상기 상부 금속층(40) 중 일부는 패시베이션층(passivation layer) 또는 보호막(50)에 의하여 상면 일부가 노출되어 본딩 패드를 구성한다.A part of the upper metal layer 40 is partially exposed by a passivation layer or a passivation layer 50 to form a bonding pad.

그러나 종래의 본딩 패드는 와이어 본딩 공정 및 프로브 테스트(probe test) 공정에서, 와이어를 상기 본딩 패드에 연결시킬 때 가해지는 기계적인 충격(impact)과 압력에 의해 발생하는 스트레스에 의해서, 상기 상부 금속층(40) 내에 크랙(cracks)을 발생시키는 문제점이 있다. However, in the conventional bonding pads, in the wire bonding process and the probe test process, due to the mechanical shock and the stress caused when the wires are connected to the bonding pads, Cracks are generated in the upper and lower substrates 40 and 40, respectively.

특히 종래의 본딩 패드는 상부 금속층을 통판 형태로 제작되어, 첨부된 도 3에 도시한 바와 같이 프로브 테스트 또는 리드 연결시 물리적인 압력에 의해 크랙이 유발될 경우 본딩 패드 전체에 손상이 발생되는 문제가 있다.Particularly, in the conventional bonding pad, the upper metal layer is formed in the form of a through-hole. As shown in FIG. 3, when a crack is generated due to physical pressure during probe test or lead connection, damage to the entire bonding pad occurs have.

따라서 본 발명은 상술한 제반 문제점을 해결하고자 안출된 것으로, 와이어 본딩 공정 또는 프로브 테스트 공정에서 크랙을 방지할 수 있는 반도체 소자의 본딩 패드 구조 및 패드 형성 방법을 제공함에 그 목적이 있다.Accordingly, it is an object of the present invention to provide a bonding pad structure and a pad forming method of a semiconductor device that can prevent cracks during a wire bonding process or a probe test process.

상술한 바와 같은 목적을 구현하기 위한 본 발명의 반도체 소자의 본딩 패드 구조는 다수의 동심원 형상으로 이루어지고, 상기 동심원의 중심을 관통하는 다수의 방사형 홈을 갖는 본딩 패드; 그리고 상기 본딩 패드의 가장자리 부분을 둘러싸면서 패터닝되는 보호막;을 포함하여 이루어진 것을 특징으로 한다.According to another aspect of the present invention, there is provided a bonding pad structure for a semiconductor device, comprising: a bonding pad having a plurality of concentric circles and a plurality of radial grooves passing through the center of the concentric circles; And a protection layer surrounding the edge of the bonding pad and patterned.

또한, 상기 본딩 패드에 형성되는 방사형 홈의 폭은 0.5 ~ 1.0㎛의 크기로 형성하는 것을 특징으로 한다.The width of the radial grooves formed in the bonding pads is 0.5 to 1.0 탆.

또한, 상기 동심원 형상은 도넛 모양으로 이루어지고, 상기 동심원의 중심을 서로 수직으로 관통하는 두 개의 홈을 갖는 것을 특징으로 한다.The concentric circles are formed in a donut shape and have two grooves passing through the centers of the concentric circles perpendicularly to each other.

본 발명의 반도체 소자의 본딩 패드 형성 방법은 하부에 반도체 소자가 형성된 반도체 기판의 절연층의 상부에 금속층을 증착하는 제1 단계; 사진·식각 공정을 진행하여 다수의 동심원 형상으로 이루어지고 상기 동심원의 중심을 관통하는 다수의 방사형 홈을 갖는 본딩 패드를 형성하는 제2 단계; 실리콘산화막 및 실리콘질화막을 순차로 증착하여 패시베이션막을 형성하는 제3 단계; 그리고 사진·식각 공정을 진행하여 본딩 패드의 상부에 존재하는 패시베이션막을 식각하는 제4 단계;를 포함하는 것을 특징으로 한다.A method of forming a bonding pad of a semiconductor device according to the present invention includes: a first step of depositing a metal layer on an insulating layer of a semiconductor substrate on which a semiconductor device is formed; A second step of forming a bonding pad having a plurality of concentric circular grooves and a plurality of radial grooves passing through the center of the concentric circle through a photo etching process; A third step of sequentially depositing a silicon oxide film and a silicon nitride film to form a passivation film; And a fourth step of etching the passivation film existing on the bonding pad by performing the photo etching process.

본 발명에 따른 반도체 소자의 본딩 패드 구조 및 패드 형성 방법에 의하면 본딩 패드의 모양을 변경함으로써 와이어 본딩 공정 또는 프로브 테스트 공정에서 크랙을 방지할 수 있는 효과가 있다. According to the bonding pad structure and pad forming method of a semiconductor device according to the present invention, cracks can be prevented in a wire bonding process or a probe test process by changing the shape of the bonding pad.

이는 패드 크랙 발생시 크랙의 심각성을 줄일 수 있는 방안으로 단순한 금속 패턴의 변경으로 큰 효과를 얻을 수 있는 장점이 있다. This is a way to reduce the severity of cracks in the event of pad cracks, which is advantageous in that a large effect can be obtained by simply changing the metal pattern.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대한 구성 및 작용을 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 쉽게 실시할 수 있도록 상세히 설명하면 다음과 같다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout.

도 4는 본 발명의 일실시예에 따른 반도체 소자의 본딩 패드의 모양을 보여주는 평면도이고, 도 5는 도 4의 A-A'선을 따라서 잘라서 본 단면도이다.FIG. 4 is a plan view showing a bonding pad of a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line A-A 'in FIG.

본 발명의 일실시예에 따른 반도체 소자의 본딩 패드 구조는 본딩 패드(400) 및 보호막(50)을 포함하여 이루어져 있다.The bonding pad structure of the semiconductor device according to an embodiment of the present invention includes a bonding pad 400 and a protective layer 50.

상기 본딩 패드(400)는 다수의 동심원 형상으로 이루어지고, 상기 동심원의 중심을 관통하는 다수의 방사형 홈을 갖는 구조로 이루어진 금속층이다. The bonding pad 400 is a metal layer having a plurality of concentric circles and a plurality of radial grooves passing through the center of the concentric circles.

이때 상기 본딩 패드(400)에 형성되는 방사형 홈의 폭은 0.5 ~ 1.0㎛의 크기로 형성하는 것이 바람직하다. At this time, the width of the radial groove formed in the bonding pad 400 is preferably 0.5 to 1.0 탆.

상기 보호막(50)은 상기 본딩 패드의 가장자리 부분을 둘러싸면서 패터닝되는 절연층이다. The protective layer 50 is an insulating layer that is patterned while surrounding the edge portion of the bonding pad.

본 발명의 다른 일실시예에 따른 반도체 소자의 본딩 패드 구조에 의하면, 상기 동심원 형상은 도넛 모양으로 이루어지고, 상기 동심원의 중심을 서로 수직으로 관통하는 두 개의 홈을 갖는 것이 바람직하다. According to another embodiment of the present invention, it is preferable that the concentric circles have a donut shape, and the concentric circles have two grooves perpendicularly passing through the centers of the concentric circles.

종래의 패드 형성 방법은 최상부 금속층을 통판의 형태로 제작하여 프로브 테스트 또는 리드 연결시 물리적인 압력에 의해 크랙이 유발될 경우 최상부 금속층전체에 손상이 발생될 수 있었다. In the conventional method of forming a pad, when the uppermost metal layer is formed in the form of a through plate and cracks are induced by physical pressure during probe test or lead connection, damage may occur to the entire uppermost metal layer.

본 발명의 일실시예에 따른 반도체 소자의 본딩 패드 구조에 의하면, 프로브 테스트 또는 리드 연결시 물리적인 압력에 의해 크랙이 유발될 경우에도 금속층 전체에 영향을 주지 않도록 최상부 금속층의 형태를 변경한 것이다. According to the bonding pad structure of a semiconductor device according to an embodiment of the present invention, the shape of the uppermost metal layer is changed so as not to affect the entire metal layer even when a crack is caused by physical pressure during probe test or lead connection.

즉 본 발명의 일실시예에 따른 반도체 소자의 본딩 패드 구조는 크랙이 발생되어도 최상부 금속층이 서로 떨어져 있어 크랙이 최상부 금속층 전체로 번지지 않고 최소한으로 줄일 수 있어 크랙이 더 이상 커지지 않게 된다.That is, in the bonding pad structure of the semiconductor device according to the embodiment of the present invention, even if cracks are generated, the uppermost metal layers are separated from each other, so that the cracks do not spread over the entire uppermost metal layer and can be minimized.

또한 최상부 금속층의 형태를 방사형으로 하여 스트레스를 완화할 수 있고, 금속층 사이의 간격을 1um 이하로 하여 프로브 테스트 및 패키지 시 컨택 저항의 헌팅(Hunting)을 방지하는 효과도 있다.In addition, the shape of the uppermost metal layer may be radial to alleviate the stress, and the distance between the metal layers may be set to 1um or less to prevent probe resistance and hunting of contact resistance when packaged.

본 발명의 일실시예에 따른 반도체 소자의 본딩 패드 형성 방법은 제1 단계 내지 제4 단계를 포함하여 이루어져 있다.A method of forming a bonding pad of a semiconductor device according to an embodiment of the present invention includes steps 1 to 4.

상기 제1 단계는 하부에 반도체 소자가 형성된 반도체 기판의 절연층의 상부에 금속층을 증착하는 단계이다. 상기 금속층으로 6000 ~ 7000Å의 알루미늄 합금막 및 100 ~ 250Å의 Ti/TiN막으로 이루어진 복합막을 형성하는 것이 바람직하다. 즉 상기 알루미늄 합금막으로 Al-Cu 합금막을 형성하는 것이 바람직하다. The first step is a step of depositing a metal layer on an insulating layer of a semiconductor substrate on which a semiconductor device is formed. It is preferable that the metal layer is formed of a composite film composed of an aluminum alloy film of 6000 to 7000 angstroms and a Ti / TiN film of 100 to 250 angstroms. That is, it is preferable to form an Al-Cu alloy film with the aluminum alloy film.

상기 제2 단계는 사진·식각 공정을 진행하여 다수의 동심원 형상으로 이루어지고 상기 동심원의 중심을 관통하는 다수의 방사형 홈을 갖는 본딩 패드를 형성하는 단계이다. 즉 상술한 본 발명의 반도체 소자의 본딩 패드 구조와 같은 형상으로 상기 금속층을 패터닝하는 것이다. The second step is a step of forming a bonding pad having a plurality of concentric circles and a plurality of radial grooves passing through the center of the concentric circles through a photo etching process. That is, the metal layer is patterned in the same shape as the bonding pad structure of the semiconductor device of the present invention described above.

상기 제3 단계는 실리콘산화막 및 실리콘질화막을 순차로 증착하여 패시베이션막을 형성하는 단계이다. 여기서 상기 패시베이션층으로 실리콘질화막 및 TEOS막으로 이루어진 복합막을 사용하는 것이 바람직하다. 예를 들어 3000Å두께의 실리콘질화막을 증착하고나서 100Å두께의 TEOS막을 증착하는 것이 바람직하다.The third step is a step of forming a passivation film by sequentially depositing a silicon oxide film and a silicon nitride film. Here, it is preferable to use a composite film composed of a silicon nitride film and a TEOS film as the passivation layer. For example, it is preferable to deposit a silicon nitride film having a thickness of 3000 A and then a TEOS film having a thickness of 100 ANGSTROM.

마지막으로 상기 제4 단계는 사진·식각 공정을 진행하여 본딩 패드의 상부에 존재하는 패시베이션막을 식각함으로써 본 발명의 일실시예에 따른 반도체 소자의 본딩 패드 형성 방법을 완성한다. Finally, in the fourth step, a photolithography process is performed to etch the passivation film existing on the bonding pad, thereby completing a method of forming a bonding pad of a semiconductor device according to an embodiment of the present invention.

본 발명은 전술한 실시 예에 한정되지 아니하고 본 발명의 기술적 요지를 벗어나지 아니하는 범위 내에서 다양하게 수정·변형되어 실시될 수 있음은 본 발명 이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어서 자명한 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. It is.

도 1은 일반적인 반도체 소자의 본딩 패드의 모양을 보여주는 평면도,1 is a plan view showing the shape of a bonding pad of a general semiconductor device,

도 2는 도 1의 A-A'선을 따라서 잘라서 본 단면도,FIG. 2 is a sectional view taken along the line A-A 'in FIG. 1,

도 3은 프로브 테스트에서 발생한 크랙을 보여주는 평면도, FIG. 3 is a plan view showing a crack generated in the probe test,

도 4는 본 발명의 일실시예에 따른 반도체 소자의 본딩 패드의 모양을 보여주는 평면도,4 is a plan view showing the shape of a bonding pad of a semiconductor device according to an embodiment of the present invention,

도 5는 도 4의 A-A'선을 따라서 잘라서 본 단면도.5 is a cross-sectional view taken along the line A-A 'in FIG.

*도면의 주요부분에 대한 부호의 설명*Description of the Related Art [0002]

10 : 하부 금속층 20 : 층간절연막10: lower metal layer 20: interlayer insulating film

30 : 비아 콘택 플러그 40 : 상부 금속층30: via contact plug 40: upper metal layer

50 : 보호막 60 : 프로브 팁50: Protective film 60: Probe tip

400 : 본딩 패드400: bonding pad

Claims (4)

2개 이상의 동심원 형상의 서로 이격하는 금속층들로 이루어지고, 상기 동심원의 중심을 관통하는 2개 이상의 방사형 홈을 갖는 본딩 패드; 및A bonding pad formed of two or more concentric metal layers spaced apart from each other and having two or more radial grooves passing through the center of the concentric circle; And 상기 본딩 패드의 가장 자리 부분을 둘러싸면서 패터닝되는 보호막을 포함하며,And a protection layer surrounding and surrounding the edge portion of the bonding pad, 상기 금속층들 사이의 간격은 1㎛이하인 것을 특징으로 하는 반도체 소자의 본딩 패드 구조.And the interval between the metal layers is 1 占 퐉 or less. 제1항에 있어서, 상기 본딩 패드에 형성되는 방사형 홈의 폭은 0.5㎛ ~ 1.0㎛의 크기로 형성하는 것을 특징으로 하는 반도체 소자의 본딩 패드 구조.The bonding pad structure of a semiconductor device according to claim 1, wherein a width of the radial groove formed in the bonding pad is 0.5 mu m to 1.0 mu m. 제1항에 있어서, 상기 동심원 형상은 도넛 모양으로 이루어지고, 상기 동심원의 중심을 서로 수직으로 관통하는 두 개의 홈을 갖는 것을 특징으로 하는 반도체 소자의 본딩 패드 구조.The bonding pad structure of claim 1, wherein the concentric circles are formed in a donut shape and have two grooves passing through the centers of the concentric circles perpendicularly. 제1항에 있어서,The method according to claim 1, 상기 금속층들은 6000Å ~ 7000Å의 알루미늄 합금막 및 100Å ~ 250Å의 Ti/TiN막으로 이루어진 복합막으로 형성되는 것을 특징으로 하는 반도체 소자의 본딩 패드 구조.Wherein the metal layers are formed of a composite film of an aluminum alloy film having a thickness of 6000 Å to 7000 Å and a Ti / TiN film having a thickness of 100 Å to 250 Å.
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