KR101585256B1 - RF signal processing circuit - Google Patents

Abstract

The present invention provides an RF signal processing apparatus capable of preventing an operation characteristic from being degraded due to a clock signal generated in a digital demodulator. The present invention provides a radio communication system comprising: a signal selector for transmitting a signal of a desired band among RF signals inputted through an antenna (ANT); A demodulator for demodulating a signal provided from the signal selection unit using a clock signal generated internally; And a trap filter unit for preventing a clock signal generated in the demodulator from propagating to the signal selection unit.

RF signal, SAW filter, frequency, oscillator, trap filter

Description

[0001] RF SIGNAL PROCESSING CIRCUIT [0002]

The present invention relates to an RF signal processing circuit, and more particularly, to an RF signal processing circuit provided with a trap filter.

With the development of wireless communication technology, it is possible to transmit and receive voice signals and video signals remotely. When a voice signal and a video signal are transmitted, a signal having a communication frequency of several hundred Mhz to several Ghz is used as an RF signal. The transmitting equipment combines the voice signal and the video signal with the RF signal, and the receiving equipment separates the RF signal, the voice signal and the video signal. At this time, coupling is called modulation and demodulation is called separation.

Recently, an RF signal processing circuit for demodulating a signal using a digital demodulator, rather than an analog demodulator, has been developed. In addition, a hybrid RF signal processing circuit having both of these demodulators has been developed. When an analog demodulator and a digital demodulator are provided together in one RF signal processing circuit, the RF signal can be processed in various cases. However, in this case, the clock signal used in the digital demodulator adversely affects other blocks.

The present invention provides an RF signal processing apparatus capable of preventing an operation characteristic from being degraded due to a clock signal generated in a digital demodulator.

The present invention provides a radio communication system comprising: a signal selector for transmitting a signal of a desired band among RF signals inputted through an antenna (ANT); A demodulator for demodulating a signal provided from the signal selection unit using a clock signal generated internally; And a trap filter unit for preventing a clock signal generated in the demodulator from propagating to the signal selection unit.

Further, the demodulator is a digital demodulator.

Further, the RF signal processing circuit of the present invention has a first wiring and a second wiring for transferring the first and second IF signals from the signal selection unit to the demodulator, and the trap filter unit is provided on the first wiring A first inductor and a first capacitor arranged; A second inductor and a second capacitor disposed on the second wiring; A third capacitor and a fourth capacitor disposed between the first wiring and the second wiring, and a resistor disposed between the first wiring and the second wiring, and the third capacitor includes a first inductor and a second inductor, One end of the first inductor and one end of the second inductor are connected to each other, and the fourth capacitor connects the other end of the first inductor and the second inductor.

The trap filter unit includes a fifth capacitor connected in parallel to the first inductor and a sixth capacitor connected in parallel with the second inductor.

In addition, the present invention provides a radio communication system comprising: a signal selector for transmitting a signal of a desired band among RF signals inputted through an antenna ANT; A digital SAW filter for filtering and transmitting a signal transmitted from the signal selector; A demodulator for demodulating a signal provided from the digital SAW filter using a clock signal generated internally; And a trap filter unit disposed between the digital SAW filter and the demodulator to prevent a clock signal generated in the demodulator from propagating to the signal selector.

In addition, the RF signal processing circuit of the present invention includes an IF amplifier for amplifying a signal output from the digital SAW filter and transmitting the amplified signal to the demodulator.

In addition, the RF signal processing circuit of the present invention includes a filter unit, an RF amplifier, and a tuning circuit arranged in series to transmit a signal provided from the antenna to the signal selector.

In addition, the demodulator includes a digital demodulator.

The RF signal processing circuit of the present invention further includes a first wiring and a second wiring for transferring the first and second IF signals from the signal selection unit to the digital SAW filter, A first inductor and a first capacitor disposed on a first wiring line; A second inductor and a second capacitor disposed on the second wiring; A third capacitor and a fourth capacitor disposed between the first wiring and the second wiring, and a resistor disposed between the first wiring and the second wiring, and the third capacitor includes a first inductor and a second inductor, One end of the first inductor and one end of the second inductor are connected to each other, and the fourth capacitor connects the other end of the first inductor and the second inductor.

In addition, the RF signal processing circuit of the present invention includes a fifth capacitor connected in parallel with the first inductor and a sixth capacitor connected in parallel with the second inductor.

According to the present invention, it is possible to prevent the RF signal processing circuit from degrading the operation characteristics due to the clock signal. Particularly, when the RF signal processing circuit includes the digital demodulator, it is possible to reduce adverse effects of the peripheral blocks due to the internally generated clock of the digital demodulator. Therefore, the RF signal processing circuit according to the present invention can process a more reliable RF signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

1 is a block diagram showing an RF signal processing circuit for explaining the present invention.

1, the RF signal processing circuit includes a filter unit 10, an RF amplifier 20, a tuning circuit 30, a signal selecting unit 40, a digital SAW filter 51, a video signal SAW filter 52, an audio signal SAW filter 53, an IF amplifier 60, an analog demodulator 80, and a digital demodulator 70.

The filter unit 10 is a block for filtering a signal inputted through the antenna ANT. The RF amplifier 20 is a signal for amplifying a signal that has passed through the filter unit 10. [ The inquiry path 30 transmits a signal of a desired band among the signals transmitted from the RF amplifier.

The signal selection unit 40 selects and delivers an RF signal of a predetermined frequency band from among the transmitted RF signals. The signal selection unit 40 includes a phase locked loop circuit, a mixing circuit, an oscillator, and the like to select and transmit RF signals in a predetermined frequency band. In recent years, it is common to implement these circuits by including them in one chip .

The digital SAW filter 51 is for digital processing and the video signal SAW filter 52 and the audio signal SAW filter 53 are for SAW processing of analog video signals and audio signals.

The SAW filter is a filter that uses a structure in which two comb-like metal plates are arranged on the piezoelectric substrate so as to be shifted on both sides and SAW (surface acoustic wave) is generated on the piezoelectric substrate when electrical signals are inputted in one direction. The mechanical vibration, which is called the surface acoustic wave, is converted into an electrical signal again from the opposite side. If the frequency of the surface acoustic wave of the piezoelectric plate itself is different from the frequency of the inputted electrical signal, the signal is not transmitted and is dying. That is, it becomes a BPF (band pass filter) that passes only the frequency equal to the mechanical-material frequency of the filter itself. The SAW filter has a very narrow bandwidth to pass through compared to a filter using an artificial LC resonance principle, so that the signal of the unnecessary frequency is almost completely filtered out. So, if you want to select the frequency of the desired signal with a narrow bandwidth, the SAW filter is the best feature. It is widely used in RF signal processing circuits that use intermediate frequencies.

The IF amplifier 60 amplifies the signal output from the digital SAW filter 51 and outputs the amplified signal to the digital demodulator 70. The digital demodulator 70 receives a signal provided from the IF amplifier 60, demodulates it, and outputs the demodulated signal. The analog demodulator 80 demodulates and outputs the signals output from the video signal SAW filter 52 and the audio signal SAW filter 53.

RF signal processing circuits can be applied to devices used in various regions. Therefore, the RF signal processing circuit must process the RF signal stably in various frequency bands. The RF signal processing circuit as shown in Fig. 1 has a digital SAW filter (7 / 8MHz), a video signal SAW (38.9MHz) filter and an audio signal SAW filter so as to be applied to a European tuner, As shown in FIG. In order to receive the SECAM L / LP method, the audio signal SAW filter is used by using the switching operation.

Recently, a digital demodulating function and an analog demodulating function are implemented using a single demodulator. The functions of the video signal SAW filter 52 and the audio signal SAW filter 53 are also implemented in the demodulator.

2 is a block diagram showing an improved RF signal processing circuit for explaining the present invention.

2, the RF signal processing circuit includes a filter unit 110, an RF amplifier 120, a tuning circuit 130, a signal selecting unit 140, a digital SAW filter 150, an IF amplifier 160 ), A digital / analog demodulator (170), and an oscillator (141). The oscillator 141 generates a clock signal and provides it to the signal selection unit 140. The phase locked loop circuit in the signal selection unit 140 receives the clock signal and operates. Since the blocks shown in FIG. 2 have the same functions as the blocks shown in FIG. 1, detailed description thereof will be omitted.

An analog modulator included in the RF signal processing circuit uses an analog voltage modulating oscillator and a crystal oscillator to process an RF signal internally. The digital modulator provided in the RF signal processing circuit does not have a voltage control oscillator and uses a clock and DSP (Digital Signal Process) generated therein. In this case, there is a problem that a clock signal generated in the digital modulator adversely affects a block of another RF signal processing circuit on the IF signal transmission line.

In order to solve this problem, the present invention provides an RF signal processing circuit having a trap filter for preventing a clock signal from being transmitted on an incorrect path to a line to which an IF signal is transmitted.

3 is a block diagram showing an RF signal processing circuit according to a preferred embodiment of the present invention.

3, the RF signal processing circuit according to the present embodiment includes a trap filter unit 300 between the signal selecting unit 200 and the digital demodulator 400. As shown in FIG. The trap filter unit 300 prevents the clock signal generated in the internal operation of the digital demodulator 400 from being transmitted to the signal selector 200. The digital demodulator 400 outputs a video signal CVBS and a sound signal SIF through a demultiplexing operation. The trap filter unit 300 includes capacitors C1 to C6, a resistor R2 and inductors L1 and L2.

The trap filter unit 300 includes a capacitor C1 and an inductor L2 connected between a node A and a node C and a capacitor C3 and an inductor L1 connected between the nodes B and C, A capacitor C2 disposed between the node A and the node B, a capacitor C4 and an inductor R2 disposed between the node C and the node D, A capacitor C5 connected to the node D, and a capacitor C6 connected to the node D. The capacitors C1 and C3 are 1 pF, the capacitors C2 and C4 are 27 pF, the capacitors C5 and C6 are 100 nF and the inductors L1 and L2 are 270 nH. Capacitors C5 and C6 use 100 nF.

The RF signal processing circuit shown in FIG. 3 includes only the trap filter unit 300, the signal selecting unit 200, and the modulator 400, but all of the blocks shown in FIG. 2 are provided. The trap filter unit 300 may be provided at any position between the signal selection unit 200 and the digital demodulator 400 and the clock signal generated in the internal operation of the digital demodulator 400 is most effectively transmitted to other blocks It can be disposed at a position that prevents the bad influence from being exerted. For example, at the input or output of the digital SAW filter 150 and the IF amplifier 160, which are the blocks between the signal selector 140 and the digital / analog demodulator 170 in FIG. In addition, not only one trap filter section but also two or more trap filter sections can be disposed between the signal selecting section 140 and the digital / analog demodulator 170.

Since the clock signal transmitted from the digital demodulator 400 to the signal selecting unit can be removed in the trap filter unit 300, the adverse effect on each block of the RF signal processing circuit including the signal selecting unit can be eliminated can do.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

1 is a block diagram showing an RF signal processing circuit for explaining the present invention.

2 is a block diagram showing an RF signal processing circuit for explaining the present invention.

3 is a block diagram showing an RF signal processing circuit according to a preferred embodiment of the present invention.

Description of the Related Art [0002]

ANT: antenna 200: signal selector

300: trap filter 400: demodulator

Claims (10)

A signal selector for transmitting a signal of a desired band among the RF signals inputted through the antenna ANT; A demodulator for demodulating a signal provided from the signal selection unit using a clock signal generated internally; And A trap filter unit for preventing a clock signal generated in the demodulator from propagating to the signal selector; Lt; / RTI > And a first wiring and a second wiring for transferring the first and second IF signals from the signal selection unit to the demodulator, The trap filter section A first inductor and a first capacitor disposed on the first wiring; A second inductor and a second capacitor disposed on the second wiring; A third capacitor and a fourth capacitor disposed between the first wiring and the second wiring, And a resistor disposed between the first wiring and the second wiring, wherein the third capacitor connects one node of the first inductor and the second inductor, and the fourth capacitor connects the first inductor and the second inductor An RF signal processing circuit for connecting the other node of the inductor. delete delete The method according to claim 1, The trap filter section A fifth capacitor connected in parallel with the first inductor, and a sixth capacitor connected in parallel with the second inductor. A signal selector for transmitting a signal of a desired band among the RF signals inputted through the antenna ANT; A digital SAW filter for filtering and transmitting a signal transmitted from the signal selector; A demodulator for demodulating a signal provided from the digital SAW filter using a clock signal generated internally; And And a trap filter unit disposed between the digital SAW filter and the demodulator to prevent a clock signal generated in the demodulator from propagating to the signal selector, And a first wiring and a second wiring for transmitting the first and second IF signals from the signal selector to the digital SAW filter, The trap filter section A first inductor and a first capacitor disposed on the first wiring; A second inductor and a second capacitor disposed on the second wiring; A third capacitor and a fourth capacitor disposed between the first wiring and the second wiring, And a resistor disposed between the first wiring and the second wiring, wherein the third capacitor connects one node of the first inductor and the second inductor, and the fourth capacitor connects the first inductor and the second inductor An RF signal processing circuit for connecting the other node of the inductor. 6. The method of claim 5, And an IF amplifier for amplifying a signal output from the digital SAW filter and transmitting the amplified signal to the demodulator. 6. The method of claim 5, A signal provided from the antenna An RF amplifier, and a tuning circuit arranged in series for transmission to the signal selector. delete delete 6. The method of claim 5, A fifth capacitor connected in parallel with the first inductor, and a sixth capacitor connected in parallel with the second inductor.

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