KR101572177B1 - Semiconductor wafer and test method of the same - Google Patents

Semiconductor wafer and test method of the same Download PDF

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Publication number
KR101572177B1
KR101572177B1 KR1020140102527A KR20140102527A KR101572177B1 KR 101572177 B1 KR101572177 B1 KR 101572177B1 KR 1020140102527 A KR1020140102527 A KR 1020140102527A KR 20140102527 A KR20140102527 A KR 20140102527A KR 101572177 B1 KR101572177 B1 KR 101572177B1
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South Korea
Prior art keywords
semiconductor wafer
drain
mos transistor
resistance
wafer
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KR1020140102527A
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Korean (ko)
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양정균
천병태
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주식회사 에이엘티
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The present invention relates to a semiconductor wafer and a test method thereof. In the semiconductor wafer having a back side drain structure, a drain pad is formed on a scribe lane, thereby uniformly measuring impedance of the wafer without using a chuck when the semiconductor wafer is tested.

Description

Semiconductor wafer and test method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly, to a semiconductor wafer having a back drain structure such as a power MOS transistor and a test method thereof.

Generally, the structure of the MOS transistor varies depending on the required characteristics, such as the position and shape of the source, the drain, and the gate. Since such a MOS transistor has to maintain a resistance (Rdson) between a proper drain source in a turn-on state irrespective of the structure thereof, a MOS transistor is fabricated on the wafer, and then power is applied to the gate of the MOS transistor. The card measures the resistance between the drain and the source.

Such a method can be easily measured when the source and the drain are formed on the upper side of the wafer. However, when the drain is provided on the back side of the wafer, a chuck which contacts the drain separately must be used. The resistance measuring method will be described in detail with reference to the accompanying drawings.

The structure of the power MOS transistor will be described with reference to FIG. 1 before a method of measuring the ON resistance of the semiconductor wafer will be described.

As shown in FIG. 1, the power MOS transistor is formed with an n-drift layer 12 on an n + semiconductor substrate 10. The n-drift layer 12 is epitaxially grown on the semiconductor substrate 10 and the drift layer 12 is formed with a P-well 14 and an n + source region 16 is formed in the P- do. A source electrode 18 is formed on the source region. A gate insulating film 20 is formed on the surface of the P well region 14 in the region between the two source regions 16 and a gate electrode 22 is formed on the gate insulating film.

According to the above structure, when a predetermined voltage is applied to the gate electrode 22 of the power MOS transistor, a channel inverted by electrons is formed on the surface of the P source region under the gate electrode. And the electrons injected from the source electrode 18 doped with n + move to the drain electrode through the channel.

In the off state, the structure of the power MOS transistor is the same as that of the PIN diode formed of the P well 14, the n-type drift layer 12, and the n + substrate 10.

However, the drift layer 12 provides a path between the source and the drain when the device is on. Therefore, the resistance of the drift layer 12 contributes to the drain-source resistance of the device.

The doping level and thickness of the n-drift layer 12 affect both the breakdown voltage and the drain-source resistance of the transistor device. The thicker the drift layer 12 and the lower the doping level, the higher the breakdown voltage of the device. Conversely, the thinner the drift layer 12 and the higher the doping level, the lower the drain-source resistance.

In order to measure the on-channel resistance of the power MOS transistor of the vertical structure, a current is applied through a chuck of a probe station, and then a voltage is measured. Generally, in the case of low-power products, the on-channel resistance is small, which is equivalent to several mΩ. Therefore, high-precision measurement is required.

2 is a configuration diagram of the on-resistance measuring apparatus of the conventional back drain structure semiconductor wafer.

As shown, the wafer 3 is placed on the chuck 1. A drain voltage is applied to the chuck 1, and a source and a gate voltage are applied through the probe card 4. A plurality of bay holes (2) for fixing the wafer are formed on the chuck.

That is, the probe card 4 and the chuck 1 are connected to both ends of the current path leading to the source and the drain, respectively, and the drain resistance is measured using the relationship between the current and the voltage. However, in the case of using the metal chuck 1 which directly contacts the drain as described above, the measured value includes the resistance of the chuck 1 itself and the contact resistance between the drain and the chuck, so that accurate measurement can not be performed.

In order to reduce the contact resistance between the wafer and the chuck, gold-plated chucks with a small resistance are used, and the number and size of the vacuum holes for fixing the wafer on the chuck are changed and optimized. However, the fundamental problem such as oxidation of the chuck can not be solved, and the contact resistance of the chuck increases non-uniformly over time. This increases the cost of chuck management and the cost of retesting wafers with low yields.

The following Patent Document 1 describes a method of reducing the on-resistance by adjusting the thickness and doping of the drift layer, but it can not solve the fundamental problem of using the chuck.

Korean Patent Registration No. 10-1413879 (Bulletin of June 30, 2014)

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor wafer and a wafer testing method which can facilitate on resistance testing.

It is another object of the present invention to provide a semiconductor wafer and a test method capable of minimizing on-resistance and measuring on-resistance without using a chuck of a probe station.

In order to achieve the above object, a semiconductor wafer according to the present invention is characterized in that a drain pad is formed in a scribe lane in a semiconductor wafer having a rear drain structure.

And a drain region doped with an impurity is formed under the drain pad.

And a contact for electrically connecting the semiconductor substrate and the drain pad is formed under the drain pad.

In accordance with another aspect of the present invention, there is provided a method of testing a semiconductor wafer of a back drain structure, comprising the steps of: applying a voltage to a gate electrode to form a drain pad And the on-resistance of the MOS transistor is measured.

And a drain region doped with impurities of the same kind as the semiconductor substrate is formed under the drain pad.

And a contact for electrically connecting the drain pad and the semiconductor substrate is formed under the drain pad.

As described above, according to the semiconductor wafer and the test method of the present invention, the on-resistance of the wafer can be uniformly measured without using a chuck in the semiconductor wafer test.

According to the semiconductor wafer and the test method of the present invention, the drain channel can be connected only by adding a needle for the drain test pad to the needle of the probe card, so that the test can be performed without using the chuck of the probe station. Therefore, since the expensive gold chuck is not used, it is possible to perform a low-cost test.

Further, according to the semiconductor wafer and the test method of the present invention, since the oxidation of the chuck is not sensitive, the rate of occurrence of the low rate is lowered, and the productivity is improved.

Further, according to the semiconductor wafer and the test method of the present invention, it is possible to obtain a measurement value of a uniform characteristic for a low on-channel resistance of a low power product.

Further, according to the semiconductor wafer and the test method of the present invention, the number of drain electrodes can be increased according to the amount of current flowing to the drain, and various sizes and shapes can be produced depending on the type of the probe card.

1 is a cross-sectional view of a power MOS transistor according to the prior art;
2 is a block diagram of an apparatus for measuring on-resistance of a conventional power MOS transistor structure wafer
3 is a cross-sectional view and a plan view of a power MOS transistor structure wafer according to an embodiment of the present invention;
4 is a cross-sectional view and a plan view of a power MOS transistor structure wafer according to another embodiment of the present invention
FIG. 5 is a cross-sectional view showing an embodiment of a rear drain power MOS transistor
6 is a structural diagram of an apparatus for measuring on-resistance of a power MOS transistor structure wafer according to the present invention

Hereinafter, a semiconductor wafer and a test method according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view and a plan view of a power MOS transistor structure wafer according to a preferred embodiment of the present invention.

In the semiconductor wafer according to the preferred embodiment of the present invention, an n-drift layer 12 is formed on an n + semiconductor substrate 10. The n-drift layer 12 is epitaxially grown on the semiconductor substrate 10. The substrate 10 and the drift layer 12 are formed of a semiconductor material. For example, the semiconductor substrate 10 may be formed of silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), germanium (Ge), gallium nitride (GaN) As the N-type impurity, phosphorus, nitrogen and the like can be used. The impurity concentration of the substrate 10 may be approximately 10 19 to 10 20 / cm 3 . The impurity concentration of the drift layer 20 may be approximately 10 14 to 10 17 / cm 3 .

A p + body region 14 is formed in the drift layer 12 and an n + source region 16 is formed in the p + body region 14. The p + body region 14 is also referred to as a p-well. A source electrode 18 is formed on the source region 16. The p + body region 14 may be doped with a p-type impurity, such as aluminum (Al), at a concentration of approximately 10 16 to 10 18 / cm 3 . A gate insulating film 20 is formed on the surface, and a gate electrode 22 is formed on the gate insulating film.

A drain region 26 doped with n + is formed in a predetermined upper region of the drift layer 12 and a drain pad 28 is formed in an upper portion of the drain region 26. The drain region 26 is doped with n impurity at a relatively high concentration. The n-type impurity may be phosphorus (P) or nitrogen (N), and the doping concentration may be approximately 10 19 to 10 20 / cm 3 .

The source electrode 18 and the drain pad 28 are preferably made of the same material as the conductive material. The drain pad 28 is not a structure of a MOS transistor but is a part to be removed from the test and added to a test, so the term pad is used, but the same material is used. For example, the source electrode 18 and the drain electrode 28 may be formed of a metal such as aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru) For example, tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), or zirconium (Zr).

The drain pad 28 is formed in the scribe line 32 of the semiconductor wafer as shown in the plan view of FIG. 3 (b). A scribe lane is a region for separating each chip, which is an area between each chip and a chip, which is discarded. Accordingly, after the test is completed, the drain pad formed in the scribe lane 32 is removed, and after the drain pad is removed, it operates like a normal MOS transistor as in FIG.

In the power MOSFET, when a predetermined voltage is applied to the gate electrode 22, an electronically inverted channel is formed on the surface of the p + body region under the gate electrode, and electrons injected from the source electrode 18 And moves to the drain pad 28 through the channel. A dotted line in Fig. 3 shows the movement path of the drain current.

FIG. 4 illustrates another embodiment of the present invention in which a contact 30 for electrically connecting the substrate 10 and the drain pad 28 is added in place of the drain region 26. In the above structure, the n + substrate serves as a drain, and the drain current flows to the drain pad 28 through the n + substrate 10 as indicated by the dotted arrow in FIG.

The back surface drain structure is not limited to the above-described embodiment and can be variously applied. FIG. 5 shows an example of a power MOS transistor of a rear-side drain structure. The structures (a), (b), and (c) are all applicable to the present invention.

FIG. 6 is a block diagram of an apparatus for measuring on-resistance of a power MOS transistor structure wafer according to the present invention. Referring to FIG. 6, channel formation can be understood more clearly.

According to the present invention, the drain cable 5 is connected to the probe card 4 without being connected to the chuck. That is, the source and gate voltages are applied through the needles 6 of the probe card and the drain voltage is applied through the drain cable 5 of the probe card. Therefore, the resistance of the chuck is not affected by the on resistance measurement.

As described above, in the semiconductor wafer having the above-described structure, a needle for the drain pad is added to the probe card having the conventional gate and source terminal without being affected by the chuck resistance of the probe station in the test, and the drain channel You can connect them.

Since the drain pad can increase the number of drain pads according to the amount of current flowing to the drain, it is possible to manufacture various sizes and shapes according to the type of the probe card.

Since the scribe lane is removed after the wafer test is completed, the package assembly can be done in the usual way after the test.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

1: Chuck 2: Bayou Hall
3: wafer 4: refresh card
5: Drain cable 6: Needle
10: semiconductor substrate 12: drift layer
14: p + body region 16: n + source region
18: source electrode 20: gate insulating film
22: gate electrode 26: n + drain region
28: drain pad 30: contact
32: Scrabble

Claims (6)

delete In a semiconductor wafer having a rear drain structure,
A semiconductor substrate provided on a back surface of the semiconductor wafer;
A drain pad formed in a scribe lane of the semiconductor wafer; And
And a drain region formed under the drain pad and including impurities of the same kind as impurities of the semiconductor substrate doped with the same concentration as in the semiconductor substrate. In a semiconductor wafer having a rear drain structure,
A semiconductor substrate provided on a back surface of the semiconductor wafer;
A drain pad formed in a scribe lane of the semiconductor wafer; And
And a contact formed to electrically connect the drain pad and the semiconductor substrate. delete The method of testing a semiconductor wafer according to claim 2,
When a voltage is applied to a gate electrode of a MOS transistor formed in a chip region of the semiconductor wafer, a current path is formed from a source of the MOS transistor to a drain pad formed in a scribe lane of the semiconductor wafer to measure the on resistance of the MOS transistor Wherein the semiconductor wafer is a semiconductor wafer. The method of testing a semiconductor wafer according to claim 3,
When a voltage is applied to a gate electrode of a MOS transistor formed in a chip region of the semiconductor wafer, a current path is formed from a source of the MOS transistor to a drain pad formed in a scribe lane of the semiconductor wafer to measure the on resistance of the MOS transistor Wherein the semiconductor wafer is a semiconductor wafer.
KR1020140102527A 2014-08-08 2014-08-08 Semiconductor wafer and test method of the same KR101572177B1 (en)

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KR1020140102527A KR101572177B1 (en) 2014-08-08 2014-08-08 Semiconductor wafer and test method of the same

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