KR101570064B1 - Duty Cycle amendment circuit - Google Patents

Abstract

The present invention relates to a circuit for correcting a duty cycle. A duty cycle correction circuit according to an exemplary embodiment of the present invention receives a first clock signal to be corrected and a second clock signal having a phase difference from the first clock signal and outputs the first clock signal and the second clock signal, A differential clock signal generator for generating a differential clock signal by performing an XOR operation on the differential clock signal and a duty cycle corrector for generating a corrected clock signal whose level is switched at a time point corresponding to a rising edge point of the differential clock signal.

Description

[0001] Duty Cycle Amendment Circuit [0002]

The present invention relates to a circuit for correcting a duty cycle.

With the recent development of digital devices, high-performance multimedia devices such as HDTV, digital set-top box (D-STB) and Blu-ray player are growing. In this regard, in order to operate the system normally in a high-speed operation device such as a data converter, a clock signal having a rising edge and a falling edge at the same interval is required.

Here, the duty cycle is 50% when the rising edge and the falling edge have the same interval. The duty cycle is calculated in terms of pulse width / period, and the unit is%.

Specifically, when the rising edge and the falling edge of the clock signal have the same interval, the high level and the low level have the same pulse width and the duty cycle is the high level pulse width / (high level pulse width + low level pulse width) The duty cycle of the clock signal becomes 50%.

Particularly, the most important part to be considered in designing a time-interleaved analog / digital converter is the clock timing part. A clock signal with the same rising edge and falling edge must be input to the Track and hold of each Sub-ADC (Analog / Digital Converter). Sub-ADCs must be clocked sequentially in accordance with the number of ADCs used for time- Phase difference between the two.

In addition, the clock signal to be finally output should be sequentially read out and output so that the data do not overlap between the sub-ADCs.

At this time, if the duty cycle of the clock signal is not 50%, there is a problem that signals are duplicated or missing in the track and hold process of the ADC, and the performance thereof is remarkably deteriorated.

Therefore, there is a conventional duty cycle correction circuit that corrects the duty cycle of the clock signal to 50%. However, the conventional duty cycle correction circuit has a problem in that the design is complicated because it corrects the signal by the analog method. Therefore, a duty cycle correction circuit capable of correcting the duty cycle by using a simpler digital circuit is a reality.

It is an object of the present invention to provide a duty cycle correction circuit that outputs a clock signal having a duty cycle of 50%.

A duty cycle correction circuit according to an exemplary embodiment of the present invention receives a first clock signal to be corrected and a second clock signal having a phase difference from the first clock signal and outputs the first clock signal and the second clock signal, A differential clock signal generator for generating a differential clock signal by performing an XOR operation on the differential clock signal and a duty cycle corrector for generating a corrected clock signal whose level is switched at a time point corresponding to a rising edge point of the differential clock signal .

In one embodiment, the phase difference between the first clock signal and the second clock signal is 180 degrees, and the differential clock signal generated by performing the XOR operation has a rising edge point at a constant interval .

In one embodiment, the duty cycle correcting unit may be a D-Flip-Flop that feeds back the opposite signal of the output as an input.

In one embodiment, the differential clock signal generator further generates an opposite differential clock signal opposite to the differential clock signal, and generates the corrected clock signal and the differential clock signal based on the differential clock signal and the opposite differential clock signal. And a selector for selecting any one of the first clock signal and the second clock signal.

In one embodiment, the selector may select the corrected clock signal when the opposite-phase differential clock signal is at a high level, and may select the first clock signal when the differential clock signal is at a high level .

In one embodiment, when the first clock signal is selected by the selector, the delay unit further delays the first clock signal to match the phase of the differential clock signal with the phase of the selected first clock signal .

According to the present invention, a clock signal whose duty cycle is not 50% can be corrected and output to have a duty cycle of 50%. Therefore, the design cost can be reduced by using a digital method instead of the conventional analog method.

1 is a block diagram illustrating a duty cycle correction circuit according to an embodiment of the present invention.
2 is a conceptual diagram for explaining a duty cycle correction concept according to an embodiment of the present invention.
3 is a conceptual diagram for explaining a pulse signal output from each node when the duty cycle according to an embodiment of the present invention is not 50%.
4 is a conceptual diagram for explaining a pulse signal output from each node when the duty cycle is 50% according to an embodiment of the present invention.
5A and 5B are simulation results according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical idea of the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly explain the present invention, parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification.

Although the terms used in the present invention have been selected in consideration of the functions of the present invention, it is possible to change the presently widely used general terms according to the intention of the technician in the technical field, custom or the emergence of new technology. Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term rather than the name of the term, and the content of the present invention throughout the present invention.

1 is a circuit diagram showing a duty cycle correction circuit according to an embodiment of the present invention.

1, a duty cycle correction circuit 100 according to an exemplary embodiment of the present invention includes a differential clock signal generator 110, a duty cycle corrector 120, a selector 130, a delay unit 140, a buffer 150, and the like.

First, a method of correcting a clock signal whose duty cycle is not 50% according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

Here, the duty cycle is a numerical value representing the ratio of the pulse width PW to the pulse period T, and can be expressed by the equation (PW / T), and the unit is [%].

The differential clock signal generator 110 receives the first clock signal CLKn to be corrected and the second clock signal CLKp having a phase difference from the first clock signal CLKn and outputs the first and second The differential clock signal X can be generated by performing an XOR operation on the clock signals CLKn and CLKp.

The XOR operation is an exclusive OR operation. When the two input signals have a value of 1 or 1, the input signal is 0. When the input signal has a value of 1 or 0, 1, and if the two input signals have a value of 0, 0, it outputs the value of l.

The clock signal of the present invention has the form of a square wave signal and has a value of 1 at a high level and 0 at a low level. Also, a portion rising from a low level to a high level is referred to as a rising edge, and a point at which the rising edge exists is referred to as a rising edge point. A portion falling from a high level to a low level is referred to as a falling edge, and a point at which the falling edge exists is defined as a falling edge point.

The phase difference between the first clock signal CLKp and the second clock signal CLKn is preferably 180 degrees. 2, the duty cycle correction circuit according to an embodiment of the present invention includes a clock signal CLKp to be corrected, a clock signal CLKn having a phase difference of 180 degrees with the clock signal CLKp, The corrected clock signal having a duty cycle of 50% is generated by using the fact that the point of the rising of the clock signals CLKp and CLKn is constant.

In FIG. 1, the differential clock signal generator 110 is shown receiving a first clock signal CLKp and a second clock signal CLKn independently from the outside. However, if the first clock signal CLKp is inputted, the phase of the first clock signal CLKp may be shifted 180 degrees by using a phase shifter (not shown) The 180-degree shifted second clock signal CLKn and the first clock signal CLKp may be used.

The differential clock signal generator 110 may generate the differential clock signal X by performing an XOR operation using the first clock signal CLKp and the second clock signal CLKn. Specifically, if the first clock signal CLKp and the second clock signal CLKn are both at the high level or all at the low level, a low level signal is output to the node X. When the first clock signal CLKp and the second clock signal CLKn are low, When the signal CLKn is different between the high level and the low level, a high level signal can be outputted to the X node.

The differential clock signal X generated through the XOR operation is half the period and twice the frequency of the first clock signal to be corrected.

The differential clock signal X shown in FIG. 3 shows the XOR operation performed on the first clock signal CLKp and the second clock signal CLKn. It should be noted that the differential clock signal X is shown slightly delayed with respect to the time axis (x axis) because it reflects a slight delay in the time according to the XOR operation.

The differential clock signal generator 110 may output the differential clock signal Xb, which is the opposite signal to the differential clock signal X, to the Xb node.

The opposite differential clock signal Xb has a low level when the differential clock signal X is at the high level and a signal having the high level when the differential clock signal X is at the low level.

The opposite differential clock signal Xb may serve as a reference for selecting a signal to be output from the selector 130 when the duty cycle of the first clock signal CLKn to be corrected is 50%.

The differential clock signal X generated by the differential clock signal generator 110 may have rising edge points of the same interval.

Duty correction unit 120 may receive the differential clock signal X and generate a clock signal whose duty cycle is corrected. The duty correction unit 120 may generate a corrected clock signal whose level is switched at a time point corresponding to the rising edge point of the differential clock signal X. [

The duty corrector 120 may be a D-Flip-Flop (DFF). Specifically, the duty corrector 120 may be implemented to feedback the opposite signal (Q bar) of the DFF output to the input node D. The DFF 120 may switch the output signal Q or the opposite signal Q bar of the output signal to a high level or a low level at the rising edge of the received signal X, To perform the switching operation.

In one embodiment, DFF 120 may be initialized from a Q node to a high level and from a Q bar node to a low level. In this state, the low level output from the Q bar node is fed back to the input node D, and the Q node outputs a low level signal. Thereafter, when the differential clock signal X is input, the Q-bar node can be switched at the rising edge of the differential clock signal X. When the low level output from the Q-bar node is switched to the high level at the rising edge of the differential clock signal X, the switched high level is fed back to the input node D and the signal output from the Q- To a high level.

The duty corrector 120 may output the corrected clock signal Xt whose level is switched at a time point corresponding to the rising edge of the received differential clock signal X. In this case, The corrected clock signal Xt thus generated is twice as frequent as the differential clock signal X, and the frequency is halved. Therefore, the corrected clock signal Xt has the same frequency and period as the first clock signal to be corrected.

As shown in FIG. 3, the clock signal Xt whose duty cycle of the first clock signal CLKp to be corrected is corrected to 50% can be generated. The reason why the corrected clock signal Xt is delayed slightly with respect to the time axis (x axis) is that it reflects that the time is slightly delayed by performing the feedback process in the duty cycle correction unit 120 And that the

Hereinafter, a case where a clock signal having a duty cycle of 50% according to an embodiment of the present invention is input will be described with reference to FIGS. 1 and 4. FIG.

The differential clock signal generator 110 may generate the differential clock signal X by performing an XOR operation using the first clock signal CLKn and the second clock signal CLKp to be corrected. Also, the differential clock signal generator 110 may output the opposite differential clock signal Xb, which is the opposite of the differential clock signal X, to the Xb node.

However, when the duty cycle of the first clock signal CLKn to be corrected is 50%, the second clock signal CLKp having a phase difference of 180 degrees and the first clock signal CLKn are mutually opposite signals. Accordingly, the differential clock signal X output from the differential clock signal generator 110 is a signal having only a high level. The differential clock signal Xb, which is the opposite of the differential clock signal X, becomes a signal having only a low level.

In this case, even if the differential clock signal X is input to the duty correction unit 120, since the differential clock signal X does not have a rising edge, the signal Xt output from the duty correction unit 120 is It does not have a square wave signal. Therefore, when a signal having a duty cycle of 50% is input, a method capable of directly outputting the input signal is required.

Accordingly, the duty cycle correction circuit according to the embodiment of the present invention selects the corrected clock signal and the first clock signal based on the differential clock signal X and the opposite differential clock signal Xb (130).

When a clock signal requiring no correction (duty cycle of 50%) is inputted, the selector 130 outputs the input clock signal as it is. When a clock signal requiring correction is inputted, the duty corrector 120 corrects And outputs the clock signal Xt.

The selection unit 130 may use a multiplexer (MUX). The multiplexer used in the present invention plays a role of selecting and outputting any one of the signals input through the plurality of nodes according to a predetermined method.

The selector 130 selects the first clock signal CKLp or the second clock signal Xb based on the differential clock signal X output from the differential clock signal generator 110 and the differential clock signal Xb opposite thereto. It is possible to select and output the corrected clock signal Xt.

If the opposite differential clock signal has a high level, the selector 130 determines that a clock signal required to correct the duty cycle is input. The selector 130 selects the corrected clock signal generated by the duty corrector 120, (Xt) can be selected. When the differential clock signal has only a high level, the selector 130 determines that a clock signal that does not require the duty cycle correction is input. The selector 130 selects the first clock signal CLKp) as it is.

When the first clock signal CLKp is selected in the selector, the duty cycle correction circuit according to the embodiment of the present invention selects the duty cycle of the first differential clock signal X from the differential clock signal X generated by the differential clock signal generator 110, And a delay unit 140 for delaying the first clock signal CLKp to match the phase of the clock signal CLKp.

4, the delay unit 140 may delay the phase of the first clock signal CLKp selected by the selector 130 to a phase of the differential clock signal X so as to match the phase of the differential clock signal X, And output a delayed clock signal CLKp '.

The duty cycle correction circuit according to an exemplary embodiment of the present invention may further include a buffer 150 for temporarily storing the clock signal output from the duty correction unit 120 or the selection unit 130. [

The buffer 150 temporarily stores the data or the signal to compensate for the difference between the data transmission speed and the processing speed between the devices when transmitting data, signals, etc. from one device to another device. The output signals (Output, outp) output in FIG. 3 to FIG. 4 reflect the delay time according to the buffer 150.

5A and 5B are graphs showing simulation results performed in the duty cycle correction circuit according to an exemplary embodiment of the present invention when a clock signal having a duty cycle of 50% is input and a clock signal having a duty cycle of 50% Fig.

FIG. 5A is a diagram corresponding to FIG. 3, where when the clock signal CLKp having a duty cycle of 60% is input, the duty cycle of the corrected clock signal Xt and the output signals Out, outp becomes 50.1% .

4, when a clock signal CLKp having a duty cycle of 50% is input, the clock signal CLKp 'delayed according to the phase of the differential clock signal X is output as the output signals Output, outp), and then output.

By using the duty cycle correction circuit according to an embodiment of the present invention, a clock signal whose duty cycle is not 50% can be corrected to have a duty cycle of 50%. Also, even if a clock signal having a duty cycle of 50% is input, it can be output as it is. Therefore, a clock signal having a duty cycle of 50% can be output by using a simple digital circuit instead of a complicated analog circuit.

The above-described simulation server is not limited to the configuration and method of the embodiments described above, but the embodiments may be configured such that all or some of the embodiments are selectively combined so that various modifications can be made It is possible.

100: duty cycle correction circuit
110: Differential clock signal generator
120: Duty correction unit
130:
140:
150: buffer

Claims (6)

A circuit for correcting a duty cycle for a clock signal to be corrected,
A first clock signal to be corrected and a second clock signal having a phase difference with respect to the first clock signal and performing an XOR operation on the input first and second clock signals to generate a differential clock signal, A signal generator; And
And a duty cycle correction unit for generating a corrected clock signal whose level is switched at a time point corresponding to a rising edge point of the differential clock signal,
Wherein the duty cycle correction unit is a D-Flip-Flop that feeds back the opposite signal of the output as an input.
The method according to claim 1,
The phase difference between the first clock signal and the second clock signal is 180 degrees,
Wherein the differential clock signal generated by performing the XOR operation has a rising edge point at a predetermined interval.
delete The method according to claim 1,
Wherein the differential clock signal generator further generates an opposite differential clock signal opposite to the differential clock signal,
Further comprising a selector for selecting one of the corrected clock signal and the first clock signal based on the differential clock signal and the opposite differential clock signal.
5. The method of claim 4,
Wherein the selection unit comprises:
Selects the corrected clock signal when the opposite differential clock signal is at a high level,
And selects the first clock signal when the differential clock signal is at a high level.
6. The method of claim 5,
And a delay unit for delaying the first clock signal to match the phase of the differential clock signal with the phase of the selected first clock signal when the first clock signal is selected by the selection unit, Cycle correction circuit.

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