KR101568160B1 - A frequency multiplier - Google Patents

Abstract

A frequency doubler is provided. Wherein the frequency doubler comprises a duty cycle correction loop coupled to a delay locked loop and a delay locked loop and including a first phase interpolator, a clocked edge coupler, and a duty cycle detector, wherein the first phase interpolator is coupled to a delay locked loop A clocked edge combiner receives a pair of second clocks and a pair of third clocks, each of which is phase-interpolated from the first phase interpolator and the delay locked loop, and outputs a fourth clock, , The duty cycle detector outputs a first signal for correcting the duty cycle of the fourth clock provided from the clock edge combiner, and the fourth clock has a multiplication frequency.

Description

{A FREQUENCY MULTIPLIER}

The present invention relates to a frequency multiplier.

Phase-locked loops and delay-locked loops are widely used to reduce the scratch and jitter of clock signals in high-speed microprocessor-memory interfaces and high-speed communication systems.

Generally, the delay locked loop is less jittery than the phase locked loop and has better frequency stability than the phase locked loop because phase noise caused by power supply noise is not accumulated in the voltage controlled delay line, and is easily implemented as a digital circuit. Due to these characteristics, delay locked loops are widely used to synchronize clocks or generate multi-phase clock signals.

Korean Patent No. 10-1012678 (Published on Aug. 12, 2010)

It is an object of the present invention to provide a frequency multiplier capable of correcting the duty cycle of a clock having a multiplication frequency by adding a phase interpolator and a duty cycle detector to a delay locked loop.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

One embodiment of a frequency doubler of the present invention for solving the above problems includes a duty cycle correction loop connected to a delay locked loop and a delay locked loop and including a first phase interpolator, a clocked edge coupler, and a duty cycle detector Wherein the first phase interpolator is provided with a pair of first clocks from a delay locked loop and the clocked edge combiner comprises a pair of second clocked interpolated phases from a first phase interpolator and a delay locked loop, The duty cycle detector outputs a first signal for correcting the duty cycle of the fourth clock provided from the clock edge combiner, and the first signal is provided as a delay locked loop And the fourth clock has a multiplication frequency.

A second phase interpolator receiving a third signal from the control logic; a third phase interpolator receiving a fifth clock from the outside and delaying the fifth clock, And a delay line for providing a plurality of sixth clocks to the phase multiplexer unit, wherein the phase multiplexer unit receives a plurality of sixth clocks and outputs a first phase having a pair of first clocks A multiplexer and a second phase multiplexer which receives a plurality of sixth clocks and outputs a pair of seventh clocks and a pair of first clocks with a phase difference of 30 degrees.

The first phase interpolator interpolates the phases of a pair of first clocks provided from the first phase multiplexer and outputs a pair of second clocks, and the second phase interpolator interpolates the pair of first clocks provided from the first phase multiplexer, And the third clock of the pair can be outputted by interpolating the phase of the seventh clock.

Wherein the delay locked loop further comprises a digital filter connected to a phase detector and a phase detector connected to a second phase interpolator, wherein the phase detector compares a pair of seventh clocks provided from the second phase interpolator with a fifth clock To output a fourth signal, and the digital filter may provide the fourth signal to the control logic from a phase detector.

The digital filter may receive a fifth signal from the outside and the fifth signal may control the operation of the delay locked loop.

The control logic may adjust the third signal using a fourth signal and the adjusted third signal may be provided as a second phase interpolator to interpolate the phase of the pair of seventh clocks by two degrees.

The control logic may receive a first signal to control the third signal and the adjusted third signal may be provided as a first phase interpolator to interpolate the phases of the first pair of clocks by two degrees.

The pair of second clocks includes an eighth clock and a ninth clock having a phase difference of 180 degrees and a pair of third clocks includes a tenth clock and an eleventh clock having a phase difference of 180 degrees .

If the eighth clock has a 90 DEG phase difference from the tenth clock and the ninth clock is interpolated to have a 90 DEG phase difference from the eleventh clock, the duty cycle of the fourth clock can be corrected to 50%.

The second signal changes the phases of a pair of the first clock and the pair of seventh clocks by 30 degrees and the third signal changes the phases of the pair of first clocks and the pair of seventh clocks by 28 degrees .

The pair of first clocks includes a pair of a twelfth clock and a pair of thirteenth clocks each having a phase difference of 30 DEG, the seventh clock includes a pair of a fourteenth clock having a phase difference of 30 DEG, A twelfth clock of a pair has a phase difference of 90 degrees with a pair of the fourteenth clocks and a pair of thirteenth clocks has a phase difference of 90 degrees with a pair of the fifteenth clocks have.

The twelfth clock of the pair includes the sixteenth clock and the seventeenth clock having the 180 degree phase difference, the pair of thirteenth clocks includes the eighteenth clock and the nineteenth clock having the 180 degree phase difference, The fourteenth clock of the twentieth clock may include a twentieth clock and the twenty-first clock having a 180-degree phase difference, and the pair of fifteenth clocks may include a twenty-second clock and a twenty-third clock having a 180-degree phase difference.

Other specific details of the invention are included in the detailed description and drawings.

The present invention is characterized in that the chip area and power consumption can be reduced by adding a phase interpolator and a duty cycle detector without using an additional duty cycle correction control loop to correct the duty cycle of the clock having the multiplication frequency.

1 is a block diagram illustrating a frequency multiplier according to an embodiment of the present invention.
Fig. 2 is a circuit diagram for explaining the duty cycle detector of Fig. 1; Fig.
3 is a flowchart illustrating an operation method of the frequency doubler of FIG.
4 is a conceptual diagram illustrating an error detection method of the duty cycle detector of FIG.
5 is a conceptual diagram illustrating a duty cycle correction method of the ninth clock of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "with another element when it is directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a frequency multiplier according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

1 is a block diagram illustrating a frequency multiplier according to an embodiment of the present invention. Fig. 2 is a circuit diagram for explaining the duty cycle detector of Fig. 1; Fig.

Referring to FIGS. 1 and 2, a frequency multiplier 1 according to an embodiment of the present invention may include a delay locked loop 100 and a duty cycle correction loop 200.

The delay locked loop 100 includes a delay line 110, a phase multiplexer unit 120, a first phase interpolator 140, a phase detector 150, A digital filter 160, and control logic 170. In one embodiment,

 The delay line 110 may be provided with a first clock CLK1 and a first clock bar CLKB1 from the outside. Here, the external may include, but is not limited to, for example, a user.

More specifically, the delay line 110 can generate a plurality of second clocks CLK2 by delaying the first clock CLK1 and the first clock bar CLKB1 provided from the outside using a buffer have. And may provide the generated plurality of second clocks (CLK2) to the phase multiplexer unit 120. [

The plurality of second clocks CLK2 are generated by delaying the clocks a0 to a5 generated by the delay of the first clock CLK1 and the clocks b0 to b5 generated by the delay of the first clock bar CLKB1 .

The clocks a0 to a5 generated by the delay of the first clock CLK1 have a phase difference of 30 degrees with each other and the clocks b0 to b5 generated by the delay of the first clock bar CLKB1 are also 30 degrees It can have a phase difference. The clocks a0 to a5 generated by the delay of the first clock CLK1 may have phase differences of 180 degrees with the clocks b0 to b5 generated by the delay of the first clock bar CLKB1. That is, for example, if the clocks a0 to a5 generated by the delay of the first clock CLK1 are 0 to 180 degrees, the clocks b0 to b5 generated by the delay of the first clock bar CLKB1 are 180 ° to 360 °.

The phase multiplexer unit 120 may include, for example, a first phase multiplexer 125 and a second phase multiplexer 130. The phase multiplexer unit 120 may also receive the sixth signal SIG6 from the control logic 170 and the sixth signal SIG6 may be provided to the first phase multiplexer 125, (SIG6a) and a sixth signal (SIG6b) provided to a second phase multiplexer (130).

The first phase multiplexer 125 may receive a plurality of second clocks CLK2 from the delay line 110 and output a third clock CLK3 and a fourth clock CLK4 having a phase difference of 30 degrees . And may provide the output of the third clock CLK3 and the fourth clock CLK4 to the first phase interpolator 140. [

More specifically, for example, the third clock CLK3 is generated by delaying the first clock bar CLKB1 by one clock a0 of the clocks a0 through a5 generated by the delay of the first clock CLK1 And one clock b0 of the generated clocks b0 to b5. Here, one of the clocks a0 to a5 generated by the delay of the first clock CLK1 and one of the clocks b0 to b5 generated by the delay of the first clock bar CLKB1, (b0) are differential clocks, they can have a 180 DEG phase difference from each other.

Similarly, for example, the fourth clock CLK4 is generated by one clock a1 of the clocks a0 to a5 generated by the delay of the first clock CLK1 and a delay of the first clock bar CLKB1 One of the clocks a0 to a5 generated by the delay of the first clock CLK1 and one clock a1 of the clocks CLK1 and CLK2 which may include one of the clocks b0 to b5, One of the clocks b0 to b5 generated by the delay of the clocks b1 to b5 is a differential clock and therefore can have a phase difference of 180 degrees with respect to each other.

One of the clocks a0 to a5 generated by the delay of the first clock CLK1 of the third clock CLK3 is delayed by the delay of the first clock CLK1 of the fourth clock CLK4 And a clock a1 of one of the clocks a0 to a5 generated by the clock generating circuit 30a. One of the clocks b0 to b5 generated by the delay of the first clock bar CLKB1 of the third clock CLK3 is delayed by the delay of the first clock bar CLKB1 of the fourth clock CLK4, And a clock (b1) of one of the clocks (b0 to b5) generated by the clock (b0).

The first phase multiplexer 125 may also receive the sixth signal SIG6a from the control logic 170. [ The sixth signal SIG6a may phase-shift the third clock CLK3 and the fourth clock CLK4 generated by the first phase multiplexer 125 by 30 degrees. A detailed description related to this will be given later.

The second phase multiplexer 130 may receive a plurality of second clocks CLK2 from the delay line 110 and output a fifth clock CLK5 and a sixth clock CLK6 having a phase difference of 30 degrees . And may provide the output fifth clock (CLK5) and sixth clock (CLK6) to the second phase interpolator (210).

Specifically, for example, the fifth clock CLK5 is generated by delaying one clock a3 and the first clock bar CLKB1 of the clocks a0 to a5 generated by the delay of the first clock CLK1 And one clock b3 of the generated clocks b0 to b5. Here, one clock (a3) of the clocks a0 to a5 generated by the delay of the first clock CLK1 and one of the clocks b0 to b5 generated by the delay of the first clock bar (CLKB1) (b3) are differential clocks, they can have a phase difference of 180 degrees from each other.

Likewise, for example, the sixth clock CLK6 is generated by the delay of one clock a4 and the first clock bar CLKB1 among the clocks a0 to a5 generated by the delay of the first clock CLK1 One of the clocks a0 to a5 generated by the delay of the first clock CLK1 and one clock a4 of the first clock bar CLKB1, which may include one of the clocks b0 to b5, One of the clocks b0 to b5 generated by the delay of the clock signal b4 is a differential clock and therefore can have a phase difference of 180 degrees with respect to each other.

One clock a3 of the clocks a0 to a5 generated by the delay of the first clock CLK1 of the fifth clock CLK5 is delayed by the delay of the first clock CLK1 of the sixth clock CLK6 And a clock (a4) of one of the clocks a0 to a5 generated by the clock generating circuit. One of the clocks b0 to b5 generated by the delay of the first clock bar CLKB1 of the fifth clock CLK5 is delayed by the delay of the first clock bar CLKB1 of the sixth clock CLK6, And a clock (b4) of one of the clocks (b0 to b5) generated by the clock (b0).

The second phase multiplexer 130 may also receive the sixth signal SIG6b from the control logic 170. [ The sixth signal SIG6b may phase-shift the fifth clock CLK5 and the sixth clock CLK6 generated by the second phase multiplexer 130 by 30 degrees. A detailed description related to this will be given later.

The third clock CLK3 described above may have a 90 DEG phase difference from the fifth clock CLK5 and the fourth clock CLK4 may have a 90 DEG phase difference from the sixth clock CLK6. For example, when the third clock CLK3 is 0 ° based on only the clocks a0 to a5 generated by the delay of the first clock CLK1, the fifth clock CLK5 is 90 ° And if the fourth clock CLK4 is 30 degrees, the sixth clock CLK6 may be 120 degrees.

The first phase interpolator 140 may output the seventh clock CLK7 by interpolating the phases of the third clock CLK3 and the fourth clock CLK4 provided from the first phase multiplexer 125. [

Specifically, the first phase interpolator 140 may interpolate the phases of the third clock CLK3 and the fourth clock CLK4 by 2 degrees. That is, when receiving the fifth signal SIG5a from the control logic 170, the phases of the third clock CLK3 and the fourth clock CLK4 are interpolated by 2 degrees. At this time, the first phase interpolator 140 outputs the phases of the third clock CLK3 and the fourth clock CLK4 by 2 degrees until the phases of the first clock CLK1 and the seventh clock CLK7 coincide with each other Interpolation can be performed. The fifth signal SIG5 may include a fifth signal SIG5a provided to the first phase interpolator 140 and a fifth signal SIG5b provided to the second phase interpolator 210. [

The final phase of the seventh clock CLK7 may be determined when the phase of the seventh clock CLK7 matches the phase of the first clock CLK1. For example, when the phases of the first clock CLK1 and the seventh clock CLK7 coincide with each other, the phase-interpolated third clock CLK3 has 2 degrees and 182 degrees, and the fourth clock CLK4 has The seventh clock CLK7 may have 17 degrees and 197 degrees which are intermediate values between the third clock CLK3 and the fourth clock CLK4.

The phase detector 150 may be coupled to the first phase interpolator 140.

More specifically, the phase detector 150 may compare the seventh clock CLK7 provided from the first phase interpolator 140 with the first clock CLK1 to output the first signal SIG1.

The seventh clock CLK7 may have two phases, as described above, but may be synthesized and compared in phase with the first clock CLK1 in the phase detector 150. If the phases of the first clock signal CLK1 and the seventh clock signal CLK7 are not identical to each other, the phase detector 150 outputs the first signal SIG1 and outputs the first signal SIG1 to the digital Filter 160 as shown in FIG. The first signal SIG1 is provided to the digital filter 160 and then to the first phase interpolator 140 via the control logic 170 so that the third clock CLK3 and the fourth clock CLK4 The phase can be increased or decreased by 2 degrees.

Of course, if the phases of the first clock CLK1 and the seventh clock CLK7 coincide with each other, the phase detector 150 may not output the first signal SIG1.

The digital filter 160 may be connected to the phase detector 150.

Specifically, the digital filter 160 may receive the first signal SIG1 from the phase detector 150 and provide it to the control logic 170. The digital filter 160 may be provided with a fourth signal SIG4 for controlling the operation of the delay locked loop 100 from the outside. Here, the fourth signal SIG4 is a signal provided to secure a sufficient bandwidth of the delay locked loop 100, and can control the operation of the delay locked loop 100, and the outside can be controlled by, for example, But is not limited thereto.

The digital filter 160 may receive the eighth signal SIG8 in addition to the first signal SIG1 and the eighth signal SIG8 may be provided from the duty cycle detector 230. [ The digital filter 160 may also provide the received eighth signal SIG8 to the control logic 170. [

The eighth signal SIG8 is a signal generated by the duty cycle detector 230 for correcting the duty cycles of the ninth clock CLK9 and the ninth clock bar CLKB9, and a detailed description thereof will be given later. In the present invention, the ninth clock bar (CLKB9) is substantially the same as the ninth clock (CLK9), its generating method and phase correcting method, and the ninth clock (CLK9) will be mainly described. Therefore, hereinafter, the ninth clock CLK9 will be described as an example.

The control logic 170 may receive the second signal SIG2 and the third signal SIG3 from the digital filter 160. [ The control logic 170 also provides the sixth signal SIG6 to the first phase multiplexer 125 and the second phase multiplexer 130 and the first phase interpolator 140 and the second phase interpolator 210, To provide a fifth signal SIG5.

Specifically, the second signal SIG2 provided by the control logic 170 is a signal for adjusting the fifth signal SIG5 provided to the first phase interpolator 140 and the second phase interpolator 210 And the third signal SIG3 are signals for adjusting the sixth signal SIG6 provided to the first phase multiplexer 125 and the second phase multiplexer 130. [ The fifth signal SIG5a provided to the first phase multiplexer 125 and the first phase interpolator 140 among the fifth signal SIG5 and the sixth signal SIG6 provided by the control logic 170, 6 signal SIG6a is provided until the phase of the first clock CLK1 coincides with the phase of the seventh clock CLK7 and the phase of the first clock CLK1 matches the phase of the seventh clock CLK7 And may be stored in a latch 235 of the duty cycle detector 230, which will be described later.

The duty cycle correction loop 200 may include, for example, a second phase interpolator 210, a clock edge combiner 220, and a duty cycle detector 230.

The second phase interpolator 210 may output the eighth clock CLK8 by interpolating the phases of the fifth clock CLK5 and the sixth clock CLK6 provided from the second phase multiplexer 130. [

Specifically, the second phase interpolator 210 may interpolate the phases of the fifth clock CLK5 and the sixth clock CLK6 by 2 degrees. That is, when receiving the fifth signal SIG5b from the control logic 170, the phases of the fifth clock CLK5 and the sixth clock CLK6 are interpolated by 2 degrees. The second phase interpolator 210 may interpolate the phases of the fifth clock CLK5 and the sixth clock CLK6 by 2 degrees until the duty cycle of the ninth clock CLK9 becomes 50% . The second phase interpolator 210 of the duty cycle correction loop 200 also determines whether the phase of the seventh clock CLK7 coincides with the phase of the first clock CLK1, lock). That is, the value of the eighth clock CLK8 can be corrected by the second phase interpolator 210 after the value of the seventh clock CLK7 is locked.

Here, the final phase of the eighth clock (CLK8) may be determined when the duty cycle of the ninth clock (CLK9) becomes 50%. That is, the final phase of the eighth clock CLK8 can be adjusted by the second phase multiplexer 130 and the second phase interpolator 210 until the duty cycle of the ninth clock CLK9 becomes 50% . The eighth clock CLK8 may include a pair of clocks having a phase difference of 180 degrees like the seventh clock CLK7 and the final phase of the eighth clock CLK8 may include a seventh clock CLK7 90 ° phase difference. For example, if the seventh clock CLK7 has a pair of clocks having phases of 0 DEG and 180 DEG, the eighth clock CLK8 has a pair of clocks having phases of 90 DEG and 270 DEG . A detailed description related to this will be given later.

The clock edge combiner 220 receives the seventh clock CLK7 from the first phase interpolator 140 and the eighth clock CLK8 from the second phase interpolator 210. [

Specifically, the clock edge combiner 220 uses the seventh clock signal CLK7 and the eighth clock signal CLK8 to generate the ninth and ninth clock signals CLK1 and CLK2 having a multiplication frequency (for example, twice the frequency of the first clock signal CLK1) It is possible to output the clock CLK9.

Referring to FIG. 2, the duty cycle detector 230 may be provided with a ninth clock CLK9 from the clock edge combiner 220. The duty cycle detector 230 may receive the ninth clock CLK9.

Specifically, the duty cycle detector 230 receives the seventh signal SIG7 for activating the duty cycle detector 230 and the ninth clock CLK9 and the ninth clock bar CLKB9 provided from the clock edge combiner 220 And outputs the eighth signal SIG8. That is, the duty cycle detector 230 analyzes the duty cycle of the ninth clock CLK9 and the ninth clock bar CLKB9 to determine the states of the phase increase signal INC and the phase decrease signal DEC, The state of the phase increase signal INC and the phase decrease signal DEC is stored in the latch 235 and then the phase of the eighth signal INC and the phase of the phase decrease signal DEC based on the phase increase signal INC and the phase decrease signal DEC stored in the latch 235, (SIG8).

The eighth signal SIG8 may be provided to the digital filter 160 as a signal that serves to correct the ninth clock CLK9 to have a duty cycle of 50%. That is, the eighth signal SIG8 may include a signal for interpolating the eighth clock CLK8 so that the eighth clock CLK8 may have a 90 DEG phase difference from the seventh clock CLK7. The eighth signal SIG8 includes a pair of signals, and each signal may include an eighth signal SIG8a indicating an UP signal and an eighth signal SIG8b indicating a DOWN signal, A detailed description thereof will be given later.

The frequency multiplier 1 according to an embodiment of the present invention adds a second phase interpolator 210 and a duty cycle detector 230 without using an additional duty cycle correction control loop to generate the third And the duty cycle of the clock CLK9 is corrected, whereby the chip area and power consumption can be reduced. In addition, since the duty cycle of the ninth clock bar (CLKB9) as well as the ninth clock (CLK9) can be corrected, the duty cycle error of the differential clock can be corrected.

Hereinafter, a method of operating the frequency multiplier according to an embodiment of the present invention will be described with reference to FIGS. 3 to 5. FIG.

3 is a flowchart illustrating an operation method of the frequency doubler of FIG. 4 is a conceptual diagram illustrating an error detection method of the duty cycle detector of FIG. 5 is a conceptual diagram illustrating a duty cycle correction method of the ninth clock of FIG.

Referring to FIGS. 1 and 3, the operation of the delay locked loop 100 starts (S300).

Specifically, the first clock CLK1 and the first clock bar CLKB1 are externally provided to the delay line 110 of the delay locked loop 100, so that the operation of the delay locked loop 100 can be started. The delay line 110 can generate a plurality of second clocks CLK2 by delaying the first clock CLK1 and the first clock bar CLKB1 provided from the outside using a buffer.

The first phase multiplexer 125 and the second phase multiplexer 130 provide a plurality of second clocks CLK2 (S310).

Specifically, the plurality of second clocks CLK2 provided to the first phase multiplexer 125 and the second phase multiplexer 130 are divided into the clocks a0 to a5 generated by the delay of the first clock CLK1, And clocks b0 to b5 generated by the delay of the clock bar CLKB1.

The first phase multiplexer 125 may receive a plurality of second clocks CLK2 from the delay line 110 and output a third clock CLK3 and a fourth clock CLK4 having a phase difference of 30 degrees The second phase multiplexer 130 receives a plurality of second clocks CLK2 from the delay line 110 and outputs a fifth clock CLK5 and a sixth clock CLK6 having a phase difference of 30 degrees have. A detailed description of the third to sixth clocks (CLK3 to CLK6) has been previously described and will be omitted.

The first phase interpolator 140 provides the third and fourth clocks CLK3 and CLK4 and the second phase interpolator 210 provides the fifth and sixth clocks CLK5 and CLK6 S320, .

Specifically, the first phase interpolator 140 may receive the third clock CLK3 and the fourth clock CLK4 from the first phase multiplexer 125, and the second phase interpolator 210 may receive the third clock CLK3 and the fourth clock CLK4 from the first phase multiplexer 125, And may receive the fifth clock CLK5 and the sixth clock CLK6 from the phase multiplexer 130. [ The first and second phase interpolators 210 may interpolate the phases of the provided clocks by 2 degrees. However, the second phase interpolator 210 does not operate simultaneously with the first phase interpolator 140 but operates when the duty cycle of the ninth clock CLK9 is corrected later.

The first phase interpolator 140 may output the seventh clock CLK7 by interpolating the phases of the third clock CLK3 and the fourth clock CLK4 by 2 degrees and output the seventh clock CLK7 May be provided to the phase detector 150. < RTI ID = 0.0 >

Here, the phase of the seventh clock CLK7, for example, if the phase-interpolated third clock CLK3 has 2 degrees and 182 degrees and the fourth clock CLK4 has 32 degrees and 212 degrees, The seventh clock CLK7 may have 17 DEG and 197 DEG which are intermediate values between the third clock CLK3 and the fourth clock CLK4.

The first clock CLK1 and the seventh clock CLK7 are compared (S330).

Specifically, the phase detector 150 compares the phase of the provided seventh clock CLK7 with the phase of the first clock CLK1 to determine whether the phases match with each other (S335). Here, when comparing the first clock CLK1 and the seventh clock CLK7, since there is only one phase of the first clock CLK1 as described above, the phase of the seventh clock CLK7 is one phase Can be synthesized and compared.

If the phases of the first clock CLK1 and the seventh clock CLK7 do not coincide with each other, the phase detector 150 outputs the first signal SIG1 and outputs the first signal SIG1 to the digital filter 160 . The first signal SIG1 is provided to the digital filter 160 and then to the first phase interpolator 140 via the control logic 170 so that the third clock CLK3 and the fourth clock CLK4 The phase can be increased or decreased by 2 degrees. The first signal SIG1 provided to the digital filter 160 is used to generate the second signal SIG2 associated with the first phase interpolator 140 and the second signal SIG2 provided to the control logic 170 SIG2 may be used to adjust the fifth signal SIG5a provided to the first phase interpolator 140. [ That is, the first signal SIG1 may be used to control the fifth signal SIG5a, which is consequently supplied to the first phase interpolator 140. [

And the phases of the third clock CLK3 and the fourth clock CLK4 are interpolated (S340).

Specifically, the phase of the third clock CLK3 and the phase of the fourth clock CLK4 may be increased or decreased by 2 degrees by the fifth signal SIG5a provided to the first phase interpolator 140. [ The maximum and minimum phases that can be interpolated by the second phase interpolator 210 as well as the first phase interpolator 140 may correspond to + 28 ° and -28 °. In other words, the fifth signal SIG5a has a value from 0 to 14, and the phases of the third clock CLK3 and the fourth clock CLK4 can be interpolated by + 28 ° and -28 ° when the first signal SIG5a is 1 or 13 have.

The control logic 170 provides the sixth signal SIG6a to the first phase multiplexer 125 to generate the third clock CLK3 if the fifth signal SIG5a has a value of 0 or 14, And the phase of the fourth clock CLK4 by 30 DEG (S350). Here, the sixth signal SIG6a is a signal generated using the third signal SIG3 provided from the digital filter 160. [ At this time, the control logic 170 may also provide the sixth signal SIG6b to the second phase multiplexer 130 to move the phase of the fifth clock CLK5 and the sixth clock CLK6 by 30 degrees. The reason for providing the sixth signal SIG6b to the second phase multiplexer 130 is that the fifth clock CLK5 and the sixth clock CLK6 are connected to the third clock CLK3 and the fourth clock CLK4, In order to maintain the phase difference of the frequency.

The phases of the third clock CLK3 and the fourth clock CLK4 are shifted by 30 degrees and then the phase of the first clock CLK1 and the seventh clock CLK7 is returned to the phase comparing step S335, ) And the seventh clock (CLK7).

Of course, if the fifth signal SIG5a does not have a value of 0 or 14, the phase of the third clock CLK3 and the phase of the fourth clock CLK4 are shifted by 30 degrees, The process returns to the comparison step S335 of the seventh clock CLK7 to compare the phases of the first clock CLK1 and the seventh clock CLK7.

The fifth signal SIG5a and the sixth signal SIG6a at the same time are stored in the latch 235 of the duty cycle detector 230 if the phases of the first clock CLK1 and the seventh clock CLK7 coincide with each other And locks the delay locked loop 100 (S355).

Specifically, the delay locked loop 100 is locked and the fifth signal SIG5a and the sixth signal SIG6a when the phases of the first clock CLK1 and the seventh clock CLK7 coincide with each other through the latch 235 The phase of the seventh clock CLK7 provided to the clock edge combiner 220 can be determined.

The determined seventh clock CLK7 is provided to the clock edge combiner 220 and the fifth clock CLK5 and the sixth clock CLK6 are supplied to the eighth clock CLK8 through the second phase interpolator 210 And may be provided to the clock edge combiner 220.

In the case of the eighth clock CLK8, since the second phase interpolator 210 is locked before the delay locked loop 100 is locked, the phase is not interpolated to the clock edge combiner 220 Can be provided.

And generates the ninth clock CLK9 (S360).

Specifically, the clock edge combiner 220 uses the seventh clock signal CLK7 and the eighth clock signal CLK8 to generate the ninth and ninth clock signals CLK1 and CLK2 having a multiplication frequency (for example, twice the frequency of the first clock signal CLK1) The clock CLK9 and the ninth clock bar CLKB9. The ninth clock CLK9 and the ninth clock bar CLKB9 may be provided to the duty cycle detector 230 to correct the duty cycles of the ninth clock CLK9 and the ninth clock bar CLKB9 generated . In the present invention, the ninth clock bar (CLKB9) is substantially the same as the ninth clock (CLK9), its generating method and phase correcting method, and the ninth clock (CLK9) will be mainly described. Therefore, hereinafter, the ninth clock CLK9 will be described as an example.

The operation of the duty cycle detector 230 starts (S370).

Specifically, when the ninth clock CLK9 is provided to the duty cycle detector 230, a seventh signal SIG7 from the outside is supplied to the duty cycle detector 230 so that the duty cycle detector 230 can be activated .

Referring to FIGS. 1 and 4, the seventh signal SIG7 having a 1/64 frequency division period of the ninth clock CLK9 having a multiplication frequency is used for an evaluation period of the duty cycle of the ninth clock CLK9 And the precharge period can be controlled. Here, the evaluation period means a period in which the duty cycle detector 230 evaluates whether the duty cycle of the ninth clock (CLK9) has a duty cycle of 50%.

The phase increase signal INC and the phase decrease signal DEC of the duty cycle detector 230 are reduced to the logic threshold voltage VLT of the latch 235 and then the ninth clock CLK9 and the ninth clock bar CLKB9 And can be transited to a high level or a low level by the analysis result of the continuous duty cycle. In Fig. 4, the phase increase signal INC transitions to a low level at the end of the evaluation period, and the phase decrease signal DEC transitions to a high level at the end of the evaluation period. The latch 235 holds the phase increase signal INC and the phase decrease signal DEC at the end of the evaluation period. In this case, since the phase decrease signal DEC is at a high level, It can be seen that the device 210 reduces the phase of the fifth clock CLK5 and the sixth clock CLK6 by 2 degrees. Even if the ninth clock CLK9 and the ninth clock bar CLKB9 are input during the precharge period, there is no change in the output of the duty cycle detector 230 and the phase increase signal INC and the phase decrease signal DEC are set to high Level. The phase increase signal INC determines the state of the eighth signal SIG8a corresponding to the UP signal and the phase decrease signal DEC can determine the state of the eighth signal SIG8b corresponding to the DOWN signal. The eighth signal SIG8 determined by the phase increase signal INC and the phase decrease signal DEC is also provided to the digital filter 160 and consequently affects the phase interpolation operation of the second phase interpolator 210 It is to be given.

Referring again to FIGS. 1 and 3, it is determined whether the duty cycle of the ninth clock CLK9 is 50% (S375).

Specifically, when the duty cycle of the ninth clock CLK9 is 50%, the operation of the duty cycle detector 230 ends (S395). Here, if the duty cycle of the ninth clock CLK9 is 50%, for example, if the seventh clock CLK7 has a pair of clocks having phases of 0 and 180, the eighth clock CLK8 ) May have a pair of clocks with phases of 90 [deg.] And 270 [deg.].

If the duty cycle of the ninth clock CLK9 is not 50%, the duty cycle detector 230 may generate and provide the eighth signal SIG8 to the digital filter 160 according to the process described above .

The second signal SIG2 associated with the second phase interpolator 210 may be generated by the eighth signal SIG8 provided to the digital filter 160. [ The second signal SIG2 provided to the control logic 170 may also be used to adjust the fifth signal SIG5b provided to the second phase interpolator 210. [ That is, the eighth signal SIG8 may be used to control the fifth signal SIG5b provided to the second phase interpolator 210 as a result.

And interpolates the phases of the fifth clock CLK5 and the sixth clock (S380).

Specifically, the phase of the fifth clock CLK5 and the phase of the sixth clock CLK6 may be increased or decreased by 2 degrees by the fifth signal SIG5b provided to the second phase interpolator 210. [ As described above, the fifth signal SIG5b has a value ranging from 0 to 14, and the phases of the fifth clock signal CLK5 and the sixth clock signal CLK6 are + 28 ° and -28 ° when the signal is 1 or 13, Interpolation can be performed.

Referring to FIG. 5, the eighth clock (CLK8) output by interpolating the phase by the second phase interpolator (210) can be checked. 5, the phase of one eighth clock (CLK8a) is increased and the phase of the other eighth clock (CLK8b) is decreased. As a result, the duty cycle of the ninth clock (CLK9) It can be confirmed that it is corrected to 50%. At this time, since the seventh clock (CLK7) is locked, it can be confirmed that there is no change.

If the fifth signal SIG5b has a value of 0 or 14 at step S385, the control logic 170 provides the sixth signal SIG6b to the second phase multiplexer 130 to generate the fifth clock signal CLK5, And the phase of the sixth clock CLK6 by 30 DEG (S390). Here, the sixth signal SIG6b is a signal generated using the third signal SIG3 provided from the digital filter 160. [ At this time, the control logic 170 does not provide the sixth signal SIG6a to the first phase multiplexer 125 because the sixth signal SIG6a provided to the first phase multiplexer 125 is locked .

The phase of the fifth clock signal CLK5 and the sixth clock signal CLK6 is shifted by 30 degrees and then the process returns to step S375 in which it is determined whether the duty cycle of the ninth clock signal CLK9 is 50% CLK9). ≪ / RTI >

Of course, if the fifth signal SIG5b does not have a value of 0 or 14, the phase of the fifth clock signal CLK5 and the phase of the sixth clock signal CLK6 are shifted by 30 degrees, The process returns to step S375 in which it is checked whether the duty cycle is 50%, thereby confirming the duty cycle of the ninth clock CLK9.

If the duty cycle of the ninth clock (CLK9) is 50%, the operation of the duty cycle detector 230 ends (S395).

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: delay locked loop 110: delay line
125: first phase multiplexer 130: second phase multiplexer
140: first phase interpolator 150: phase detector
160: digital filter 170: control logic
200: duty cycle correction loop 210: second phase interpolator
220: clock edge combiner 230: duty cycle detector

Claims (12)

Delay locked loop; And
A duty cycle correction loop coupled to the delay locked loop and including a first phase interpolator, a clocked edge coupler, and a duty cycle detector,
Wherein the first phase interpolator is provided with a pair of first clocks from the delay locked loop,
Wherein the clock edge combiner receives a pair of second clocks and a pair of third clocks each of which is phase-interpolated from the first phase interpolator and the delay locked loop, and outputs a fourth clock,
Wherein the duty cycle detector outputs a first signal for correcting the duty cycle of the fourth clock provided from the clock edge combiner,
Wherein the first signal is provided to the delay locked loop,
The fourth clock having a multiplication frequency,
Wherein the delay locked loop includes a phase multiplexer unit, the phase multiplexer unit includes a first phase multiplexer that receives a plurality of clocks and outputs the pair of first clocks having a phase difference of 30 degrees, and a second phase multiplexer that provides the plurality of clocks And a second phase multiplexer having a 30 DEG phase difference and outputting a pair of clocks different from the pair of first clocks. The method according to claim 1,
Wherein the delay locked loop comprises control logic, the phase multiplexer unit receiving a second signal from the control logic, a second phase interpolator receiving a third signal from the control logic, a fifth clock from the outside, And a delay line for delaying the first clock by a predetermined number of times and providing a plurality of sixth clocks to the phase multiplexer unit,
Wherein the first phase multiplexer receives the plurality of sixth clocks and outputs the pair of first clocks having a phase difference of 30 degrees,
Wherein the second phase multiplexer receives the plurality of sixth clocks and outputs a pair of seventh clocks having a phase difference of 30 degrees different from the pair of first clocks. 3. The method of claim 2,
Wherein the first phase interpolator interpolates the phases of the pair of first clocks provided from the first phase multiplexer to output the pair of second clocks,
Wherein the second phase interpolator interpolates the phase of the seventh clock of the pair provided from the second phase multiplexer and outputs the pair of third clocks. The method of claim 3,
Wherein the delay locked loop further comprises a phase detector connected to the second phase interpolator and a digital filter connected to the phase detector,
Wherein the phase detector compares the pair of seventh clocks provided from the second phase interpolator with the fifth clock to output a fourth signal,
Wherein the digital filter receives the fourth signal from the phase detector and provides the fourth signal to the control logic. 5. The method of claim 4,
The digital filter receives a fifth signal from the outside,
And the fifth signal controls the operation of the delay locked loop. 5. The method of claim 4,
The control logic using the fourth signal to adjust the third signal,
And the adjusted third signal is provided to the second phase interpolator to interpolate the phases of the pair of seventh clocks by 2 degrees. The method of claim 3,
Wherein the control logic controls the third signal by receiving the first signal,
And the adjusted third signal is provided to the first phase interpolator to interpolate the phases of the pair of first clocks in two degrees. The method of claim 3,
The pair of second clocks include an eighth clock and a ninth clock having a phase difference of 180 degrees and the pair of third clocks include a tenth and eleventh clocks having a phase difference of 180 degrees Frequency multiplier. 9. The method of claim 8,
When the eighth clock has a phase difference of 90 degrees from the tenth clock and the ninth clock is interpolated to have a 90 degree phase difference from the eleventh clock, the duty cycle of the fourth clock is corrected to 50% Frequency multiplier. 3. The method of claim 2,
Wherein the second signal changes phases of the pair of first clocks and the pair of seventh clocks by 30 degrees,
And the third signal changes the phases of the pair of first clocks and the pair of seventh clocks up to 28 degrees. 3. The method of claim 2,
Wherein the pair of first clocks includes a pair of a twelfth clock and a pair of thirteenth clocks each having a phase difference of 30 占 and the seventh clock includes a pair of a fourteenth clock having a phase difference of 30 占 and The fifteenth clock of the pair,
Wherein the twelfth clock of the pair has a phase difference of 90 占 from the pair of the fourteenth clocks and the pair of thirteenth clocks has a phase difference of 90 占 from the pair of the fifteenth clocks. 12. The method of claim 11,
Wherein the twelfth clock of the pair includes a sixteenth clock and a seventeenth clock having a phase difference of 180 degrees,
Wherein the pair of thirteenth clocks includes an eighteenth clock and a nineteenth clock having a 180 DEG phase difference,
Wherein the pair of the fourteenth clocks includes a twentieth clock and a twenty-first clock having a phase difference of 180 degrees,
Wherein the pair of the fifteenth clocks includes a twenty-second clock and a twenty-third clock having a 180-degree phase difference.

Images