KR101567834B1 - Clock and data recovery circuit and recovery method using the same - Google Patents

Abstract

The present invention relates to a clock, a data recovery circuit, and a recovery method which recovery serial data from a serial data signal received by including a clock. The present invention detects a period of a clock signal inputted from the outside, and separately configures a circuit unit converting parallel data on a rapid period, and a slow period, thereby having an effect of increasing bandwidths of the clock and the data recovery circuit.

Description

CLOCK AND DATA RECOVERY CIRCUIT AND RECOVERY METHOD USING THE SAME

The present invention relates to a clock and data restoration circuit and a restoration method for recovering serial data from a received serial data signal including a clock. More specifically, the present invention relates to a clock and data restoration circuit and a restoration method for determining a period of a received serial data signal, The present invention relates to a clock and data restoration circuit and a restoration method using the FSM and the finite state machine (FSM).

Recently, with the development of communication technology, the data transmission speed has increased from tens to hundreds of gigabits per second. Generally, in such high-speed communication, a serial interface device is used rather than a parallel interface device. This is because the maximum transmission distance and the transmission speed of the parallel interface device are limited due to crosstalk, noise coupling, etc. between respective bits of data to be transmitted and received.

The serial interface device converts the data in the parallel format into the serial format, and transmits the data in the serial format. Unlike the parallel interface device that simultaneously transmits the clock and the data, the serial interface device transmits only the data signal including the clock information. This is because the unit interval of data in the high-speed communication is very short, usually 1 ns or less, and the transmission distance is long, so that if the clock and data are simultaneously transmitted, skew can be generated in the clock and data at the receiving end . Therefore, the transmitting end converts the data into the data including the clock information, and the receiving end extracts the clock and data from the received data. Here, performing the function of extracting the clock and data from the data signal including the clock information is referred to as a data restoration device or a serial link.

Generally, the serial link can be implemented by an oversampling structure, a tracking structure, a phase interpolation structure, and the like.

The restoration process of the data by the oversampling structure is as follows. First, a receiving terminal generates a plurality of sampling clocks, and latches the received serial data at predetermined intervals using the plurality of sampling clocks. Detects a transition section from the latched data, and outputs, as valid data, data farthest from the transition section of the latched data. Here, the number of the sampling clocks may be variously changed depending on how many data are to be latched from one data.

The process of restoring the data by the tracking structure is as follows. First, two sampling clocks including a clock whose position is fixed at the center of data at the receiving end and a clock which follows the edge of the data are generated. Latches the received data at regular intervals using two sampling clocks, and detects the data latched by the fixed sampling clock as valid data.

The restoration process of the data by the phase interpolator structure is as follows. First, a receiving end generates a plurality of sampling clocks and a tracking clock that tracks edges of data between sampling clocks. Data received using a plurality of sampling clocks and a follow-up clock is latched at predetermined intervals, and data at a farthest position in a transition interval detected by the follow-up clock is detected as effective data.

1 is a block diagram of a serial link according to the conventional phase interpolator structure. A serial link having a phase interpolator is composed of a sampler that receives input serial data by 1 bit after readjusting the clock according to a clock adjustment signal (iCLK, qCLK), and a shift register, A finite state machine (FSM) that generates a phase increase signal (up signal) and a phase decrease signal (down signal) after receiving data from the deserializer, Phase clock signals iCLKref and qCLKref inputted from a phase locked loop (PLL) using phase up / down signals (up / down signals) outputted from the FSM, , qCLK). Here, feedback inputs and input clocks are used as inputs of the frequency phase detector constituting the PLL. In high-speed serial transmission, there are (1) a method of sending an input clock to input data and (2) a method of sending only data without sending a clock. In the former case, the input clock is partially corrected and used as an input to the phase locked loop. In the latter case, the clock is recovered from the data and the recovered clock is used as the input to the phase locked loop.

By continuously performing the phase interpolation control, the clock and data recovery circuit (CDR) can sample and recover the input serial data at the optimum point. Since the edges of the input serial data can vary in frequency, the clock and data recovery circuitry must be able to change the sampling point accordingly. This is called the CDR loop bandwidth and can be expressed by Equation (1).

Here, Kp is a phase detector gain,

Kpa: Phase Adjuster Gain,

T: FSM operating period (Operating Period)

According to Equation (1), it can be seen that the CDR loop bandwidth is dependent on the FSM operation period, and as the data rate is lowered, the loop bandwidth of the clock and data recovery circuit is also lowered and satisfies the performance required in various high-speed serial data transmission standards It can be seen that there is no number. For example, in the case of an HDMI signal, data is transmitted at a data transfer rate of about 250 MBPS when VGA image data is transmitted, and about 3.4 GBPS when full HD image data is transmitted. In sum, bandwidth limitations exist in the case of HDMI signal transmission line to process 250MBPS ~ 3.4GBPS rate with one clock and data recovery circuit.

Patent Document 1: Korean Patent Laid-Open No. 10-2004-0075243 (published on Aug. 27, 2004)

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a clock and data recovery circuit for processing data signals according to a low data rate and a high data rate, And to provide a clock and data restoration circuit and a restoration method that solve the above problems.

The above object of the present invention is achieved by a clock and data restoration circuit for recovering a clock and data by using a phase locked loop after receiving a clock signal including a clock and data serially and inputting the clock signal into a 1-bit iDATA and a qDATA A first serial-to-parallel converter for collecting 1-bit data input from the data sampler and then outputting 10-bit parallel I / Q data; and a 10-bit parallel I A first finite state machine for inputting / Q data to determine a final state and outputting a phase control signal, and a second finite state machine for collecting 1-bit data input from the data sampler, Parallel I / Q data input from the second serializer, and a final state is determined by inputting N parallel I / Q data input from the second serializer A second finite state machine for outputting a phase control signal, a phase locked loop for receiving a reference clock from the phase locked loop and receiving a phase control signal output from one selected from the first finite state machine or the second finite state machine And a phase interpolator for providing the corrected i-clock and q-clock to the data sampler.

It is still another object of the present invention to provide a clock and data recovery method for restoring a clock and data by using a phase locked loop after receiving a clock signal including a clock and data serially, And qDATA; a second stage of collecting 1-bit data input from the first stage and outputting 10-bit parallel I / Q data after the first stage; A third step of determining a final state by inputting 10-bit parallel I / Q data and outputting a phase control signal, a third step of collecting 1-bit data input from the first step, Bit parallel I / Q data input from the first stage and the N parallel I / Q data input from the second stage, and outputs a phase control signal Step 3-2, and step 3-2, And a phase control signal output from one of the 3-1st and 3-2steps is input to the i-th clock and the q-clock, which are used in the sampling step of the first step, And a fourth step of outputting the clock and data.

According to the clock and data restoring circuit and the restoring method according to the present invention, the input data rate is discriminated, and the data signal having the low data rate and the data signal having the high data rate are processed using the separate serializer and FSM By implementing the clock and data restoration circuit, it is possible to solve the problem caused by lack of bandwidth.

1 is a block diagram of a serial link by a conventional phase interpolator structure;
2 is a block diagram of a serial link having a clock and data recovery circuit according to an embodiment of the present invention;

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

2 is a block diagram of a serial link including a clock and data recovery circuit according to an embodiment of the present invention. A serial link according to the present invention includes a buffer, a data sampler, a first serializer, a first FSM, a second serializer, a second FSM, a multiplexer, a phase interpolator, a PLL, MUX), and an input data rate discriminator.

The buffer is a circuit block for temporarily storing input clock data, and the data sampler outputs 1-bit data (iDATA, qDATA) according to an in phase clock (iCLK) and a quadrature clock (qCLK) input from a phase interpolator. ). The first serial-to-parallel converter is composed of a plurality of flip-flops, and is a circuit block that stores serial data input from a data sampler and outputs 10-bit parallel data (I / Q data 10-bit). Since the first serializer needs to process 10-bit data into one clock, it operates with a clock (CLKdiv10) that divides the clock used by the data sampler by ten. The second serial-to-parallel converter is composed of a plurality of flip-flops, and is a circuit block for storing serial data input from the data sampler and outputting the serial data as N-bit parallel data (I / Q data N-bit). Where N is a natural number less than 10. Since the second serializer needs to process N-bit data into one clock, it operates by a clock (CLK divN) that divides the clock used by the data sampler by N. The first FSM and the second FSM are connected to the first serializer and the second serializer, respectively, and discriminate the current state using input I / Q data and then output a phase control signal for correcting iCLK and qCLK. Block. A phase locked loop (PLL) is a constituent block for generating a reference clock composed of fixed iCLK ref and qCLK ref from input data.

The data rate discriminator is a circuit block for discriminating a data rate of externally inputted data and discriminating whether data having a high data rate is input or data having a low data rate is inputted. The data rate determination can be implemented by various known techniques. In one embodiment, the reference clock, which is composed of iCLK ref and qCLK ref output from the phase locked loop, and iCLK and qCLK output from the phase interpolator, And determines whether the clock data has a high data rate or a low data rate and then outputs the result. In the case where clock data having a fast period operating at 3.5 GHz, such as Full HD, is input, the serial link according to the present invention is converted into 10-bit parallel data by a first serializer and processed through a first FSM Selected by the MUX, and operates in such a way that the first FSM and phase interpolator are coupled. Also, in the case where the data input from the outside is data having a low data rate of 250 MHz such as a VGA signal, the serial link according to the present invention is data-processed through the second serializer and the second FSM and then selected by the MUX, A phase interpolator is connected. The MUX selects one of a phase control signal output from the first FSM or a phase control signal output from the second FSM, and inputs the output to the phase interpolator using the output of the clock period discriminator as a control signal.

Accordingly, the present invention provides a clock and data recovery method comprising a first step of detecting a data rate of input data, a second step of determining whether a detected data rate is greater than or less than a reference value, Bit parallel data using the first serializer and the first FSM, and when the data rate is determined to be slow, the second serializer and the second FSM are used to output parallel data of N bits smaller than 10 And the third step. A fourth step of outputting a phase control signal output from any one FSM selected from a first FSM or a second FSM through a MUX to a phase interpolator; and a phase interpolator for outputting a phase control signal, A fifth step of outputting iCLK and qCLK using a reference clock input from the PLL, and a sixth step of sampling data by extracting one bit of data input according to iCLK and qCLK.

In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present disclosure rather unclear.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In addition, the components shown in the embodiments of the present invention are shown independently to represent different characteristic functions, which does not mean that each component is composed of separate hardware or software constituent units. That is, each constituent unit is included in each constituent unit for convenience of explanation, and at least two constituent units of the constituent units may be combined to form one constituent unit, or one constituent unit may be divided into a plurality of constituent units to perform a function. The integrated embodiments and separate embodiments of the components are also included within the scope of the present invention, unless they depart from the essence of the present invention.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Claims (6)

There is provided a clock and data restoration circuit for restoring a clock and data by using a phase locked loop after receiving a clock signal including a clock and data,
A data sampler for sampling an input clock signal with one bit of iDATA and qDATA,
A first serial-to-parallel converter for collecting 1-bit data input from the data sampler and outputting 10-bit parallel I / Q data;
A first finite state machine for inputting 10-bit parallel I / Q data input from the first serial-to-parallel converter to determine a final state and outputting a phase control signal,
A second serial-parallel converter for collecting 1-bit data input from the data sampler and outputting N-bit parallel I / Q data that is a natural number less than 10;
A second finite state machine for inputting N parallel I / Q data input from the second serial-to-parallel converter to determine a final state and outputting a phase control signal,
Receiving a reference clock from the phase locked loop and inputting a phase control signal output from one selected from the first finite state machine or the second finite state machine to provide the corrected i clock and q clock to the data sampler And a phase interpolator for performing a phase interpolator operation on the clock signal.
The method according to claim 1,
And a clock period discriminator for detecting whether the detected period is a long period or a short period which is longer than the reference period value after detecting the period of the clock signal input from the outside A clock and data recovery circuit.
3. The method of claim 2,
And a phase control signal output from the first finite state machine or controlled by an output of the clock period discriminator between the first finite state machine and the second finite state machine and the phase interpolator, Further comprising a multiplexer for selecting one of the output clock signals and the output phase control signals.
delete CLAIMS 1. A method of restoring a clock and data by receiving a clock signal including a clock and data serially and then restoring the clock and data using a phase locked loop,
A first step of sampling an input clock signal with one bit of iDATA and qDATA,
A second step of collecting 1-bit data input from the first step and outputting 10-bit parallel I / Q data,
A 3-1 step of inputting 10-bit parallel I / Q data input from the step 2-1 to determine a final state and outputting a phase control signal;
A second step of collecting 1-bit data input from the first step and outputting N-bit parallel I / Q data that is a natural number less than 10,
A 3-2 step of inputting N parallel I / Q data input from the step 2-2 to determine a final state and outputting a phase control signal;
Wherein the reference clock is input from the phase locked loop and the phase control signal output from one phase selected from the phase 3-1 or phase 3-2 is input to an i- And a fourth step of outputting the clock and the q clock.
6. The method of claim 5,
Further comprising a fifth step of detecting a period of the clock signal input from the outside and then outputting whether the detected period is a long period or a short period shorter than the reference period value, Wherein the fifth step is performed irrespective of the other steps and the order.

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