KR101565584B1 - Method and Apparatus for Transmitting Data Based on SPI Communication - Google Patents

Abstract

An apparatus and method for data transmission based on SPI communication are disclosed.
According to an aspect of the present invention, there is provided a method for a slave device to detect an SPI operation mode, comprising: determining CPOL using CLK and CSB received via an SPI bus; Determining a CPHASE (Clock Phase) based on the determined CPOL and the determined edge of the CLK, comparing the detected signal pattern with the signal pattern of the master device, determining the edge of the CLK used by the master device for MOSI signal transmission, The method comprising:

Description

FIELD OF THE INVENTION [0001] The present invention relates to an apparatus and method for transmitting data based on SPI communication,

The present embodiment relates to an apparatus and method for detecting a clock polarity and a clock phase for determining a communication method in SPI communication.

The contents described in this section merely provide background information on the present embodiment and do not constitute the prior art.

FIG. 1 is a diagram illustrating a configuration of a conventional slave device in a serial peripheral interface (SPI) communication. In SPI communication, data transmission / reception is performed by four signals. The Master Out Slave In (MOSI) signal is a signal generated by the master and received by the slave. The master in slave out (MISO) signal is a signal generated by the slave and received by the master. CLK (Clock) 110 is a signal synchronized to transfer data between a master and a slave generated by a master. A CSB (Chip Select Bar) 140 is a signal generated by the master and selecting peripheral devices or slave devices. When the CSB signal is low, the slave is activated.

Another required signal value is a clock polarity (CPOL) 150 and a clock phase (CPHASE) 160. These signals are the signals that are sent from the master to determine the edge of the clock signal to be sampled. Since CPOL and CPHASE have 0 or 1 value respectively, when the clock signal is synchronized to perform data transmission, there are four methods of transmitting according to whether CPOL and CPHASE are 0 or 1 respectively. Therefore, it is essential to know CPOL and CPHASE to determine transmission method.

The SPI decoding unit 170 determines the SPI operation mode using the CPOL and CPHASE values received from the master, and decodes a signal transmitted from the master according to the determined operation mode.

There is a problem in that, in addition to the pins for receiving four signals required for transmitting and receiving data, the slave uses two additional pins to receive the CPOL and CPHASE signals.

The main purpose of this embodiment is to provide an apparatus and method for detecting CPOL and CPHASE without using additional pins for receiving CPOL and CPHASE signals from the master.

According to an aspect of the present invention, there is provided a data communication system including an SPI bus, a master device connected to the SPI bus, and one or more slave devices connected to the SPI bus, And determines a CPOL and CPHASE based on at least a part of CLK, CSB, and MOSI signals received through the SPI bus in determining an SPI communication mode to be used.

According to another aspect of the present invention, there is provided a method for a slave device to detect an SPI communication mode, comprising: determining a CPOL using CLK and CSB received via an SPI bus; Determining a CPHASE based on the determined CPOL and an edge of the determined CLK; comparing the signal pattern with a predetermined signal pattern to determine an edge of the CLK used by the master device for transmitting the MOSI signal; Detection method.

As described above, according to the present embodiment, it is possible to detect and detect the CPOL and the CPHASE without receiving a separate signal for knowing the CPOL and the CPHASE, thereby preventing the use of the pin for receiving the CPOL and CPHASE signals, It is effective to prevent waste.

1 is a diagram illustrating an exemplary configuration of a conventional slave device in SPI communication.
2 is a configuration diagram for performing SPI communication between a master and a slave.
3 is a timing diagram showing four SPI operation modes according to CPOL and CPHASE, respectively.
4 is an exemplary diagram illustrating a configuration of a slave device according to an embodiment of the present invention in SPI communication.
5 is a configuration diagram of an SPI mode detecting unit according to an embodiment of the present invention.
6 is a flowchart illustrating a method of detecting CPOL and CPHASE according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. Throughout the specification, when an element is referred to as being "comprising" or "comprising", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise . In addition, '... Quot ;, " part, " and the like denote a unit for processing at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software.

2 shows a configuration for performing SPI communication between the master 210 and the slaves 220 (a), 220 (b), and 220 (c).

 Serial Peripheral Interconnect (SPI) communication is a synchronous communication standard developed by Motorola that enables full duplex communication. The devices operate in master-slave mode and the master outputs the clock for synchronization. Each SPI slave device operates only when the CSB is activated. Thus, the master can drive two or more slave devices using the method of sending CSB to slave devices over multiple CSB buses and selecting only one slave device at a time

The four buses shown in FIG. 2 are buses for transmitting and receiving data defined in the SPI communication, and the signals transmitted from the four buses are as follows. First, CLK is a synchronization clock output from the master 210. [ It may be called SCLK or SCK depending on the manufacturer. Second, the CSB is a signal that the master 210 outputs to select the slaves 220 (a), 220 (b), and 220 (c). This may be referred to as SS, CS, CSN or STE depending on the manufacturer. Third, MOSI is a signal for sending information to the slaves 220 (a), 220 (b), and 220 (c) at the output of the master 210. It may also be called SDI, SI, DI, or DIN depending on the manufacturer. Fourth, the MISO is a signal for the master 210 to receive the information of the slave with the output of the slaves 220 (a), 220 (b), and 220 (c). It may be called SDO, DO, SO, or DOUT depending on the manufacturer.

Generally, slaves are enabled only while CSB is low. In order to communicate, the master first outputs a low state to the CSB to activate the corresponding slave. The master then outputs a CLK for synchronization to the pin of the clock signal, which sends out the data to the bus of the MOSI signal bit by bit. At the same time, the master reads the MISO signal bit by bit according to the CLK it outputs. In other words, the master outputs the data to the pin of the MOSI signal in accordance with its output CLK, and at the same time receives the data to the bus of the MISO signal. SPI communication always carries out bidirectional communication. The received data may be a meaningful value or a meaningless value depending on the situation. Similarly, data is output to the bus of the MOSI signal while receiving the input of the MISO signal to the CLK in order to read the data of the slave.

Normally, SPI communication proceeds in 8-bit units, but it can be 12 bits or 16 bits or more in length. There is no specification for bit transmission order. The transmission of data may start at the most significant bit (MSB) or may start at the least significant bit (LSB). The SPI specification does not specify this part, but is determined by the commitment between the master and the slave.

When data is transmitted, there is a single-byte mode in which data is transmitted per unit of data, and a multiple-byte mode in which data is continuously transmitted. In the single-byte method, the CSB should be transmitted every time one unit of data is transmitted. However, the multi-byte method maintains this state until all the data is transmitted after setting the CSB to a low state. CSB can be changed to a high state.

Another factor is CPOL and CPHASE. These are important factors in determining the type of clock signal used in SPI communications. CPOL is divided according to the base value of CLK. Here, the default value means the value of CLK when the SPI bus is not activated, that is, when the CSB is not kept in a low state. If CPOL is 0, the default value of CLK is 0. If CPOL is 1, the default value of CLK is 1. CPHASE depends on when it is time to sample the data. Regardless of whether the edge of the clock is a rising edge or a falling edge, data is sampled at the edge of the first clock if CPHASE is 0 and data is sampled at the edge of the second clock when CPHASE is 1, Lt; / RTI > Since CPOL and CPHASE have 0 and 1, respectively, they have four SPI operation modes according to CPOL and CPHASE values.

3 is a timing diagram illustrating four SPI modes of operation.

In practice, sampling is performed every cycle of the CLK, but in FIG. 3, only sampling 310 in one cycle is illustrated for convenience. 3 (a) is a timing diagram showing a case where CPOL and CPHASE are 0, respectively. Since CPOL is 0, the clock has a default value of 0, so CLK occurs from 0. Since CPHASE is 0, it is sampled at the edge of the first clock, so data is sampled at the rising edge. Then, data is transmitted when the falling edge. FIG. 3 (b) is a timing diagram showing a case where the CPOL is 1 and the CPHASE is 0. Since CPOL is 1, the clock has a default of 1, so CLK occurs from 1. Since CPHASE is 0, it is sampled at the edge of the first clock, so data is sampled at the falling edge. The data is then transmitted on the rising edge. FIG. 3 (c) is a timing diagram showing a case where the CPOL is 0 and the CPHASE is 1. Since CPOL is 0, the clock has a default value of 0, so CLK occurs from 0. Since CPHASE is 0, it is sampled at the edge of the second clock, so data is sampled at the falling edge. The data is then transmitted on the rising edge. 3 (d) is a timing diagram showing a case where the CPOL is 1 and the CPHASE is 1. Since CPOL is 1, the clock has a default of 1, so CLK occurs from 1. Since CPHASE is 1, it is sampled at the edge of the second clock, so data is sampled at the rising edge. Then, data is transmitted when the falling edge.

4 is an exemplary diagram illustrating a configuration of a slave device according to an embodiment of the present invention in SPI communication.

The slave device 400 according to an embodiment of the present invention includes an SPI detecting unit 410 and an SPI decoding unit 420.

The SPI detecting unit 410 detects the CPOL and the CPHASE using the CLK, CSB, and MOSI signals received via the SPI bus, and provides the detected CPOL and CPHASE to the SPI decoder 420.

The SPI decoder 420 determines the SPI operation mode using the CPOL and CPHASE values received from the SPI detector 410 and decodes a signal transmitted from the master according to the determined SPI operation mode.

1, in addition to the CLK, CSB, MOSI, and MISO signals according to the related art, a pin for transmitting and receiving the CPOL and the CPHASE is also required. In contrast, the embodiment of the present invention detects CPOL and CPHASE from the CLK, CSB, and MOSI signals. Therefore, as shown in FIG. 4, in addition to pins for transmitting and receiving CLK, CSB, MOSI, and MISO signals, No pin to receive is needed.

5 is a configuration diagram of an SPI mode detecting unit according to an embodiment of the present invention.

The detection unit 410 detects the CPOL and the CPHASE using the information received via the SPI bus. For this purpose, in one embodiment of the present invention, the polarity detection unit 510, the decoding unit 520, the edge determination unit 530, And a phase detector 540.

The polarity detecting unit 510 detects the CPOL using the level of the CLK signal (i.e., the base value of the CLK signal) when the CSB signal is in an inactive state (i.e., high level).

The decoding unit 520 samples the MOSI signal using the rising edge (or the falling edge) of CLK, and decodes the sampled signal. Since the decoding unit 520 does not know the SPI communication mode used by the master, it uses the rising edge (or falling edge) of CLK according to the preset, regardless of the SPI communication mode used by the master.

The edge fin end portion 530 compares the previously predicted pattern value with the MOSI signal pattern decoded by the decoding unit 520. [

The phase detector 540 detects the CPHASE using the comparison result of the edge determiner 530 and the CPOL detected by the polarity detector 510.

Hereinafter, a method for detecting CPOL and CPHASE will be described in more detail with reference to FIG. 6 is a flowchart illustrating a method of detecting CPOL and CPHASE according to an embodiment of the present invention.

In the initial setting step for confirming the SPI operation mode, the slave receives the output signal from the master via the SPI bus (S610). However, according to the embodiment of the present invention, since CPOL and CPHASE are detected using only CLK, CSB, MOSI, and MISO signals, it is not necessary to separately receive CPOL and CPHASE signals from the master.

Next, the CPOL is detected using the CSB and the CLK (S620). When CPOL is detected, it is used when CSB is inactive. This is because CLK has a base value when the CSB is inactive. Therefore, when the CSB is inactive, the CPOL becomes 0 if the CLK default value is 0, and the CPOL becomes 1 if the CLK default value is 1.

Next, the pattern of the MOSI signal received using the SPI bus is decoded using the rising edge and the falling edge of the CLK in accordance with the preset (S630). In the initial setup stage to check the SPI operation mode, the slave does not yet know the CPHASE, so it decodes the MOSI signal using the rising edge of CLK or decodes the MOSI signal using the falling edge of CLK in advance.

Next, the slave compares the pattern of the decoded signal with the predetermined pattern, and determines whether the master uses the rising edge or the falling edge of the CLK (S640). For example, if the pattern of the MOSI signal decoded using the rising edge of CLK matches the previously promised pattern signal, then using the rising edge of CLK is the SPI mode of operation used by the master Edge). Conversely, if they do not match, the master knows that they used the falling edge of CLK.

However, even when the CPHASE is 0, there is a mode (Fig. 3 (a)) that uses the rising edge and a mode (Fig. 3 (d)) that uses the rising edge even when the CPHASE is 1 , The above result alone can not detect CPHASE.

Accordingly, the slave determines the CPHASE using the CPOL detected in step S620 together with the edge of the CLK used by the master determined in step S640 (S650). For example, if it is determined in step S640 that the master uses the rising edge of the CLK, CPHASE has to be 0 (corresponding to the mode of FIG. 3A) if the CPOL determined in step S620 is 0, If the determined CPOL is 1, CPHASE has to have 1 (corresponding to the mode of FIG. 3 (d)).

Using the CPOL and CPHASE determined in the above manner, the slave determines the SPI communication method used by the master (S660).

Although it is described in FIG. 6 that steps S610 to S650 are sequentially executed, this is merely illustrative of the technical idea of an embodiment of the present invention. In other words, those skilled in the art will appreciate that the present invention can be implemented by changing the order described in FIG. 6 without departing from the essential characteristics of an embodiment of the present invention, or by executing one of steps S610 to S660 6 is not limited to the time-series order because it can be variously modified and modified by being executed in parallel.

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

170: SPI decoding unit 210: SPI Master
220 (a) to 220 (c): SPI Slave 310: sampling point
400: SPI Slave 410: SPI detector
420: SPI decoding unit 510: Polarity detection unit
520: decoding unit 530: edge determining unit
540:

Claims (11)

In a data communication system,
SPI (Serial Peripheral Interface) bus;
A master device connected to the SPI bus; And
(Clock Phase) and CPHASE (Clock Phase) based on at least a part of CLK (Clock), CSB (Chip Select Bar) and MOSI (Master Out Slave In) signals connected to the SPI bus. ) For determining an SPI communication mode to be used by the master device and a slave device
, ≪ / RTI &
Wherein the slave device includes a polarity detector for determining the CPOL according to the CLK value when the CSB is in an inactive state. delete The method according to claim 1,
The slave device includes:
Further comprising a decoding unit for decoding the MOSI signal by alternatively using a rising edge or a falling edge of the CLK. The method of claim 3,
The slave device includes:
Further comprising an edge determining unit for comparing the result of decoding the MOSI signal with a predetermined signal pattern and determining an edge of a CLK used by the master to transmit the MOSI signal. 5. The method of claim 4,
The slave device includes:
And a phase detector for determining a CPHASE (Clock Phase) based on the CPOL determined by the polarity detector and the edge of the CLK determined by the edge determiner. 5. The method of claim 4,
The pre-determined signal pattern may be a signal pattern,
Wherein the length of the signal pattern is different depending on whether the SPI communication is a single-byte method or a multi-byte method. A method of detecting a SPI communication mode in a slave device in SPI (Serial Peripheral Interface) communication,
Determining a CPOL (Clock Polarity) according to a CLK value when the CSB is in an inactive state using a CLK (Clock) and a CSB (Chip Select Bar) received via an SPI bus;
Comparing a result of decoding the Master Out Slave In (MOSI) signal with a predetermined signal pattern, and determining an edge of the CLK used by the master device to transmit the MOSI signal; And
The process of determining the CPHASE (Clock Phase) based on the determined CPOL and the edge of the determined CLK
The method comprising the steps of: delete 8. The method of claim 7,
Further comprising the step of decoding the MOSI signal by alternatively using a rising edge or a falling edge of the clock signal CLK. 10. The method of claim 9,
And the edge of the CLK used for the MOSI signal transmission is determined to be equal to the edge of the CLK used for decoding the MOSI signal when the decoded result coincides with the predetermined signal pattern. Method of detecting operating mode. 8. The method of claim 7,
The pre-determined signal pattern may be a signal pattern,
Wherein the length of the signal pattern is different depending on whether the SPI communication is a single-byte method or a multi-byte method.

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