KR101563772B1 - SERDES for high speed interface - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface (SERDES) for a high-speed interface, a serializer for converting input parallel data into serial data, and a serializer for outputting the serial data output from the serializer, And a deserializer for converting the parallel data into serial data. The serializer converts the parallel data into serial data, and supplies the serial data to the serializer, The deserializer includes the same circuit elements as the serializer, and outputs the parallel data between the delay elements. The delay elements are connected in series. According to the present invention, the use of a wave-pipelined SERDES that synchronizes itself by using a delay element without a clock signal enables a high-speed operation and power consumption to be greatly reduced without loss of data.

Description

{SERDES for high speed interface}

The present invention relates to SERDES for high speed interfaces.

Recently, as high-performance data communication and multimedia technology are spreading to the living standards, there is an increasing demand for a technology capable of transmitting various kinds of data at a high speed and a low power configuration. In a conventional PC, data is processed in parallel. But

However, since the number of transmission lines for parallel data transmission increases, there arises problems such as an increase in area and signal distortion due to coupling between transmission lines. Therefore, in order to prevent such a problem, a method of serializing and transmitting data at high speed is used, and a system for converting parallel data to serial and converting received serial data to parallel data is needed.

SERDES is a transceiver related to the transmission and reception of signals transmitted between high-speed serial links. Sedes transforms a parallel signal into a serial signal or converts a serial signal into a parallel signal.

In general, the desdesystem includes a serializer and a deserializer. Here, a serializer is a device for converting a parallel signal into a serial signal, and a deserializer is a device for converting a serial signal into a parallel signal. Such a system is widely employed to perform higher-bandwidth data communication in a semiconductor integrated circuit.

FIG. 1 shows a general data transmission / reception system 1 using a wireless terminal 10. 1, the data transmission and reception system 1 includes a server 10, a link layer 20, and a host 30. The host 30 and the link layer 20 transmit and receive high-speed serial data using the desert.

The desdes 10 includes a serializer 40 and a deserializer 50. [ The serializer 40 receives N-bit parallel data from the link layer 20, converts the serial data into high-speed serial data, and transmits the high-speed serial data to the host 30. In general, serializer 40 serializes 10 bits of parallel data encoded with 8B10B code from link layer 20.

The deserializer 50 receives the high-speed serial data from the host 30, restores the parallel data of N bits, and transmits the parallel data to the link layer 20.

2 is a circuit diagram of a conventional desdes. The circuit of FIG. 2 is a model using 4-bit data transmission as a D flip-flop.

Referring to FIG. 2, D3, D2, D1, and D0 are respective parallel data inputs. Each parallel data is stored into the respective flip-flop via the MUX when the LOADb signal is low. Thereafter, when the LOADb signal goes high, the parallel data input is interrupted and the output of the flip-flop of the previous stage is input. In addition, the EN signal operates the flip-flop to shift the data stored in the flip-flop to the next flip-flop in accordance with the clock signal. Therefore, the flip-flop output of the last stage is serialized from the bit # 0 of the input parallel data to the clock frequency.

The parallel data is converted into a serial signal and transmitted to a deserializer. The received data is shifted and stored according to the receiving end flip-flop clock signal. When the D0 signal is transmitted to the last flip-flop of the receiving end, each data is output in parallel from Q3 to Q0. The EN signal of the receiving end stops the operation of the flip-flop when the 4-bit data arrives and outputs it.

In this way, the sender and receiver clocks must have the same frequency and be synchronized with the transmitted data. Therefore, when an embedded clock is used to transmit data and a clock simultaneously to a receiving end, and to minimize the number of transmission lines used, a CDR circuit separates data and clock from the transmitted signal, A frequency synchronization circuit such as a phase locked loop (PLL) is additionally needed to synchronize the clocks of the transmitter and receiver. Additional circuitry results in increased area and additional power consumption. Also, the instantaneous power consumption that occurs when the clock is applied to the flip - flop at the same time is very large.

Conventionally used synchronous serial is a structure in which a clock signal is inserted into a data stream by a transmitter and a clock is obtained from a data stream by a receiver. In addition, a PLL is required in the receiver for synchronization of transmitted data. As described above, in the conventional system, since a clock is used, high power consumption occurs due to an additional circuit configuration, and the size of the circuit increases.

In this way, a circuit configuration that maintains high-speed operation while maintaining low power is required in the system.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-mentioned problems, and it is an object of the present invention to provide a clock-less data transmission method using a wave-pipelined SERDES structure and to provide a delay element and a tri- state inverter. The purpose of this circuit is to construct a circuit that can operate at a higher speed and operate at a lower power than the conventional system by ensuring low power by adjusting the delay time,

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a serializer for converting input parallel data into serial data, a serializer for converting the serial data output from the serializer into parallel data, And a deserializer, wherein the serializer includes a delay element for each bit constituting parallel data in a process of converting parallel data into serial data, and a delay element for delaying each input bit for a predetermined time, The deserializer is composed of the same circuit elements as the serializer, and outputs parallel data between the delay elements.

And a tri-state inverter is connected between the delay elements.

In the serializer, parallel data may be input between the three-phase inverter and the delay element. In the deserializer, data may be output between the delay element and the three-phase inverter.

When the pilot signal is input to the delay element in the deserializer, data can be initialized. That is, if the pilot signal is output from the last delay element of the deserializer, the data transmission of the deserializer is stopped, the parallel data is fetched (en_latch), and the initialization is performed (reset).

The delay element may include a keeper for feeding back the input data signal to maintain the same data value, and one or more inverters connected to the input end of the keeper in series.

According to the present invention, the use of a wave-pipelined SERDES that synchronizes itself by using a delay element without a clock signal enables a high-speed operation and power consumption to be greatly reduced without loss of data.

That is, according to the present invention, the delay timing of the delay element and the tri-state inverter is used in place of the additional PLL for generating the conventional clock and the flip-flop for which instantaneous large power consumption occurs, And the power consumption can be greatly reduced.

FIG. 1 shows a general data transmission / reception system using a standard.
2 is a circuit diagram of a conventional desdes.
3 is a block diagram of a desdes in accordance with an embodiment of the present invention.
4 is a timing diagram of each signal according to an embodiment of the present invention.
5 is a circuit diagram of a serializer according to an embodiment of the present invention.
6 is a circuit diagram of a deserializer according to an embodiment of the present invention.
7 is a circuit diagram of a delay element according to an embodiment of the present invention.
FIG. 8 is a graph showing simulation results of the desdes during data input according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. Also, throughout this specification, when a component is referred to as "comprising ", it means that it can include other components, aside from other components, .

In the present invention, SERDES is used for data transmission to the outside of the chip, but it can also be used in SoC that integrates the system into one chip. That is, the data can also be used for data transmission within a single chip.

3 is a block diagram of a desdes in accordance with an embodiment of the present invention.

Referring to FIG. 3, the present invention includes a serializer 100 and a deserializer 200.

The serializer 100 converts input parallel data into serial data.

The deserializer 200 converts the serial data output from the serializer 100 into parallel data and outputs the parallel data.

5 is a circuit diagram of a serializer according to an embodiment of the present invention.

Referring to FIG. 5, the serializer 100 includes a delay element 300, which is provided for each bit constituting parallel data in the process of converting parallel data into serial data, and delays input bits by a predetermined time do. At this time, the delay elements 300 are connected in series.

The serializer 100 has a structure in which a tri-state inverter 400 is connected between the delay elements 300.

In the serializer 100, parallel data D0 to D7 are input between the three-phase inverter 400 and the delay element 300. [

The embodiment of FIG. 5 is an embodiment of an 8-bit serializer 100.

The serializer 100 of the present invention utilizes the self transmission delay of each transmission end composed of a delay element (DE) 300 and a three-phase inverter 400 instead of transmitting data according to the clock period. In this case, since the transmission width between each data bit of the transmitted serial signal must be constant, it is important to design the transmission delay of each transmission end to be constant.

The operation of the serializer 100 is as follows.

When the load signal becomes high, the respective parallel data D7 to D0 are inputted to the input terminal of the delay element 300 through the TG (Transmisson gate).

The delay element 300 is a delay module, and an input signal is transmitted to an output terminal after a predetermined delay time. Therefore, when a certain delay time elapses after the load, the parallel input data is input to the three-phase inverter 400 of each transmission stage.

Thereafter, the load signal goes low to block parallel data input. This prevents the parallel data from affecting the transmission data if the parallel input data is changed before the serial data is transmitted.

When the load signal is low and the en_se signal goes high, serialization and transmission start. At this time, when the load signal and the en_se signal become high at the same time, collision between the transmission data and the parallel input data occurs, so that it should not be high at the same time. Accordingly, when the load signal is low, the en_se signal is low. At this time, since the input terminal of the delay element 300 becomes a floating node and becomes unstable, a keeper circuit is added to the input terminal of the delay element 300 do. This can be confirmed in FIG.

P in the parallel data input terminal is a pilot signal, and this signal is a signal that the reception is completed when data is received in the deserializer 200.

6 is a circuit diagram of a deserializer according to an embodiment of the present invention.

6, the deserializer 200 is composed of the same circuit elements as the serializer 100, and outputs the parallel data P0 to P7 between the delay elements 300, respectively.

In order to prevent erroneous data transmission between the serializer 100 and the deserializer 200 in order to prevent erroneous data transmission, the serializer 100 and the deserializer 200 are required to have the same timing relationship. The same.

In the deserializer 200, data is output between the delay element 300 and the three-phase inverter 400.

In an embodiment of the present invention, deserializer 200 may initialize data when a pilot signal is input to last delay element 305. [

The reset signal initializes each transmission end of deserializer 200. Initialization must be preceded before data is received.

The serialized data transmitted from the transmitter is input through the serial in input. The input data is transmitted to the next transmission end through the three-phase inverter 400 and the delay element 300 as in the serializer 100.

When transmitting data from the transmitting end to the receiving end, the pilot signal (P) is added to the front of the data. When this pilot signal arrives at the last stage of the receiving end, it notifies that all the data has arrived and outputs the serialized data in parallel (P0 to P7).

en_latch The parallelized data is taken from the system according to the signal. After the signal is output in parallel, the receiving end receives a reset signal to initialize the data and prepare to receive the next data. It also sends an ack signal to the transmitter to indicate that it is ready to receive data.

4 is a timing diagram of each signal according to an embodiment of the present invention. 4 is a timing diagram of each signal in the serializer of Fig. 5 and the deserializer of Fig. 6;

The delay time of the delay element 300 and the tri-state inverter 400 when the data input in parallel in the serializer 100 is divided into bits is affected by the present invention.

4, 5 and 7, in the initial stage, the load signal of the serializer 100 is high and the en_se signal is low. At this time, the parallel data enters the input signal of the serializer 100.

the data is transferred to the respective delay elements 300 by the load signal and output after a predetermined delay time. Thereafter, the load signal becomes low to stop the input to the serializer 100, and the en_se signal becomes high to turn on the three-phase inverter 400. [

The signal output through the delay element 300 enters the next three-phase buffer. At this time, in order to prevent transmission data loss, en_se should be turned ON simultaneously with the load signal.

The signals shifted to the next three-phase buffer are separated and transmitted by the transmission delay time of the three-phase inverter 400 and the delay element 300.

When parallel data is transmitted as a serial signal, a pilot signal is added to the beginning of the data. When the pilot signal is output from the last delay element 305 of the deserializer 200, all tri-state inverters of the DES will stop data transmission.

The transmitted serial data may be located in parallel with the deserializer 200 to obtain the parallel data transmitted from the data detector of each deserializer 200.

When the pilot signal is output from the last delay element 305 of the deserializer 200, the en_latch signal is applied. The en_latch signal indicates that the data transmission is completed. After the data transmission is completed, the reset signal becomes High, so that the data stored in the deserializer 200 is initialized and ready to receive the next data packet. At this time, the last bit of the data transmitted from the serializer 100 becomes 0, and the transmission line is in an idle state in which no operation is performed. And remains in an idle state until the next load signal is applied.

7 is a circuit diagram of a delay element according to an embodiment of the present invention.

7, the delay device 300 includes a keeper 500 for feeding back an input data signal to maintain the same data value, and a keeper 500 for connecting the keeper 500 to one or more And an inverter 700. In the embodiment of FIG. 7, the delay element 300 is a structure including four inverters 700.

The keeper 500 is formed by coupling the first PMOS P1 and the second PMOS P2.

In the present invention, the data rate of the deserializer 300 can be adjusted by the input voltage Vn applied to the delay element 300. The smaller the delay time of the delay element 300, the faster the data rate. For example, to use the maximum data rate, the voltage of Vn is set to the supply voltage.

FIG. 8 is a graph showing simulation results of the desdes during data input according to an embodiment of the present invention.

The simulation result of FIG. 8 shows that the semiconductor 180 nm process operates at a speed of 3.9 Gbps and has a power consumption of 1 mW. As a result of the simulation, it can be seen that the power consumption of the present invention is 47% lower than that of the conventional power supply.

While the present invention has been described with reference to several preferred embodiments, these embodiments are illustrative and not restrictive. It will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit of the invention and the scope of the appended claims.

100 serializer 200 deserializer
300 Delay element 400 Three-phase inverter
500 keeper 700 inverter

Claims (6)

In SERDES for high-speed interfaces,
A serializer for converting input parallel data into serial data; And
And a deserializer for converting the serial data output from the serializer into parallel data and outputting the parallel data again,
The serializer includes a delay element provided for each bit constituting parallel data in a process of converting parallel data into serial data and delaying each input bit for a predetermined time,
The delay elements are connected in series,
Wherein the deserializer is composed of the same circuit elements as the serializer and outputs each parallel data between the delay elements,
A tri-state inverter is connected between the delay elements,
Parallel data is input between the three-phase inverter and the delay element in the serializer,
Wherein data is output between the delay element and the three-phase inverter in the deserializer,
The serializer adds a pilot signal to the front of parallel data input to the serializer, and when the pilot signal arrives at the last end of the receiver in the deserializer, the data reception is completed and the serialized data is output in parallel,
Wherein the delay element includes a keeper for feeding back an input data signal to maintain the same data value, and at least one inverter connected to the input end of the keeper in series,
Wherein the serializer transmits data using a self-transmission delay of each of the transmission stages including each of the delay elements and the three-phase inverter, wherein the transmission delay of each transmission stage is constant.
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