KR101529645B1 - Liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

A liquid crystal display device capable of stabilizing an electrical characteristic and improving an aperture ratio and a manufacturing method thereof are disclosed.

A liquid crystal display device of the present invention includes first and second common lines, first and second common lines arranged in parallel with first and second gate lines, respectively, and a data line and a data line, A connection electrode electrically connecting the first and second common lines, first and second thin film transistors connected to the first and second gate lines and to the data line, and a second thin film transistor electrically connected to the first thin film transistor and the second thin film transistor And a pixel electrode.

Liquid crystal display, aperture ratio, connecting electrodes, electrical characteristics

Description

[0001] The present invention relates to a liquid crystal display device and a manufacturing method thereof,

1 is a plan view showing a liquid crystal display device according to the present invention.

2 is a cross-sectional view taken along line A-A 'and line B-B' in the liquid crystal display device of FIG. 1;

3A to 3D are diagrams for explaining a process of manufacturing a liquid crystal display device of the present invention.

Description of the Related Art

1, 3, 5, 7: pixel region 8: thin film transistor region

9: connection area 10: substrate

11a, 11b: gate lines 13a, 13b: common lines

15: gate electrode 17: gate insulating film

18: active layer 19: ohmic contact layer

20: semiconductor layer 21a: source electrode

21b: drain electrode 23: thin film transistor

25, 26: data line 27: connecting electrode

29a, 29b, 33: contact hole 31:

35, 36, 37, 38: pixel electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of stabilizing electrical characteristics and improving an aperture ratio and a method of manufacturing the same.

As the information society develops, the demand for display devices is increasing in various forms. In recent years, various flat panel display devices including a liquid crystal display device (LCD), a plasma display panel (PDP), and an electro luminescent display (ELD) have been studied. Has already been widely used as a display device.

Among these, the liquid crystal display device is excellent in the current image quality, and has advantages such as light weight, thinness, and low power consumption, thereby quickly replacing the CRT. 2. Description of the Related Art Liquid crystal display devices have been developed variously as monitors for notebook computers, display panels for televisions, and the like.

The liquid crystal display device must maintain the data voltage for one frame in order to display desired information on one screen. To this end, the liquid crystal display device is formed with a storage capacitor. The data voltage can be maintained for one frame by the storage capacitor.

The storage capacitor is formed by a gate line serving as a first storage electrode, a pixel electrode serving as a second storage electrode, and a gate insulating film and a protective film having a dielectric constant between the first and second storage electrodes. The first and second storage electrodes may overlap. A system having such a structure is referred to as a storage-on-gate (SOG) system.

If a gate line is used as the first storage electrode, it can affect the gate voltage passing to the gate line by the data voltage stored in the storage capacitor.

In order to solve this problem, a storage capacitor is formed by a common line serving as a first storage electrode, a pixel electrode serving as a second storage electrode, a gate insulating film having a dielectric constant between the first and second storage electrodes, and a protective film . A scheme having such a structure is referred to as a storage on common (SOC) scheme.

Since the common lines are arranged corresponding to the respective gate lines, a plurality of common lines are arranged in the liquid crystal display device.

In this case, even if the same common voltage is supplied to each common line, the width of each common line is not constant, so that the line resistance of each common line is different, and a common voltage slightly different to each common line is ultimately applied .

In addition, when a predetermined region of a common line is disconnected, a common voltage can not be smoothly supplied to the common line, resulting in a problem that the storage capacitor is not provided.

In order to solve such a problem, a mesh common electrode having a mesh structure in which each common line disposed in an adjacent pixel region is electrically connected has been proposed.

A common voltage having an equal potential is applied between common electrodes arranged in adjacent pixel regions by the mesh common electrode, so that stable electrical characteristics are expected.

The mesh common electrodes are connected by the connection electrodes formed on the same layer, with the common lines arranged in the adjacent pixel regions being the same material as the pixel electrodes. Each common line is formed on the same layer as the gate line, and a connecting electrode is required because each common line arranged in the adjacent pixel region can not be connected directly. Accordingly, each common line and the connection electrode are electrically connected through the contact hole.

However, since the pixel electrode must be formed to be electrically separated from the connection electrode, it is difficult to maximize the size of the pixel electrode, which results in a problem that the aperture ratio is reduced.

In addition, since the pixel electrode is made of a conductive material having a high resistance, the connection electrode formed of the same material as the pixel electrode also has a high resistance, so that it is difficult for the common voltage to be transmitted to the adjacent pixel region through the connection electrode, The equal potential is not maintained between the common electrodes arranged in the pixel region, and the electrical characteristics become unstable.

An object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same that can maximize the pixel electrode to improve the aperture ratio.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same which can stabilize electrical characteristics by maintaining a uniform equipotential.

According to a first aspect of the present invention, there is provided a liquid crystal display including: first and second gate lines arranged in a first direction; First and second common lines arranged parallel to the first and second gate lines, respectively; A data line arranged in a second direction intersecting the first direction; A connection electrode disposed on the same layer as the data line and electrically connecting the first and second common lines; First and second thin film transistors connected to the first and second gate lines and to the data line; And a pixel electrode electrically connected to the first and second thin film transistors.

According to a second embodiment of the present invention, a method of manufacturing a liquid crystal display comprises: forming a gate line, a gate electrode, and first and second common lines on a substrate; Forming a gate insulating film having first and second contact holes on the substrate including the gate line, the first and second common lines being exposed; Forming a semiconductor layer on the gate insulating film corresponding to the gate electrode; Forming a data line, a source / drain electrode, and a connection electrode on the substrate including the semiconductor layer; Forming a protective film on the substrate including the data lines; And forming a pixel electrode on the passivation layer, wherein the connection electrode is electrically connected to the first common line through the first contact hole, and the second common line is electrically connected to the second common line through the second contact hole, And is electrically connected.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view showing a liquid crystal display device according to the present invention, and FIG. 2 is a cross-sectional view taken along line A-A 'and line B-B' in the liquid crystal display device of FIG.

1 and 2, first and second gate lines 11a and 11b are arranged on a substrate 10 along a first direction and extend from the first and second gate lines 11a and 11b, And the gate electrode 15 is disposed in the thin film transistor region 8.

First and second common lines 13a and 13b having a mesh structure are disposed on the same layer as the first and second gate lines 11a and 11b. The first common line 13a is arranged in the first pixel region 1 between the first gate line 11a and the dummy gate line (not shown), and the second common line 13b is arranged in the first pixel region 1 between the first gate line 11a and the dummy gate line And the second pixel region 3 between the first and second gate lines 11a and 11b. The first common line 13a may be disposed along an edge region of the first pixel region 1. [ The second common line 13b may be disposed along the edge region of the second pixel region 3. [ The first common line 13a may be integrally connected between the first and third pixel regions 1 and 5 adjacent to each other in the first direction. The second common line 13b may be integrally connected between the second and fourth pixel regions 3 and 7 adjacent to each other in the first direction. (1, 3) adjacent in the second direction perpendicular to the first direction and between the third and fourth pixel regions (5, 7) adjacent to the first and second pixel regions Since the first gate line 11a is disposed in the same layer as the lines 13a and 13b, the first and second pixel regions 1 and 3 adjacent to each other in the second direction, The first and second common lines 13a and 13b can not be integrally connected to each other between the four pixel regions 5 and 7.

A gate insulating film 17 is formed on the substrate 10 including the first and second gate lines 11a and 11b.

The first common line 13a and the second and fourth pixel regions 3 and 7 disposed in the first and third pixels 1 and 5 are formed in the connection region 9 of the gate insulating layer 17, The first and second contact holes 29a and 29b are formed to expose the second common line 13b disposed in the first contact hole 29a. The first contact hole 29a may be formed in the gate insulating layer 17 such that the first common line 13a disposed in the first and third pixel regions 1 and 5 is exposed. The second contact hole 29b may be formed in the gate insulating layer 17 such that a second common line 13b disposed in the second and fourth pixel regions 3 and 7 is exposed.

A semiconductor layer 20 including an active layer 18 and an ohmic contact layer 19 is disposed on the gate insulating film 17 corresponding to the gate electrode 15. [

First and second data lines 25 and 26 are disposed on the gate insulating layer 17 in the second direction and source and drain electrodes 21a and 21b are formed on the semiconductor layer 20, . The source electrode 21a may extend from the first and second data lines 25 and 26, respectively.

The thin film transistor 23 may be constituted by the gate electrode 15, the semiconductor layer 20 and the source and drain electrodes 21a and 21b.

Wherein the first pixel region 1 is defined by the first gate line 11a and the first data line 25 and the second pixel region 3 is defined by the second gate line 11b, May be defined by the first data line 25. The third pixel region 5 is defined by the first gate line 11a and the second data line 26 and the fourth pixel region 7 is defined by the second gate line 11b, And may be defined by a second data line 26.

The connection electrode 27 is disposed on the same layer as the first and second data lines 25 and 26 and is connected to the first and the second pixel regions 1 and 5 through the first A second contact hole 29b formed in the gate insulating film 17 of the second and fourth pixel regions 3 and 7 and electrically connected to the first common line 13a through a contact hole 29a, And may be electrically connected to the second common line 13b. The connection electrode 27 is electrically connected to the second and fourth pixel regions 3 and 4 through the first contact hole 29a formed in the first and third pixel regions 1 and 5 and the first gate line 11a, And the second contact hole 29b formed in the first and second contact holes 7 and 7, respectively.

Although the connecting electrode 27 is formed in an angular rectangle in the drawing, the connecting electrode 27 may have a rectangular shape having rounded corners, or a shape in which the width of the central region is relatively narrower than the edge regions on both sides.

A first common line 13a disposed in the first and third pixel regions 1 and 5 and a second common line 13b disposed in the second and fourth pixel regions 3 and 7 by the connection electrode 27, The common line 13b can be electrically connected. Since the first and second common lines 13a and 13b are electrically connected by the connection electrode 27, the first and second common lines 13a and 13b can be maintained at the same potential.

Therefore, by disposing the connecting electrode 27 with the same conductive material as the data line having excellent conductivity, the equipotential can be maintained between the first and second common lines 13a and 13b, so that the electrical characteristics can be stabilized.

A protective film 31 is formed on the substrate 10 including the first and second data lines 25 and 26. A third contact hole 33 is formed in the passivation layer 31 to expose the drain electrode 21b.

The first to fourth pixel electrodes 35 to 38 electrically connected to the drain electrode 21b are disposed on the protective film 31 through the third contact hole 33. [

The first and second common lines 13a and 13b are overlapped with the first to fourth pixel electrodes 35 to 38 and between the common lines 13a and 13b and the pixel electrodes 35 to 38 The storage capacitance can be formed because the gate insulating film 17 and the protective film 31 having a dielectric constant are formed in the gate insulating film. The data voltage can be maintained for one frame in this storage capacitance.

The first to fourth pixel electrodes 35 to 38 are connected to the first and second gate lines 11a and 11b and the first and second gate lines 11a and 11b to the first to fourth pixel regions 1 to 3, And the second data lines 25 and 26, the sizes of the first to fourth pixel electrodes 35 to 38 are maximized, and the aperture ratio can be improved.

3A to 3D are views for explaining a manufacturing process of a liquid crystal display device of the present invention.

The following description will be made with reference to Figs. 1 and 2. Fig.

3A, a first metal film is first formed on a substrate 10, and then the first metal film is patterned using a first mask to form first and second gate lines 11a and 11b, The gate electrode 15 and the first and second common lines 13a and 13b are formed. The first and second gate lines 11a and 11b are formed along the first direction and the gate electrode 15 is formed in the thin film transistor region 8 from the first and second gate lines 11a and 11b Can be extended. The first common line 13a is formed along each edge region of the first and third pixel regions 1 and 5 adjacent to each other in the first direction and the adjacent first and third pixel regions 1, As shown in FIG. Wherein the second common line (13b) is formed along each edge region of the second and fourth pixel regions (3, 7) adjacent in the first direction, and the adjacent second and fourth pixel regions (3, 7) As shown in FIG.

A gate insulating film 17 is formed on the substrate 10 including the first and second gate lines 11a and 11b. The first common line 13a formed in the first and third pixel regions 1 and 5 is exposed in the connection region 9 by patterning the gate insulating film 17 using the second mask, The second contact hole 29b exposing the second common line 13b formed in the second and fourth pixel regions 3 and 7 is formed.

3B, pure silicon and impurity-doped silicon are successively formed on the gate insulating film 17, and then the pure silicon and impurity-doped silicon are patterned using a third mask, The active layer 18 and the ohmic contact layer 19 are formed in the thin film transistor region 8. The semiconductor layer 20 including the active layer 18 and the ohmic contact layer 19 may be formed. The semiconductor layer 20 may be formed on the gate insulating film 17 corresponding to the gate electrode 15.

A second metal film is formed on the substrate 10 including the semiconductor layer 20 and then the second metal film is patterned using a fourth mask to form first and second data lines 25 and 26, Source / drain electrodes 21a and 21b, and a connection electrode 27 are formed. The first and second data lines 25 and 26 are formed along a second direction perpendicular to the first direction. The source and drain electrodes 21a and 21b may be spaced apart from each other on the semiconductor layer 20. The source electrode 21 a may extend from the first and second data lines 25 and 26.

The thin film transistor 23 can be formed by the gate electrode 15, the semiconductor layer 20, and the source / drain electrodes 21a and 21b.

Wherein the first pixel region 1 is defined by the first gate line 11a and the first data line 25 and the second pixel region 3 is defined by the second gate line 11b, May be defined by the first data line 25. The third pixel region 5 is defined by the first gate line 11a and the second data line 26 and the fourth pixel region 7 is defined by the second gate line 11b, And may be defined by a second data line 26.

The connection electrodes 27 may be formed of the same material as the first and second data lines 25 and 26 at the same time.

The connection electrode 27 is electrically connected to the first common line 13a through a first contact hole 29a formed in the first and third pixel regions 1 and 5, And may be electrically connected to the second common line 13b through a second contact hole 29b formed in the four pixel regions 3 and 7. [ The connection electrode 27 is electrically connected to the second and fourth pixel regions 3 and 4 from the first contact hole 29a formed in the first and third pixel regions 1 and 5 through the first gate line 11a, And the second contact hole 29b formed in the second contact hole 7a.

Since the first and second common lines 13a and 13b are electrically connected by the connection electrode 27, the first and second common lines 13a and 13b can be maintained at the same potential.

Therefore, by disposing the connecting electrodes 27 with the same conductive material as the first and second data lines 25 and 26 having excellent conductivity, the equipotential is maintained between the first and second common lines 13a and 13b, The characteristics can be stabilized.

A protective film 31 is formed on the substrate 10 including the first and second data lines 25 and 26 and the protective film 31 is formed using a fifth mask, The third contact hole 33 in which the drain electrode 21b is exposed is formed.

3D, a transparent conductive film is formed on the protective film 31, and then the conductive film is patterned using a sixth mask to form the first to fourth pixel regions 1, 3, 5, and 7 The first to fourth pixel electrodes 35 to 38 electrically connected to the drain electrode 21b are formed through the third contact hole 33. [ Each of the pixel electrodes 35 to 38 may be formed adjacent to the first and second gate lines 11a and 11b and the first and second data lines 25 and 26.

The first and second common lines 13a and 13b are overlapped with the first to fourth pixel electrodes 35 to 38 and between the common lines 13a and 13b and the pixel electrodes 35 to 38 The storage capacitance can be formed because the gate insulating film 17 and the protective film 31 having a dielectric constant are formed in the gate insulating film. The data voltage can be maintained for one frame in this storage capacitance.

Since the connection electrodes 27 are formed on the same layer as the first and second data lines 25 and 26, the pixel electrodes do not need to be disturbed by the connection electrodes, To 38 can be maximized in the pixel regions 1, 3, 5, and 7, so that the aperture ratio can be improved.

As described above, according to the present invention, since each common line formed in the adjacent pixel region is formed of a material having excellent conductivity such as a metal film, the equipotential is precisely maintained between the common lines, so that the electrical characteristics can be stabilized .

According to the present invention, since the connection electrode is formed in a different layer from the pixel electrode, the pixel electrode is not disturbed by the connection electrode, so that the pixel electrode can be maximized in the pixel region, so that the aperture ratio can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (18)

First and second gate lines arranged in a first direction; First and second common lines arranged parallel to the first and second gate lines, respectively; A data line arranged in a second direction intersecting the first direction; A connection electrode which is disposed on the same layer as the data line and is the same metal as the data line and electrically connects the first and second common lines; First and second thin film transistors connected to the first and second gate lines and to the data line; And And a pixel electrode electrically connected to the first and second thin film transistors, Wherein the pixel electrode is disposed adjacent to the first or second gate line on the connection electrode, Wherein the first and second common lines are disposed on the same layer as the first and second gate lines. The semiconductor device according to claim 1, further comprising a gate insulating film formed between the first and second gate lines and the connection electrode and having first and second contact holes formed on the first and second common lines Wherein the liquid crystal display device is a liquid crystal display device. 3. The liquid crystal display according to claim 2, wherein the connection electrode is electrically connected to the first common line through the first contact hole, and electrically connected to the second common line through the second contact hole. Display device. The liquid crystal display of claim 3, wherein the connection electrode has a shape selected from the group consisting of an angled rectangle and a rounded rectangle. The liquid crystal display device according to claim 3, wherein the connection electrode has a shape in which the width of the central region is relatively narrower than the edge regions of both sides. The liquid crystal display of claim 3, wherein the connection electrode is disposed in a range of the first contact hole to the second contact hole. Forming a gate line, a gate electrode and first and second common lines on a substrate; Forming a gate insulating film having first and second contact holes on the substrate including the gate line, the first and second common lines being exposed; Forming a semiconductor layer on the gate insulating film corresponding to the gate electrode; Forming a data line, a source / drain electrode, and a connection electrode on the substrate including the semiconductor layer, wherein the connection electrode is the same metal as the data line; Forming a protective film on the substrate including the data lines; And And forming a pixel electrode on the protective film, Wherein the pixel electrode is disposed adjacent to the first or second gate line on the connection electrode, The connection electrode is electrically connected to the first common line through the first contact hole and electrically connected to the second common line through the second contact hole, Wherein the first and second common lines are disposed on the same layer as the first and second gate lines. 8. The method of claim 7, wherein the connection electrodes are formed between adjacent pixel regions defined by the gate lines and the data lines. 8. The method of claim 7, wherein the connection electrode is disposed in a range of the first contact hole to the second contact hole. The method according to claim 1, A first pixel region is defined by the first gate line and the first data line, A second pixel region is defined by the first gate line and the second data line, A third pixel region is defined by the second gate line and the first data line, And a fourth pixel region is defined by the second gate line and the second data line. 11. The method of claim 10, Wherein each of the first and second common lines has a perforated structure in the first to fourth pixel regions. 11. The method of claim 10, Wherein the first common line is formed on the first and second pixel regions and has a mesh structure in the first and second pixel regions. 11. The method of claim 10, The second common line is formed on the third and fourth pixel regions, and the third and fourth pixel regions have a mesh structure. 11. The method of claim 10, Wherein the first common line is integrally formed across the first and second pixel regions, And the second common line is integrally formed across the third and fourth pixel regions. 11. The method of claim 10, The connecting electrode And a first connection electrode connecting the first and second common lines on the first gate line across the first and third pixel regions. 11. The method of claim 10, The connecting electrode And a second connection electrode connecting the first and second common lines on the first gate line across the second and fourth pixel regions. The method according to claim 1, Wherein the first and second common lines are the same metal as the first and second gate lines. The method according to claim 1, And the connection electrode is the same metal as the first and second data lines.

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