KR101528753B1 - Etchant having low etch rate and method of manufacturing a display substrate using the same - Google Patents

Abstract

A low etch-rate etchant and a method for manufacturing a display substrate using the same are disclosed. The low etch rate etchant includes hydrogen peroxide (H2O2) that etches metal films and / or metal oxide films, additives that inhibit the reaction of hydrogen peroxide, and extra solvents. This makes it possible to improve the manufacturing reliability of the signal wiring meeting the requirements of the large area and high resolution.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an etchant etchant,

The present invention relates to a low etch rate etchant and a method of manufacturing a display substrate using the same, and more particularly, to a low etch rate etchant used in the manufacture of a liquid crystal display device and a method of manufacturing a display substrate using the same.

In general, a liquid crystal display panel includes a display substrate on which switching elements for driving respective pixel regions are formed, a counter substrate facing the display substrate, and a liquid crystal layer interposed between the display substrate and the counter substrate. The liquid crystal display panel displays an image by applying a voltage to the liquid crystal layer to control the transmittance of light.

The display substrate includes gate lines and data lines which are signal lines, a thin film transistor (TFT) as a switching device, and a pixel electrode electrically connected to the thin film transistor. The thin film transistor includes a gate electrode connected to a gate line, an active pattern formed on the gate electrode, and a source electrode and a drain electrode formed apart from each other on the active pattern.

On the other hand, the length of the signal wirings becomes long according to a demand of a large area and a high resolution of the display device, and a problem of signal delay arises. The signal delay problem can be solved by forming the signal lines with a relatively thick thickness or by forming the signal lines using a low resistance metal.

However, the kind of the low resistance metal is limited, and there is a limitation in controlling the process of manufacturing the display substrate so that the inherent physical properties of the low resistance metal such as aluminum and copper are not deteriorated. In addition, when the thickness of the gate line and the gate electrode is increased, the source electrode and the drain electrode formed on the gate electrode can not normally come down on the side wall of the gate electrode due to a step between the gate electrode and the base substrate The problem of breaking occurs.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a low etch rate etchant for improving manufacturing reliability of a signal wiring that meets a large-area and high-resolution requirement.

Another object of the present invention is to provide a method of manufacturing a display substrate using the etchant of low etching rate.

The low etch rate etchant according to an embodiment for realizing the object of the present invention includes hydrogen peroxide (H2O2) for etching a metal film and / or a metal oxide film, an additive for suppressing the reaction of the hydrogen peroxide and an extra solvent.

Examples of the additives include sodium and sulfuric acid (SPS), potassium and sulfuric acid (PPS), and benzotriazole (BTA). These may be used alone or in combination.

According to another aspect of the present invention, there is provided a method of manufacturing a display substrate using the etchant with a low etching rate, the method comprising: forming a trench in a gate region of an insulating substrate; forming a metal seed on the trench; . A metal seed formed on a sidewall surface connected to the bottom surface of the trench is removed using a low etch rate etchant including hydrogen peroxide (H2O2), an additive for suppressing the reaction of hydrogen peroxide and an excess solvent, . Depositing a gate metal layer in the trench in which the buffer layer is formed to form a gate pattern including a gate line and a gate electrode; a data line crossing the gate line on an insulating substrate on which the gate pattern is formed; A source electrode connected to the source electrode, and a drain electrode spaced apart from the source electrode, and forming a pixel electrode to be in contact with the drain electrode.

According to such a low etch rate etchant and a method of manufacturing a display substrate using the etch rate etch rate etchant, a part of the metal seed is removed using a low etch rate etchant, thereby preventing a factor that hinders deposition of the subsequent film. In addition, the low etch rate etchant can remove impurities generated by contact with oxygen on the surface of the buffer layer formed on the bottom surface of the trench and remove impurities generated by contact with oxygen on the surface of the gate metal layer and / or the data metal layer can do.

1 to 6 are cross-sectional views illustrating a method of manufacturing a display substrate according to an embodiment of the present invention.
7 to 12 are cross-sectional views illustrating a method of manufacturing a display substrate according to another embodiment of the present invention.

Hereinafter, a method for manufacturing a low etch rate etchant and a display substrate using the same will be described in detail.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the term "comprises" or "comprising ", etc. is intended to specify that there is a stated feature, figure, step, operation, component, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

In the accompanying drawings, the dimensions of the substrate, layer (film), or patterns are shown enlarged in actuality for clarity of the present invention. In the present invention, when each layer (film), pattern or structure is referred to as being formed on the substrate, on each layer (film) or on the patterns, ) Means that the pattern or structures are directly formed on or under the substrate, each layer (film) or patterns, or another layer (film), another pattern or other structure may be additionally formed on the substrate.

Low etch rate etchant

The low etch rate etchant of the present invention includes hydrogen peroxide (H2O2), additives, and excess solvent.

Hydrogen peroxide

The hydrogen peroxide of the present invention is a compound dissolved in water, ethanol, ether or the like, and in the aqueous solution, the hydrogen peroxide is partially dissociated into hydrogen ions (H +) and has a weak acidity. The decomposition reaction of the hydrogen peroxide occurs relatively more easily in the alkaline aqueous solution than in the acidic aqueous solution. By the decomposition reaction of the hydrogen peroxide, the hydrogen peroxide decomposes into oxygen (O) and water (H 2 O).

The hydrogen peroxide is decomposed in the additive and in the solvent, and the oxygen of the decomposed hydrogen peroxide reacts with the metal and / or the metal oxide of the thin film formed of metal and / or metal oxide. Thereby, the metal and / or the metal oxide reacted with oxygen are separated from the thin film, and the thin film is etched by being dissolved in the solvent. Examples of the metal and / or the metal oxide include molybdenum (Mo), copper (Cu), aluminum (Al), molybdenum oxide, copper oxide and aluminum oxide.

If the content of hydrogen peroxide is less than about 1 weight percent of the total etch rate of the low etch rate, the amount of oxygen generated by the decomposition of the hydrogen peroxide is insignificant, so that the reaction between oxygen and the metal and / or the metal oxide hardly occurs. When the content of the hydrogen peroxide is more than about 10 weight percent, it is difficult to control the decomposition reaction of the hydrogen peroxide, so that the amount of oxygen generated by the decomposition of the hydrogen peroxide is increased, and the thin film is excessively etched. Thus, the content of hydrogen peroxide is preferably from about 1 weight percent to about 10 weight percent of the total low-etch rate etchant weight. In consideration of the chemical stability of the etchant etchant etchant and the reliability of the product, it is more preferable that the content of hydrogen peroxide is about 3 wt% to about 5 wt%.

additive

The additive of the present invention is an inhibitor that inhibits the decomposition reaction of the hydrogen peroxide, and interferes with the reaction of the metal and / or the metal oxide with oxygen generated by decomposition of the hydrogen peroxide.

The additive acidifies the solvent and the decomposition reaction of the hydrogen peroxide in the acidic solvent does not occur. That is, the decomposition reaction of the hydrogen peroxide can be suppressed by the additive, and the generation of oxygen by decomposition of the hydrogen peroxide can be controlled. In addition, the reaction amount of the oxygen with the metal and / or the metal oxide can be controlled by interfering with the reaction between the oxygen and the metal and / or the metal oxide. Thus, the additive can control the hydrogen peroxide to over-etch the thin film, and the etch rate of the etch rate of the etch rate can be adjusted to an appropriate level.

Examples of the additive include a persulfate compound, an azole compound, and the like. Specific examples of the persulfate-based compound include sodium persulfate (SPS), potassium persulfate (PPS), ammonium and sulfuric acid (APS), and the like. Specific examples of the azole compound include pyrazole, imidazole, triazole, pyrazole derivatives, imidazole derivatives, triazole derivatives, and the like. More specific examples of the azole-based compound include benzotriazole (BTA). These may be used alone or in combination. Preferable examples of the additive include sodium and sulfuric acid (SPS), potassium and sulfuric acid (PPS), and benzotriazole (BTA).

If the content of the additive is less than about 1 weight percent of the total low-etch rate etchant, the effect on the decomposition reaction of hydrogen peroxide is minimal. When the content of the additive exceeds about 10 weight percent, the decomposition reaction of the hydrogen peroxide is excessively suppressed and the reaction of oxygen with the metal and / or the metal oxide is excessively disturbed, so that the etching of the thin film substantially does not occur. Accordingly, the content of the additive is preferably from about 1 weight percent to about 10 weight percent of the total low-etch rate etchant weight.

menstruum

The solvent of the present invention is pure water (DI water, Deionized water). The solvent dissolves the hydrogen peroxide and the additive. The solvent may exhibit acidity by hydrogen ions of the hydrogen peroxide and the additive. The solvent is adjusted to the total etch rate of the etchant to 100 weight percent, except for the content of hydrogen peroxide and the additive. Specifically, the solvent content is from about 80 weight percent to about 95 weight percent of the total low-etch rate etchant weight.

On the other hand, in order to remove the metal thin film of about 1000 Å by using the commercialized metal etching solution having an etching rate of about 5000 Å / min, the etching process should be completed in about 12 seconds. When about 12 seconds have elapsed, about 1000 Å or more of the metal thin film is removed. Considering that the etch rate of a commercially available metal etchant is greater than about 1000 A / min and the etch rate of the metal etchant used is from about 4000 A / min to about 6000 A / min, to control the etch depth of the thin film finely and precisely, The etching rate of the etch rate etchant is preferably less than about 1000 A / min. More preferably, the etch rate of the etchant etchant according to the present invention is from about 40 A / min to about 600 A / min.

Example

Low etch rate etchants were prepared according to Examples 1 to 12 of Table 1 below.

[Table 1]

(In Table 1, APS indicates ammonium and sulfuric acid, SPS indicates sodium and sulfuric acid, PPS indicates potassium and sulfuric acid, and BTA indicates benzotriazole)

Comparative Example 1

About 75 weight percent phosphoric acid, about 5 weight percent nitric acid, about 5 weight percent acetic acid, about 5 weight percent sulfuric acid, and 10 weight percent pure water.

Low etch rate Etch rate measurement of etchant

The metal thin films were etched using the compositions prepared according to Examples 1 to 12 and Comparative Example 1, and the average thickness (Å) and average speed (Å / min) of the metal thin films etched with time were measured. The metal thin film was formed by sputtering molybdenum on an insulating substrate to deposit about 2000 Å. The etching temperature was about 30 캜. The measured results are shown in Tables 2 and 3 below.

[Table 2]

[Table 3]

Referring to Tables 2 and 3, the average etch rate (Å / min) of the etchant of low etching rate according to the first to twelfth embodiments of the present invention is the average etch rate (Å / min) of the metal etchant according to Comparative Example 1, min. < / RTI >

The low etch rate etchant according to the present invention is characterized in that the metal film and / or the metal oxide film are etched, and the etching rate is significantly slower than that of an etchant containing a strong acid such as sulfuric acid or nitric acid, It can be easily used for finely and finely controlling the etching thickness or for removing impurities on the surface of the metal film and / or the metal oxide film.

Method for manufacturing display substrate

Hereinafter, embodiments of manufacturing a display substrate using a low etch rate etchant according to the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 to 6 are sectional views for explaining a method of manufacturing a display substrate according to Embodiment 1 of the present invention.

Referring to FIG. 1, a photoresist pattern 120 is formed on an insulating substrate 110.

Examples of the material for forming the insulating substrate 110 include glass, soda lime, and plastic. In the first embodiment of the present invention, the insulating substrate 110 is a glass substrate.

The photoresist pattern 120 exposes the gate region GA of the insulating substrate 110. The gate region GA is a region in which a gate pattern including gate lines of the display substrate and gate electrodes connected to each gate line is formed. Examples of the material for forming the photoresist pattern 120 include a positive photoresist composition and a negative photoresist composition. For example, a photoresist composition is applied on the insulating substrate 110 to form a photoresist layer (not shown), and the photoresist layer is exposed and developed to form the photoresist pattern 120.

Referring to FIG. 2, the insulating substrate 110 is etched using the photoresist pattern 120 as an etching mask. Accordingly, the insulating substrate 110 of the gate region GA is removed, and the trench 112 is formed in the insulating substrate 110.

The trench 112 includes a sidewall surface 113 defining a depth of the trench 112 and a bottom surface 114 connected to the sidewall surface 113 and formed lower than the surface of the insulating substrate 110 do. An undercut may be formed between the sidewall 113 of the trench 112 and the etched surface of the photoresist pattern 120.

Referring to FIG. 3, the trench 112 is formed, and a seed metal layer 130 is formed on the insulating substrate 110 on which the photoresist pattern 120 is formed.

The seed metal layer 130 may be deposited by sputtering. The seed metal layer 130 is formed on the photoresist pattern 120 and is formed on the bottom surface 114 of the trench 112. The seed metal layer 130 may be formed on the sidewall 113 of the trench 112.

The seed metal layer 130 preferably includes a metal capable of substituting for the metal of the gate metal layer for forming the gate pattern. That is, the metal of the seed metal layer 130 is a metal that is larger than the reactivity of the metal of the gate metal layer. Examples of the metal of the seed metal layer 130 include tin (Sn) when the gate metal layer includes copper (Cu).

Referring to FIG. 4, the seed metal layer 130 and the photoresist pattern 120 formed on the photoresist pattern 120 are removed. The seed metal layer 130 formed on the photoresist pattern 120 may be removed from the insulating substrate 110 by removing the photoresist pattern 120. Accordingly, only the seed metal layer 130 formed on the trench 112 remains.

Then, the seed metal layer 130 remaining on the insulating substrate 110 is etched using an etchant. The etchant may remove the seed metal layer 130 formed on the sidewall 113 of the trench 112 in the remaining seed metal layer 130. Since the etching rate of the etchant is about 40 ANGSTROM / min to about 600 ANGSTROM / min, only a part of the seed metal layer 130 can be partially removed by adjusting the time for applying the etchant to the seed metal layer 130. Since the etchant is substantially the same as the etchant of low etch rate according to the present invention described above, the detailed description will not be repeated.

The seed metal layer 130 formed on the sidewall surface 113 is removed and the seed metal layer 130 of the bottom surface 114 is left to form a buffer layer 132 on the bottom surface 114 do.

Meanwhile, impurities formed on the surface of the buffer layer 132 may be removed by applying the etching solution to the insulating substrate 110 on which the buffer layer 132 is formed. The buffer layer 132 may be exposed to air when the insulating substrate 110 on which the buffer layer 132 is formed is moved to a chamber for a subsequent process and the surface of the buffer layer 132, Impurities may be generated. The impurity may form a thin film on the surface of the buffer layer 132, where the film may be removed by the etchant having an etch rate of about 40 A / min to about 600 A / min. That is, the etchant may serve as a surface cleaning agent for the buffer layer 132.

Referring to FIG. 5, a gate metal layer 140 is deposited on the insulating substrate 110 on which the buffer layer 132 is formed. The gate metal layer 140 is deposited on the insulating substrate 110 by electroless plating (ELP). For example, the metal of the buffer layer 132 may be replaced with the metal of the insulating substrate 110 to form the gate metal layer 140. Accordingly, the gate metal layer 140 is formed only in the region where the buffer layer 132 is formed.

For example, since tin in the buffer layer 132 is more reactive than copper in the gate metal layer 140, when copper is added to the insulating substrate 110, tin on the surface of the buffer layer 132 is substituted with copper, The copper may continue to bond with the copper added to the insulating substrate 110 to form the gate metal layer 140.

The buffer layer 132 and the gate metal layer 140 are formed in the trench 112 so that the gate pattern G including the gate lines and the gate electrodes is formed on the insulating substrate 110.

On the other hand, the surface of the gate metal layer 140 can be cleaned by removing the thin film containing impurities formed on the surface of the gate metal layer 140 by using the etchant in contact with the gate metal layer 140 .

Referring to FIG. 6, a gate insulating layer 150 is formed on an insulating substrate 110 on which the gate pattern GL is formed. The gate insulating layer 150 is formed on the entire surface of the insulating substrate 110. The gate pattern G may be formed in the trench 112 so that the gate insulating layer 150 may be formed flat on the surface of the insulating substrate 110.

An active pattern 160 is formed on the insulating substrate 110 on which the gate insulating layer 150 is formed. The active pattern 160 is formed by sequentially forming a semiconductor layer 152 and an ohmic contact layer 154 on the gate insulating layer 150 and patterning the semiconductor layer 162 and the ohmic contact layer 164, . The semiconductor layer 162 may be an amorphous silicon film (a-Si), and the ohmic contact layer 164 may be an amorphous silicon film (n + a-Si) doped with an n-type impurity at a high concentration.

Next, a data metal layer (not shown) is formed on the insulating substrate 110 on which the active pattern 160 is formed, and the data metal layer is patterned to form data lines crossing the gate lines, A source electrode SE and a drain electrode DE spaced apart from the source electrode SE are formed.

On the other hand, the surface of the data metal layer can be cleaned by removing the thin film containing the impurities formed on the surface of the data metal layer by contacting the data metal layer with air using the etchant.

Alternatively, the active layer 160, the data lines, the source electrode SE, and the drain electrode DE may be formed on the gate insulating layer 150 by patterning the semiconductor layer 162, the ohmic contact layer 164 and the data metal layer sequentially and patterning using one mask.

A passivation layer 170 is formed on the insulating substrate 110 on which the data lines, the source electrode SE and the drain electrode DE are formed and the passivation layer 170 is patterned to form the drain electrode (CNT) exposing a part of the contact hole (DE).

A transparent electrode layer (not shown) is formed on the passivation layer 170 including the contact hole CNT. The transparent electrode layer contacts the drain electrode DE through the contact hole CNT. The transparent electrode layer is patterned to form a pixel electrode 180 which is in contact with the drain electrode DE. The pixel electrode 180 is electrically connected to the switching element TFT.

According to the present invention, the reliability of deposition of the gate metal layer 130 and the subsequent film can be improved by removing the seed metal layer 130 of the sidewall surface 113 before the electroless plating process using the etchant.

When the electroless plating process is performed in a state where the seed metal layer 130 is formed on the sidewall surface 113 and the bottom surface 114 of the trench 112 and the seed metal layer 130 of the sidewall surface 113 is formed, The thickness of the gate metal layer 140 formed to be substituted from the seed metal layer 130 of the bottom surface 114 is larger than the thickness of the gate metal layer 140 formed by substitution from the seed metal layer 130 of the bottom surface 114, The gate metal layer 140 of the region is formed rising from the trench 112. The above problems can be solved by using the etching solution of the present invention, and the reliability of the process can be improved.

Example 2

FIGS. 7 to 12 are cross-sectional views illustrating a method of manufacturing a display substrate according to a second embodiment of the present invention.

The manufacturing method of the display substrate according to the second embodiment of the present invention is the same as the manufacturing method of the display substrate according to the first embodiment of the present invention except for the step of forming the trench and the step of forming the metal seed, Are denoted by the same reference numerals and will be denoted by the same names, and a detailed description thereof will be omitted.

Referring to FIG. 7, an adhesive metal layer 10 and a photoresist pattern 120 are sequentially formed on an insulating substrate 110.

The adhesive metal layer 10 is a metal layer for improving adhesion between the insulating substrate 110 and the photoresist pattern 120. Examples of the material for forming the adhesive metal layer 10 include copper (Cu), molybdenum (Mo), and the like. The photoresist pattern 120 exposes the adhesive metal layer 10 in the gate region GA of the insulating substrate 110.

Referring to FIG. 8, the metal pattern 12 is formed by removing the adhesive metal layer 10 of the gate region GA using the photoresist pattern 120 as an etch stopping layer. The insulating substrate 110 of the gate region GA exposed through the metal pattern 12 is etched using the photoresist pattern 120 and the metal pattern 12 as an etch stopper to form trenches 112 ).

9, a seed metal layer 130 is deposited on the insulating substrate 110 on which the photoresist pattern 120, the metal pattern 12, and the trenches 12 are formed.

The seed metal layer 130 is formed on the surface of the photoresist pattern 120, that is, the flat surface and the etched surface of the photoresist pattern 120. The seed metal layer 130 is formed on the sidewall 113 of the trench 112. The seed metal layer 130 may be formed on the bottom surface 114 of the trench 112.

Referring to FIG. 10, the seed metal layer 130 and the photoresist pattern 120 formed on the photoresist pattern 120 are removed. The seed metal layer 130 formed on the foamed resist pattern 120 may be removed from the insulating substrate 110 by removing the photoresist pattern 120.

Then, the metal pattern 12 is removed.

Accordingly, only the seed metal layer 130 formed on the sidewall surface 113 and the bottom surface 114 of the trench 112 remains on the insulating substrate 110.

Referring to FIG. 11, the seed metal layer 130 remaining on the insulating substrate 110 is etched using an etching solution. The etchant may remove the seed metal layer 130 formed on the sidewall 113 of the trench 112 in the remaining seed metal layer 130. Since the etchant is substantially the same as the etchant of low etch rate according to the present invention described above, the detailed description will not be repeated. Thus, a buffer layer 132 is formed on the bottom surface 114.

Referring to FIG. 12, a gate metal layer 140 is deposited on the insulating substrate 110 on which the buffer layer 132 is formed. The gate metal layer 140 is deposited on the insulating substrate 110 by electroless plating (ELP). The buffer layer 132 and the gate metal layer 140 are formed in the trench 112 so that the gate pattern G including the gate lines and the gate electrodes is formed on the insulating substrate 110.

In the manufacturing method of the display substrate according to the second embodiment, the surface of the buffer layer 132 is cleaned, the surface of the gate metal layer 140 is cleaned, and / or the surface of the buffer layer 132 is removed by removing the thin film containing impurities formed on the surface using the etching solution. Or the surface of the data metal layer (not shown) can be cleaned.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It will be understood.

110: insulating substrate 112: trench
113: side wall surface 114: bottom surface
120: photoresist pattern 130: seed metal layer
132: buffer layer 140: gate metal layer
TFT: thin film transistor G: gate pattern
160: active pattern SE: source electrode
DE: drain electrode 180: pixel electrode

Claims (12)

Forming a trench in the gate region of the insulating substrate;
Forming a metal seed in the trench;
The metal seed formed on the sidewall of the trench is removed by using a low etch rate etchant including hydrogen peroxide (H2O2), an additive for suppressing the reaction of hydrogen peroxide and excess water, Forming a buffer layer on a bottom surface formed lower than the surface of the buffer layer;
Forming a gate metal layer in the trench in which the buffer layer is formed to form a gate pattern including a gate line and a gate electrode;
Forming a data line crossing the gate line, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode, on an insulating substrate on which the gate pattern is formed; And
And forming a pixel electrode to be in contact with the drain electrode,
The step of forming the trenches
Forming an adhesive metal layer on the insulating substrate;
Forming a photoresist pattern on the adhesive metal layer to expose the adhesive metal layer of the gate region;
Removing the adhesive metal layer of the gate region using the photoresist pattern as an etch stopping film; And
And etching the exposed insulating substrate to form the trench. The method of claim 1, wherein the additive
At least one compound selected from the group consisting of a persulfate compound and an azole compound. The method of claim 2, wherein the additive
Characterized in that it comprises at least one compound selected from sodium and sulfuric acid (SPS), potassium and sulfuric acid (PPS) and benzotriazole (BTA). The method of manufacturing a display substrate according to claim 1, wherein the etching speed of the metal seed by the low etching rate etch is 40 ANGSTROM / min to 600 ANGSTROM / min. The method of claim 1, wherein the low etch rate etchant
1 weight percent to 10 weight percent hydrogen peroxide;
1 weight percent to 10 weight percent of the additive; And
And from 80 to 95 weight percent of said water. 2. The method of claim 1, wherein forming the trench comprises:
Forming a photoresist pattern on the insulating substrate so as to expose the insulating substrate of the gate region; And
And etching the insulating substrate of the gate region using the photoresist pattern as an etching mask to form the trench. 7. The method of claim 6, wherein forming the metal seed
Depositing a seed metal layer on the photoresist pattern and the insulating substrate on which the trench is formed; And
And removing the photoresist pattern to leave the seed metal layer on the bottom and sidewall surfaces of the trench. delete The method of claim 1, wherein forming the metal seed
Depositing a seed metal layer on the photoresist pattern and the insulating substrate on which the trench is formed; And
And removing the photoresist pattern and the patterned adhesive metal layer to leave the gate metal layer on the bottom surface and the sidewall surface of the trench. The method of manufacturing a display substrate according to claim 1, further comprising the step of surface-cleaning the buffer layer formed in the trench using the low etch rate etchant. The method of claim 1, wherein forming the gate pattern
Further comprising the step of surface-cleaning the gate metal layer using the low etch rate etchant. The method of claim 1, wherein forming the drain electrode
Further comprising the step of surface cleaning the data metal layer forming the drain electrode using the low etch rate etchant.

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