KR101520654B1 - Method for data rate matching - Google Patents

Abstract

This document discloses a data rate matching method, and more specifically, a method for performing rate matching using two or more parameters.

As an example of the rate matching method disclosed in this document, a method is disclosed in which a first indication parameter for selecting one or more bits for an input bit stream and a second indication parameter for canceling a selection according to the first indication parameter or for further selecting unselected bits Selecting a bit using an indication parameter, and processing the selected bit according to a rate matching mode to generate an output bit stream.

By using this rate matching method, high-speed processing is possible through a simple operation, and the position of a target bit can be efficiently determined through two or more instruction parameters. Thus, the amount of computation can be reduced or better performance can be obtained.

Rate matching, indicator

Description

[0001] The present invention relates to a method for data rate matching,

This document relates to a data rate matching method and, more particularly, to a method for performing rate matching using two or more parameters.

It is practically impossible to receive a signal with no distortion or noise when receiving a signal transmitted from a transmitting apparatus through a wireless network in a mobile communication system. Therefore, various techniques for overcoming this have been proposed, and one of the representative ones is an error control coding technique. In the case of a CDMA mobile communication system which is one of the mobile communication systems, for example, a turbo code and a convolutional code are used as an error control coding technique.

That is, channel coding may be used to correct errors occurring in the process of transmitting data. At this time, additional parity data other than the information to be transmitted is generated. The error correction capability of the channel coding code is improved as the ratio of the parity data to the information to be transmitted is higher. That is, as the code-rate of the bit stream to be transmitted decreases, error recovery performance improves.

However, if the code rate is lowered, the amount of parity data is increased compared to the information to be transmitted in a communication system using limited resources, thereby lowering transmission efficiency. Therefore, there is a need for a rate matching method that can flexibly adjust the coding rate to meet the communication conditions to be transmitted.

The UMTS standard (RELEASE '99) completed by 3GPP performs rate matching on the coded bits output after channel coding. Generally, the number of coded bits output after channel coding and the total number of bits of a unit (TU) transmitted on the radio are mostly inconsistent. The rate matching is an operation for matching the number of the coded bits to the total number of bits required on the radio through repetition and puncturing on the coded bits. This rate matching can be used in various standards such as the HSDPA standard.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for performing rate matching using two or more instruction parameters. It is also an object to provide a method of determining two or more instruction parameter values used to perform the rate matching.

According to an aspect of the present invention, there is provided a rate matching method in a mobile communication system, including: receiving a first indication parameter for selecting one or more bits for an input bit string; Selecting a bit using a secondary indication parameter for further selecting an unselected bit, and processing the selected bit according to a rate matching mode to generate an output bit stream.

In another aspect of the present invention, there is provided a rate matching method in a mobile communication system including a rate matching block in which a predetermined input bit string is input, the rate matching method comprising: And puncturing or repeating the bits of the designated location according to the rate matching mode.

In the above-described embodiments, the primary indication parameter and the secondary indication parameter may be determined in consideration of at least one of the number of bits of the input bit string and the number of bits of the output bit string. The secondary indication parameter may be determined based on the primary indication parameter value.

Further, the primary indication parameter and the secondary indication parameter may indicate a selection period. The secondary instruction mode may be used to indicate selection or selection of a bit using the secondary indication parameter.

The rate matching mode may be a puncturing mode when the size of the input bit stream is larger than the size of the output bit stream and a repeated mode when the size of the input bit stream is smaller than the size of the output bit stream.

Rate matching can be performed in an effective and simple manner through the rate matching method disclosed in this document. In addition, a position or a target bit is determined through a simple counter or conditional statement for an input bit stream, and puncturing or repetition is performed based on the target bit, thereby enabling high-speed processing through a simple operation. In addition, two or more instruction parameters can be used to efficiently position the system. Therefore, the computation amount can be reduced or better performance can be obtained when performing puncturing or iteration.

In particular, compared with the case where the required coding rate is adjusted by puncturing or repetition using a certain pattern, there is an effect that is easy to apply to the size and the coding rate of various input bit strings. Further, puncturing or repetition can be performed by a simple formula or a combination of algorithms for application to various cases, thereby reducing the complexity of rate matching.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The detailed description set forth below in conjunction with the appended drawings is intended to illustrate exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced. The following detailed description includes specific details for a better understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without these specific details. For example, in the following description, certain terms are mainly described, but they need not be limited to these terms, and they may have the same meaning when they are referred to as arbitrary terms.

In some instances, well-known structures and / or devices may be omitted to avoid obscuring the concepts of the present invention, and may be represented in block diagrams and / or flowchart diagrams centered on the core functions of each structure and / or device have. In the following description, the same components are denoted by the same reference numerals throughout the specification.

This document relates to a rate matching method, that is, a method of generating a bit stream of a code-rate to be obtained by performing a puncturing or repetition technique on a channel-encoded bit stream. Generally, a bit position in a predetermined bit or bit string is selected to perform puncturing or repetition on a bit string, and puncturing or repetition is performed on selected bits to adjust bit string size. The present invention is characterized in that selection is performed using at least three parameters in selecting a bit for performing puncturing or repetition in performing rate matching. For convenience of explanation, a bit to be punctured or repeated is referred to as a target bit.

Indication parameters can be used to select the target bit for puncturing or repetition. That is, an instruction parameter value is determined in consideration of at least one of a system condition, a coding rate, an input bit string and an output bit string, and it is determined according to the determined instruction parameter value which bit of the input bit string is determined as a target bit . Here, the indication parameter may be a selection period value for the input bit stream. For example, when the instruction parameter is 3, the bits can be selected at intervals of 3 in the input bit stream.

According to the embodiments disclosed in this document, it is not necessary to select a target bit so as to be a bit string satisfying a code rate that is necessarily obtained by selection by one parameter. The target bit is selected by a number close to the required bit string size through the primary indication parameter and the bit string of the coding rate to be obtained by correcting the selection result of the primary indication parameter through the secondary indication parameter or more is accurately generated .

In other words, it is possible to cancel the selection of the selected bit by considering the bits selected through the previous or the first instruction parameter through the second or more instruction parameters, or to select a bit stream of a code rate to be obtained by further selecting unselected bits Can be accurately generated. For example, if the number of bits to be selected by the primary indication parameter is larger than the number of bits according to the code rate to be obtained, at least one of the selected bits is deselected using a secondary or higher instruction parameter. If the number of bits is less than the number of bits according to the code rate to be obtained, at least one of the bits that are not selected is further selected using the second or more instruction parameters.

1 is a flow diagram illustrating a method for performing rate matching using two or more indication parameters in accordance with one embodiment of the present invention.

Hereinafter, a rate matching method for selecting a target bit using the plurality of parameters described above with reference to FIG. 1 will be described in more detail.

First, in step S100, a bit string is input. At this time, the bit stream may be a bit on which channel coding is performed. In step S110, the rate matching mode, the primary indication parameter, the secondary indication parameter, the number of necessary target bits, and the like are determined in consideration of the size of the input bit string and the size of the output bit string.

Then, some of the bits included in the input bit string are selected through the primary indication parameter determined in step S120. Then, in step S130, the number of bits thus selected is compared with the number of required bits to determine whether rate matching can be performed correctly or whether correction is required. That is, if the number of selected bits and the number of target bits are the same, since the rate matching can be accurately performed, puncturing or repetition is performed on the bits selected as the primary indication parameter in step S150.

However, if the number of selected bits and the number of target bits are not the same, additional correction is required on the selected bits. More specifically, if the number of selected bits is smaller than the number of target bits, a bit is further selected through the secondary indication parameter in step S140. If the number of selected bits is greater than the target bit number, the selection of the bit selected as the primary indication parameter is canceled through the secondary indication parameter in step S145. If the number of bits selected through step S140 or step S145 becomes equal to the number of target bits required, puncturing or repetition is performed on the bits selected as the primary indication parameter in step S150.

However, even in this case, if the number of selected bits and the number of target bits are not the same, an additional correction is required for the selected bits. That is, it is possible to perform the correction for the selected bits by the above-described step S140 or step S145. In this case, when the correction is performed again, the instruction parameter value of the third or higher order than the second order parameter may be used. That is, when the bit selection correction is performed n times, the n + 1 < th > order indication parameter value can be defined and the bit selection or the bit selection can be canceled by using the (n + 1)

It is possible to determine the above-mentioned two or more instruction parameters and basic parameters before performing the rate matching, and perform rate matching through the determined parameters. Hereinafter, an example of a method of setting the initial values of the parameters and the like described in step S110 will be described.

>

) 반복 모드, 입력 비트 수가 출력 비트 수보다 크면 (

>

) 펑처링 모드로 결정된다. 이와 같은 레이트 매칭 모드를 결정하기 앞서서 또는 결정할 때 선택되는 대상 비트의 수와 전체 입력 비트열에 대한 전체 반복 횟수를 결정할 수 있다.One of the parameters of the rate matching is a rate matching mode. That is, the mode of the rate matching may be divided into a puncturing mode and a repetitive mode depending on whether puncturing or repetition is performed on an input bit stream. Basically, if the number of input bits is smaller than the number of output bits (

>

) Repeat mode, if the number of input bits is greater than the number of output bits (

>

) The puncturing mode is determined. The number of target bits and the total number of iterations for the entire input bit stream can be determined before or in determining the rate matching mode.

In the case of the repetitive mode, all repetitions of the entire input bit string are possible up to the number of bits, that is, the number of output bits according to the code rate to be obtained. If it is not possible to match the whole iteration, the target bit is selected and the iteration is performed only for the selected bit. For example, assume that the number of bits in the input bit stream is 12 and the number of output bits is 41. In this case, at least three complete iterations can be done. That is, if three iterations are performed, a total of 36 bits will be generated and an additional 5 bits are needed to match the number of output bits. That is, the number of target bits to be selected at this time will be 5 bits.

As another example, assume that the number of bits of the input bit string is 12 and the number of output bits is 43. In this case, at least three complete iterations can be done. At this time, when the method is applied in a repetitive mode according to the above-described method, an additional 7 bits are further needed to match the number of output bits. That is, the number of target bits to be selected will be a total of 7 bits.

However, if the number of bits to be repeated to perform rate matching is greater than half the number of input bits, one full iteration may be added and the rate matching mode may be determined to be a puncturing mode to perform rate matching.

For example, it is assumed that the number of bits of the input bit string as described above is 12 and the number of output bits is 43. In this case, according to the present embodiment, if one full iteration is performed to perform a total of four iterations, a total of 48 bits will be generated and five bits must be punctured to fit the number of output bits. That is, the number of target bits to be selected at this time will be 5 bits.

That is, when the number of target bits is larger than half of the number of input bits, the case of puncturing mode is more effective than the case of applying it in the repeat mode in the same situation because the number of bits to be selected can be reduced.

In the puncturing mode, the number of bits to be selected can be determined by subtracting the number of bits of the input bit string from the number of bits according to the code rate to be obtained. In this case, if the total number of repetitions described above is to be determined, it may be fixed at one time.

Hereinafter, an example of setting two instruction parameter values will be described, but it will be obvious that a target bit can be selected by setting three or more instruction parameter values if necessary.

A method of determining a primary indication parameter with another parameter of rate matching will be described. The primary indication parameter may be the selection period value as described above. That is, an integer value corresponding to a value obtained by dividing the total number of input bits by the number of target bits is selected as the number of target bits, so that the bits can be selected in a cycle according to the first instruction parameter. Here, the corresponding integer value means that the value obtained by dividing the number of input bits by the number of selected bits is a prime number such as rounding, rounding, truncation, a maximum integer value not exceeding a divided value, and a minimum integer value exceeding a divided value. You can decide.

A method for determining secondary indication parameters with other parameters of rate matching will be described. The secondary indication parameter can be the selection period value as the primary indication parameter. However, it is preferable that the difference from the primary indication parameter is determined to be larger than the primary indication parameter. A large selection period may mean reducing the number of bits selected for a limited input bit stream.

As an example of determining the secondary indication parameter, an integer value corresponding to a value obtained by dividing the value obtained by subtracting the number of bits selected by the primary indication parameter from the number of input bits by the number obtained by dividing the required number of bits by the number of selected bits in the primary selection Can be determined by the secondary instruction parameter value. That is, a rough selection period for the secondary indication parameter may be obtained by dividing the number of remaining bits not selected by the primary indication parameter by the number of bits that exceeds or is smaller than the required number of target bits.

Here, a value obtained by subtracting the number of bits selected as the primary indication parameter from the number of necessary bits required is used to determine whether correction by the secondary indication parameter is necessary, additional selection is made if necessary, or a part of bits selected by the primary indication parameter You can decide if you want to opt out.

For example, if a value obtained by subtracting the number of bits selected as the primary indication parameter from the required number of bits required is 0, the rate matching can be performed only with the primary indication parameter without the secondary indication parameter. When the value obtained by subtracting the number of bits selected as the primary indication parameter from the number of necessary target bits is greater than 0, the base station determines to additionally select bits not selected as the primary indication parameter through the secondary indication parameter, If the value obtained by subtracting the number of bits selected by the primary indication parameter from the number is less than 0, it may be decided to deselect the selection bits with respect to the selection bits in the primary selection through the secondary indication parameter.

Table 1 below shows a method of determining each of the above three parameters in an algorithmic manner.

parameter( Parameter ) construction( syntax ) Mode decision

,
n _select = L _output - L _input *rpt;
If n _select > (L _input /2),
Mode= Puncturing,
rpt = rpt + 1,
n _select = L _input - n _select ;
Otherwise,
Mode = Puncturing,
rpt = 1,
n _select = L _{input -} L _output ;
If L _input < L _output ,
Mode = Repetition,
rpt =

,
n _select = L _output - L _input * rpt ;
If n _select > ( L _input / 2),
Mode = Puncturing,
rpt = rpt + 1,
n _select = L _input - n _select ;
Otherwise,
Mode = Puncturing,
rpt = 1,
n _select = L _{input -} L _output ;
First selection period parameter prid ₁ = rounding ( L _input / n _select ) off to the nearest integer
If prid ₁ &Lt; 2, prid ₁ = 2
Second selection period parameter temp ₁ = L _input -

,
temp ₂ = n _select -

,
prid ₂ =

If temp ₂ = 0, use only first selection
If temp _{2 &} gt; 0, SIM = Selection
Otherwise, SIM = De-selection

는 입력 비트 수,

는 출력 비트 수,

는 펑처링 또는 반복을 수행하기 위해 선택하는 대상 비트 수, rpt는 전체 입력 비트열에 대한 전체 반복 횟수를 나타낸다. 여기서, rpt는 반복하는 경우 반복 횟수를 나타내며 특히 LLR(log likelihood ratio) 값을 결합하는 횟수로 볼 수 있다. 그리고, prid ₁ 은 1차 지시 파라미터, prid ₂ 는 2차 지시 파라미터, SIM은 2차 지시 모드 즉, 2차 지시 파라미터를 통해 추가 선택을 수행할지 선택을 해지할 지 여부를 지시하는 정보이다.Table 1

Is the number of input bits,

Is the number of output bits,

Denotes the number of bits to be selected to perform puncturing or repetition, and rpt denotes the total number of repetitions of the entire input bit stream. Here, rpt represents the number of repetitions in the case of repetition, in particular, the number of times of combining the log likelihood ratio (LLR) values. Prid ₁ is a primary indication parameter, prid ₂ is a secondary indication parameter, and SIM is secondary indication mode, that is, information indicating whether or not to perform addition selection through a secondary indication parameter.

Hereinafter, a method for selecting a target bit to perform rate matching will be described based on initial parameters set by the above-described method. Likewise, an example of selecting a target bit using two instruction parameters will be described, but it will be obvious that a target bit can be selected with three or more instruction parameters if necessary.

First, selection is made with the primary indication parameter as described above, and correction is made with respect to selection with the primary indication parameter through the secondary indication parameter. If the number of bits selected by the primary indication parameter is smaller than the number of required bits required, the secondary indication parameter may be additionally selected. If the number of bits selected by the primary indication parameter is larger than the required number of required bits, Bit &lt; / RTI &gt; Thus, it is possible to determine whether to further select the secondary indication parameter or to deselect the primary selection as the secondary indication mode. That is, in the former case, the secondary instruction mode may be selected as the selection, and in the latter case, the secondary instruction mode may be selected as the selection termination.

For example, when the secondary instruction mode is selected, a method of selecting a target bit will be described. First, a bit is selected with respect to the input bit string in a cycle according to the primary indication parameter. If the selected number of bits does not meet the required number of bits required, bits are additionally selected in cycles according to the secondary indication parameter for the bits not selected as the primary indication parameter. At this time, the bit is selected until the number of required target bits is selected.

If the secondary instruction mode is selected, a method of selecting a target bit will be described. First, a bit is selected with respect to an input bit string in a cycle according to a primary indication parameter. If the selected number of bits exceeds the required number of target bits, the bit selection is canceled at a cycle according to the secondary indication parameter for the primary indication parameter selected bits. At this time, the bit selection is canceled until the required number of target bits is selected.

2 is a diagram for explaining an example of a method of selecting a target bit according to an embodiment of the present invention.

In FIG. 2, the bit stream at the top represents the input bit stream and the bit stream at the bottom represents the rate target bit stream. Referring to FIG. 2, it can be seen that bits are selected at intervals of 2 by 2 in the primary indication parameter value. That is, if the index of the bit selected by the primary selection is listed, it will be 0, 2, 4, 6, 8, 10, 12,

Assuming that the number of bits selected by the primary indication parameter is larger than the required number of target bits, some of the bits selected by the secondary indication parameter should be canceled. Referring to FIG. 2, it is confirmed that the bits selected by 6 intervals are canceled in the secondary indication parameter value. That is, if the index of the bit to be deselected by the secondary selection is listed, it will be 0, 6, 12, and so on.

That is, if the bit index of the target bit to be finally selected is listed, it will be 2, 4, 8, 10, 14, etc. as shown in the lower part of FIG. If the rate matching mode is iterative, the selected target bits will be repeated to generate an output bit stream, and if the rate matching mode is punctured, the selected target bits will be punctured to generate an output bit stream.

In the case where the secondary instruction mode is selected, another method of selecting a target bit can be performed by a single determination rather than a method over the two-step determination described above. That is, a bit that does not correspond to a period of a product of a primary indication parameter and a secondary indication parameter is satisfied for a period corresponding to the primary indication parameter with respect to the input bit string, and the number of necessary target bits is selected.

That is, for the sake of convenience of description, the present invention is described based on the selection of the first instruction parameter and the second instruction parameter. However, Therefore, it can be done by one selection process.

2 again, the value of the secondary indication parameter is determined to be 3, and the value of the primary indication parameter (2) and the secondary indication parameter 6 = 2 * 3) is selected by the number of necessary target bits.

Table 2 below shows a method of determining the target bits described above in an algorithmic manner. The first example shows the case where two steps are performed, the second example shows one case where one step is performed, and the third example shows a case where the first method and the second method are mixed. to be. There may be some differences in the results of the three methods, but there will be no significant difference in overall performance.

Output bit stream generation
using 2 selection steps
(When sequentially performing the selection of the primary indication parameter and the selection of the secondary indication parameter) s = 0, p = 0; // dummy variable for counting
If ( SIM = = Selection)
{
for (i = 0 to L _input -1)
{
if (i% prid ₁ = 0)
{
select this bit ,
p = p + 1;
}
else
{
if (s% prid ₂ = 0 && p < n _select )
{
select this bit ,
p = p + 1;
}
s = s + 1;
}
}
}
Else ( SIM = De-selection)
{
for (i = 0 to L _input -1)
{
if (i% prid ₁ = 0)
{
select this bit ,
p = p + 1;
}
else
{
if (s% prid ₂ = 0 && p < n _select )
{
de - select this bit ,
p = p - 1;
}
s = s + 1;
}
}
}
Output bit stream generation
using 1 selection step
(When the selection is performed while simultaneously considering the primary indication parameter and the secondary indication parameter) s = 0, p = 0; // dummy variable for counting
If ( SIM = = Selection)
{
for (i = 0 to L _input -1)
{
if ((% prid ₁ == 0 || s% prid ₂ = = 0) && p < n _select )
{
select this bit ,
p = p + 1;
}
s = s + 1;
}
}
Else ( SIM = De-selection)
{
for (i = 0 to L _input -1)
{
if (i% prid ₁ = = 0 && i% ( prid ₁ * prid ₂ )! = 0 && p < n _select )
{
select this bit ,
p = p + 1;
}
}
}
Output bit stream generation
using 2 selection steps for SIM == Selection and 1 selection step for SIM == De-selection
(When the secondary instruction mode is the selection mode, the selection of the primary instruction parameter and the selection of the secondary instruction parameter are sequentially performed, and when the secondary instruction mode is the selection release, the primary instruction parameter and the secondary instruction parameter If the selection is performed considering simultaneously) s = 0, p = 0; // dummy variable for counting
If ( SIM = = Selection)
{
for (i = 0 to L _input -1)
{
if (i% prid ₁ = 0)
{
select this bit , p = p + 1;
}
else
{
if (s% prid ₂ = 0 && p < n _select )
{
select this bit , p = p + 1;
}
s = s + 1;
}
}
}
Else ( SIM = De-selection)
{
for (i = 0 to L _input -1)
{
if (i% prid ₁ = = 0 && i% ( prid ₁ * prid ₂ )! = 0 && p < n _select )
{
select this bit , p = p + 1;
}
}
}

는 입력 비트 수,

는 출력 비트 수,

는 펑처링 또는 반복을 수행하기 위해 선택하는 대상 비트 수, prid ₁ 은 1차 지시 파라미터, prid ₂ 는 2차 지시 파라미터, SIM은 2차 지시 모드를 나타내는 점은 표 1의 경우와 동일하다. 추가로 i는 입력 비트열의 비트 당 할당되는 인덱스를 나타내고, s는 입력 비트열에서 1차 선택 후 남은 비트 당 할당되는 인덱스를 나타내며, p는 선택된 비트 수를 나타낸다. 여기서, i는 0부터

-1까지의 정수 값이 될 수 있다. Table 2

Is the number of input bits,

Is the number of output bits,

Prid ₁ indicates a primary indication parameter, prid ₂ indicates a secondary indication parameter, and SIM indicates a secondary indication mode. In addition, i denotes an index allocated per bit of the input bit string, s denotes an index allocated to the remaining bits after the primary selection in the input bit string, and p denotes the number of selected bits. Here, i is 0

And may be an integer value of up to -1.

Rate matching can be performed using the target bits selected by the above-described method. That is, when the rate matching mode is the iterative mode, it is possible to generate the output bit stream by repeating the target bits with the entire iterations or separately. If the rate matching mode is a puncturing mode, the target bits can be erased or punctured to generate an output bit stream.

A rate matching method that can be applied when channel coding is performed with a tail bit convolutional code having a mother code rate of 1/3 will be described as a specific embodiment of the present invention. In this case, the rate matching may be performed as a rate matching module with a separate rate matching module or may be performed by adding a simple algorithm to the channel coding module.

3 is a diagram for explaining an example of a method of selecting a target bit according to an embodiment of the present invention.

)가 123(=41*3) 비트이고 출력 비트 수 (

)가 72비트인 경우 레이트 매칭을 수행하기 위한 대상 비트를 선택하는 방법을 도시하고 있다.3, the number of information bits is 41 and the number of input bits (

) Is 123 (= 41 * 3) bits and the number of output bits (

) Is 72 bits, a method for selecting a target bit for rate matching is shown.

)는 입력 비트 수와 출력 비트 수의 차(

-

)로 51 비트가 될 것이다. 1차 지시 파라미터 (prid ₁ )는

에 따라 2(=

)가 되고, temp1=123-

=62, temp2=51-

=-10 이므로 2차 지시 파라미터(prid ₂ )는

=6이 될 것이다. temp2 값이 0보다 작으므로 2차 지시 모드(SIM)는 선택 해지가 된다. 즉, 선택된 비트들 중에서 6주기로 선택을 해지해야 하므로 결국 1차 지시 파라미터와 2차 지시 파라미터의 곱(prid ₁ * prid ₂ )에 해당하는 12 주기로 입력 비트 열의 선택을 해지할 것이다. When the above-mentioned parameter values are defined, the rate matching mode will be a puncturing mode since the number of input bits is larger than the number of output bits. Then, the number of target bits (

) Is the difference between the number of input bits and the number of output bits (

-

) Will be 51 bits. The primary indication parameter ( prid ₁ )

2 (=

), And temp1 = 123-

= 62, temp2 = 51-

= -10, the secondary indication parameter ( prid ₂ ) is

= 6. Since the value of temp2 is less than 0, the second instruction mode ( SIM ) is selected. That is, since the selection must be canceled in six cycles among the selected bits, the selection of the input bit string will be canceled in 12 cycles corresponding to the product ( prid ₁ * prid ₂ ) of the primary indication parameter and the secondary indication parameter.

Referring to FIG. 3, the indexes of bits to be selected according to the primary indication parameter are listed up to 122 including 0, 2, 4, 6, 8, 10, 12, That is, since the total number of selected bits becomes 62, it exceeds the number of necessary target bits, and thus the selection must be canceled through the secondary indication parameter. In this case, if the index of the bit to be selected by the secondary indication parameter is listed, it will be 11 to 120 including 0, 12, and 24. Therefore, the target bit to be finally selected will be a hatched bit at the top of FIG. If the index of the target bit is represented, it will be 51 in total including 122, including 2, 4, 6, 8, 10, and 14.

Since the rate matching mode of this embodiment is puncturing, if the selected target bit is punctured, the output bit string to be output will be as shown in the lower part of FIG. If the index of the bit corresponding to the output bit string is listed, it will be 121 including 0, 1, 3, 5, 7, 9, 11, The number of bits of the output bit string becomes 72 bits, so that it can be confirmed that the rate matching is correctly performed.

4 is a diagram for explaining an example of a method of selecting a target bit according to an embodiment of the present invention.

)가 120(=40*3) 비트이고 출력 비트 수(

)가 72비트인 경우 레이트 매칭을 수행하기 위한 대상 비트를 선택하는 방법을 도시하고 있다.4 shows that the number of information bits is 40 and the number of input bits (

) Is 120 (= 40 * 3) bits and the number of output bits (

) Is 72 bits, a method for selecting a target bit for rate matching is shown.

)는 입력 비트 수와 출력 비트 수의 차(

-

)로 48 비트가 될 것이다. 1차 지시 파라미터(prid ₁ )는

에 따라 3(=

)가 되고, temp1=120-

=80, temp2=48-

=8 이므로 2차 지시 파라미터(prid ₂ )는

=10이 될 것이다. temp2 값이 0보다 크므로 2차 지시 모드(SIM)는 추가 선택이 된다. 즉, 선택되지 않은 비트 중에서 10 주기로 선택할 것이다.When the above-mentioned parameter values are defined, the rate matching mode will be a puncturing mode since the number of input bits is larger than the number of output bits. Then, the number of target bits (

) Is the difference between the number of input bits and the number of output bits (

-

) Will be 48 bits. The primary indication parameter ( prid ₁ )

3 (=

), And temp1 = 120-

= 80, temp2 = 48-

= 8, the secondary indication parameter ( prid ₂ ) is

= 10. Since the temp2 value is greater than zero, the secondary instruction mode ( SIM ) is an additional selection. That is, it will select 10 cycles out of the unselected bits.

Referring to FIG. 4, the indexes of the bits to be selected according to the primary indication parameter are listed up to 117 including 0, 3, 6, 9, 12, and 15. That is, the total number of selected bits becomes 40, which is less than the required number of target bits, and thus, the secondary selection parameter will be further selected. In this case, if the indexes of the bits selected by the secondary indication parameter are listed, the number of bits including 1 and 16 will be 8 up to 106. Therefore, the target bit to be finally selected will be a hatched bit at the top of FIG. If the index of the target bit is represented, it will be 48 including 117, including 0, 1, 3, and 6.

Since the rate matching mode of this embodiment is puncturing, if the selected target bit is punctured, the output bit string to be output will be as shown in the lower part of FIG. If the index of the bit corresponding to the output bit string is listed, it will be 119 including 2, 4, 5, 7, 8, 10, 11, The number of bits of the output bit string becomes 72 bits, so that it can be confirmed that the rate matching is correctly performed.

5 is a diagram for explaining an example of a method of selecting a target bit according to an embodiment of the present invention.

)가 99(=33*3) 비트이고 출력 비트 수(

)가 144비트인 경우 레이트 매칭을 수행하기 위한 대상 비트를 선택하는 방법을 도시하고 있다.5 shows that the number of information bits is 33 and the number of input bits (

) Is 99 (= 33 * 3) bits and the number of output bits (

) Is 144 bits, a method of selecting a target bit for rate matching is shown.

)는 입력 비트 수와 출력 비트 수의 차로 45 비트가 될 것이다. 1차 지시 파라미터(prid ₁ )는

에 따라 2(=

)가 되고, temp1=99-

=50, temp2=45-

=-4 이므로 2차 지시 파라미터(prid ₂ )는

=12가 될 것이다. temp2 값이 0보다 작으므로 2차 지시 모드는 선택 해지가 된다. 즉, 선택된 비트들 중에서 12주기로 선택을 해지해야 하므로 결국 1차 지시 파라미터와 2차 지시 파라미터의 곱에 해당하는 24 주기로 입력 비트 열의 선택을 해지할 것이다. When the above-mentioned parameter values are defined, the rate matching mode will be a repeat mode since the number of input bits is larger than the number of output bits. Then, the total number of times of repetition ( rpt ) becomes 1 and the number of target bits (

) Will be 45 bits as the difference between the number of input bits and the number of output bits. The primary indication parameter ( prid ₁ )

2 (=

), And temp1 = 99-

= 50, temp2 = 45-

= -4, the secondary indication parameter ( prid ₂ ) is

= 12. Since the temp2 value is less than 0, the secondary instruction mode is selected. That is, since the selection must be canceled in 12 cycles among the selected bits, the selection of the input bit string will be canceled in 24 cycles corresponding to the multiplication of the primary indication parameter and the secondary indication parameter.

Referring to FIG. 5, if the indexes of the bits to be selected are listed according to the primary indication parameter, they will be up to 98 including 0, 2, and 4. That is, since the total number of selected bits becomes 50, it is larger than the required number of target bits, and therefore, the secondary indication parameters will be selected for termination. In this case, if the indexes of the bits selected by the secondary indication parameter are listed, the number of bits including 0 and 24 will be 5 up to 96. Therefore, the target bit to be finally selected will be a hatched bit at the top of FIG. If the index of the target bit is represented, it will be 45, including 2 and 4, up to 98.

Since the rate matching mode for this embodiment is repetitive, the output bit string to be output when the selected target bit is repeated will be as shown in the lower part of FIG. If the index of the bit corresponding to the output bit string is listed, the entire bit from 0 to 98 will be included, and an additional 98 including 2 and 4 will be included. The number of bits of the output bit string becomes 144 bits, and it can be confirmed that the rate matching is performed correctly.

It is clear that the claims that are not expressly cited in the claims may be combined to form an embodiment or be included in a new claim by an amendment after the application.

Embodiments in accordance with the present invention may be implemented by various means, for example, hardware, firmware, software, or a combination thereof. In the case of hardware implementation, the rate matching method according to an embodiment of the present invention may include one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices, field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and the like.

In the case of firmware or software implementation, the rate matching method according to an embodiment of the present invention may be implemented in the form of a module, a procedure, a function, or the like for performing the functions or operations described above. The software code can be stored in a memory unit and driven by the processor. The memory unit may be located inside or outside the processor, and may exchange data with the processor by various well-known means.

It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the above description should not be construed in a limiting sense in all respects and should be considered illustrative. The scope of the present invention should be determined by rational interpretation of the appended claims, and all changes within the scope of equivalents of the present invention are included in the scope of the present invention.

1 is a flow diagram illustrating a method for performing rate matching using two or more indication parameters in accordance with one embodiment of the present invention.

2 is a view for explaining an example of a method of selecting a target bit according to an embodiment of the present invention;

3 is a diagram for explaining an example of a method of selecting a target bit according to an embodiment of the present invention;

4 is a diagram for explaining an example of a method of selecting a target bit according to an embodiment of the present invention;

5 is a view for explaining an example of a method of selecting a target bit according to an embodiment of the present invention;

Claims (7)

In the rate matching method,

An input bit string having a bit size of &quot;

Determining a rate matching mode by comparing output bit streams having a bit size of &lt; RTI ID = 0.0 &gt; Based on the following Equation (1), a primary indication parameter

And determines, for the input bit string,

Selecting one or more bits in accordance with the number of bits; Based on the following expression (2)

Based on the following equation (3)

A second instruction mode parameter indicating one of the addition of bits using bit &lt; RTI ID = 0.0 &gt;

; remind

Quot; indicates the deselection of the bit,

For one or more bits selected according to

Terminating the selection of at least one bit according to the selection; remind

Quot; indicates the addition of the bit,

For a bit that is not selected according to &lt; RTI ID = 0.0 &

Selecting at least one bit according to the selected bit and adding it to the selected one or more bits; If the rate matching mode is a repeat mode,

And

Adding a selected bit based on the input bit stream; And When the rate matching mode is a puncturing mode,

And

And puncturing the selected bit in the input bit stream based on the input bit stream, Wherein the rate matching mode comprises:

Gt;

And if it is smaller, it is a repeat mode,

Gt;

If it is larger, it is a puncturing mode, remind

Is smaller than 0,

Indicates the deselection of the bit, remind

Is greater than 0,

Gt; &lt; / RTI &gt; characterized in that said step &Quot; (1) &quot;

=

, remind

The

Lt; / RTI &gt; &Quot; (2) &quot;

=

, remind

As the size of bits not selected by the primary indication parameter

Lt; / RTI &gt; &Quot; (3) &quot;

=

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