KR101517048B1 - Synchronizing pattern detection apparatus and method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync pattern detecting technique, and more particularly, to a sync pattern detector for detecting a sync pattern for synchronizing frames in a data stream and a method for detecting the same.
According to the present invention, there is an effect that a sync pattern can be detected quickly by a simple operation even when information on the position and length of the sync pattern is not given.

Description

TECHNICAL FIELD [0001] The present invention relates to a sync pattern detector and a method for detecting a sync pattern,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync pattern detecting technique, and more particularly, to a sync pattern detector for detecting a sync pattern for synchronizing frames in a data stream and a method for detecting the same.

A data stream converted into a bit stream and transmitted serially can be divided into frames, and a sync pattern for inter-frame synchronization is inserted in each frame. It is general that the sync pattern exists at the same position in each frame.

Detecting such a sync pattern quickly and accurately is an essential requirement for processing data or analyzing data. As a result, many methods have been introduced for detecting a sync pattern.

However, when the position of the sync pattern in the frame is not known as in the case of receiving data of the enemy group as a military purpose, if the sync pattern is detected through the correlation as described above, The number of calculations is increased because all the correlations are calculated while moving by one bit from the beginning to the end. In addition, when not only the position of the sync pattern but also the length of the sync pattern are unknown, the correlation is calculated while changing the unit according to the estimated length of the sync pattern.

Therefore, the detection method using such a correlation is time consuming and inefficient in terms of operation. This can be very lethal in areas where rapid data analysis and processing is required, such as defense and aviation. In addition, an error may occur in a bit in the process of transmitting data. The detection method using such a correlation is vulnerable to an error environment.

In particular, this problem becomes apparent when an error occurs in the sync pattern. That is, since the bits estimated as the length of the sync pattern are regarded as a single block, the correlation is calculated. Therefore, when an error occurs in the bit, a correlation value such as a block size value can not be derived. As a result, according to the detection method using such a correlation, if an error occurs even in one bit in a block, it affects the determination of the sync pattern.

1. U.S. Patent No. 5,148,453 2. Korea Patent No. 0253809

The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a sync pattern detector capable of quickly detecting a sync pattern even when information on a sync pattern is insufficient, The purpose is to provide.

The present invention provides a method of detecting a sync pattern that can detect a sync pattern quickly even when information on the sync pattern is insufficient, and also provides a method of detecting a sync pattern that is robust against an error environment.

The sync pattern detecting method comprising: a matrix generating step of generating a matrix by sequentially assigning a column index or a row index to a plurality of frames separated in parallel from a data stream; A mapping step of mapping the data values of the matrix and integers to generate mapping values; A summation value calculating step of summing up the mapping values corresponding to the same row index or column index to generate summation values; Comparing the absolute values of the sum values with a comparison value; A confirming step of confirming whether the same summation values as the comparison value are continuously present as a result of the comparison; A sync pattern length calculation step of calculating a sync pattern length by summing consecutive times of consecutive sum values; A determination step of determining whether the sync pattern length matches a predetermined set value; And a sync pattern detection step of detecting a sync pattern using a sync pattern position where the length of the sync pattern and the number of consecutive sum values appear as a result of the determination.

If the absolute values of the summation values are not equal to the comparison value or the summation values equal to the comparison value do not exist consecutively in the calculating of the sync pattern length, And changing the unit length of the plurality of frames if the frame size does not match the set value.

The method may further include extracting a data value corresponding to the sync pattern length and a sync pattern position, or extracting a continuous comparison value The number of frames and the data value before mapping are calculated based on the same summation values as in FIG.

(여기서, S : 합산값, N : 프레임의 갯수, n : 맵핑한 정수를 나타낸다) 에 의해 표현되는 것을 특징으로 할 수 있다.At this time, the relationship between the absolute value of the summation values and the comparison value is

(Where S is a summed value, N is the number of frames, and n is a mapped integer).

In order to minimize the influence of the bit error of the data, sum values corresponding to a predetermined reference value or more among the absolute values of the sum values are processed to have the same value as the product of the number of the frames and the absolute value of the integer The method comprising the steps of:

,

(여기서, β : 기준값, N : 프레임의 갯수, α : 문턱계수, n : 맵핑한 정수를 각각 나타낸다)에 의해 표현되는 것을 특징으로 할 수 있다.In addition,

,

(Where β is a reference value, N is the number of frames, α is a threshold coefficient, and n is a mapped integer).

According to another embodiment of the present invention, there is provided a method for generating a matrix by sequentially applying a column index or a row index to a plurality of frames separated in parallel from a data stream to generate a matrix; An integer mapping unit for mapping the data values of the matrix and integers to generate mapping values; An adder for summing up the mapping values corresponding to the same row index or column index to generate summed values; Comparing the absolute values of the sum values with a comparison value, calculating a sync pattern length by summing the consecutive times of the sum values when the same sum values as the comparison value are continuously present, A sync pattern determination unit determining whether the sync pattern is a sync pattern or not; And a sync pattern detector for detecting a sync pattern using a sync pattern position where the length of the sync pattern and the number of consecutive sum values are detected.

At this time, if the absolute values of the summation values are not equal to the comparison value, or the summation values equal to the comparison value do not exist continuously, or the sync pattern length does not match the predetermined set value, And the unit length of the plurality of frames is changed.

In order to minimize the influence of the bit error of the data, the sync pattern determination unit may multiply sum values corresponding to a predetermined reference value or more among the absolute values of the sum values by a product of the number of the plurality of frames and the absolute value of the integer To the same value.

According to the present invention, there is an effect that a sync pattern can be detected quickly by a simple operation even when information on the position and length of the sync pattern is not given.

According to another aspect of the present invention, a method of detecting a sync pattern by detecting a sync pattern by applying a threshold coefficient when a bit error occurs can provide a robust sync pattern detection method.

FIG. 1A is a block diagram of a communication system according to an embodiment of the present invention, and FIG. 1B is a block diagram of the sync pattern detector 100 shown in FIG. 1A.
FIG. 2A is a flowchart illustrating a general data synchronization process according to an embodiment of the present invention, and FIG. 2B is a flowchart illustrating a sync pattern detection step (S210) in detail during the data synchronization process shown in FIG. 2A.
FIGS. 3 to 6 are conceptual diagrams showing the concept of the sync pattern detection step S210 shown in FIG. 2A.

Although some embodiments of the present invention have been described, it will be apparent to those skilled in the art that modifications may be made without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims and their equivalents.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

1A is a block diagram of a communication system in accordance with an embodiment of the present invention. 1A, a communication system includes a data receiving unit 10, a sync pattern detector 100 for detecting a sync pattern from data received by the data receiving unit 10, and a sync pattern detector 100 for synchronizing data using the detected sync pattern A synchronization unit 20, and the like. Here, the sync pattern means a bit stream inserted at a predetermined position in each frame for inter-frame synchronization of the data stream.

FIG. 1B is a block diagram of the sync pattern detector 100 shown in FIG. 1A. 1, the sync pattern detector 100 includes a matrix unit 110, an integer mapping unit 120, an adder 130, a sync pattern determination unit 140, a sync pattern detection unit 150, and the like. .

The matrix forming unit 10 generates a plurality of frames by separating a data stream received through the data receiving unit 10 into predetermined predetermined unit lengths and arranges a plurality of frames to form a matrix. At this time, when information on the frame length of the data stream is known in advance, the length of the frame is separated by applying the unit length, and if the frame length is not known, the unit length is determined by predicting the frame length. In addition, the predicted frame length may be stored in advance and the frame length suited to the situation may be applied. A diagram showing such a matrix concept is shown in Fig. 3 will be described later.

The integer mapping unit 120 maps the integers having the same absolute value and different sign in one-to-one correspondence to the data values of the components constituting the matrix generated by the matrix construction unit 110. The integers having the same absolute value and different signs may be, for example, 1 and -1, but are not limited thereto. A diagram showing this mapping concept is shown in Fig. 4 will be described later.

The adder 130 sums the mapped values of components having the same row or column index among the components belonging to different frames of the matrix, respectively. At this time, since the components belonging to different frames are summed up, the index to be added to the row index or the column index is determined depending on the direction in which the frames are arranged when the matrix is generated. Figures 5 and 6 show a diagram showing such a summation concept. 5 and 6 will be described later.

The sync pattern determination unit 140 determines the number of frames N generated by the matrix unit 110 among the absolute values of the sum values S that are added through the adder 130 and the number of frames generated by the integer mapping unit 20, The position of the in-frame sync pattern and the length of the sync pattern are determined on the basis of the position and the continuous number of consecutive values corresponding to the product of the absolute value of the mapped integer (n) The relationship between the absolute value of the sum value S, the number of frames N, and the mapped integer n is expressed by the following equation.

[ Equation 1 ]

Here, S: sum value, N: number of frames, n: mapped integer.

Therefore, the position of the sync pattern can be determined in the frame based on the position where the summation value S according to Equation 1 continuously appears, and the length of the sync pattern can be found based on the number of consecutive times.

The sync pattern determination unit 140 determines whether or not the sync pattern is correctly determined based on whether or not the length of the determined sync pattern is included in the preset range of the sync pattern length value. For this purpose, the sync pattern determination unit 140 may store a sync pattern length value determined in consideration of various attributes of data such as a standard format, a type, and an application of the data.

In other words, if there is no value corresponding to the product of the number N of frames and the absolute value of the mapped integer n among the absolute values of the sum value S or if the length of the sync pattern determined according to the number of consecutive times is predicted It may happen that the length value of the known sync pattern does not match. For example, a signal having an IRIG telemetry standard generally has a sync pattern length of 16 bits or more, so that if the length of the determined sync pattern does not match, the frame length is mispredicted. Therefore, in this case, the sync pattern determining unit 140 changes the unit length by re-predicting the unit length, and the matrix forming unit 110 constructs the matrix by applying the changed unit length to the frame length, So that re-estimation of position and length can be made.

On the other hand, there is a possibility that a bit error occurs in the process of transmitting and receiving data. On the other hand, the sync pattern detection method based on the correlation has a disadvantage in that it is very vulnerable to detecting a sync pattern even if an error occurs in one bit in a block unit, because a sync pattern is detected in units of blocks grouped into several bits. However, according to the sync pattern detector according to the embodiment of the present invention, the bit error can be easily compensated using the threshold value.

In other words, since it is very unlikely that all the data words except the sync pattern in the frame have the same bit value, the sum S of the mapped values of the matrix is mostly mapped to the number of frames N Is less than the product of the integer (n).

Therefore, the sync pattern determining unit 140 determines and stores the reference value beta using the above facts, and stores the value corresponding to the reference value beta or more among the absolute values of the sum value S as the number of frames (N) and the integer (n) mapped. The equation is expressed as follows.

Here, S: sum value, β: reference value.

The threshold value? May be defined as a product of the number N of frames and a threshold coefficient? As shown in the following equation. Here, the threshold coefficient? It has a value between absolute values.

Here, β is a reference value, N is the number of frames, α is a threshold coefficient, and n is a mapped integer.

For example, when the mapped integer n is 1 and -1, the threshold coefficient a has a value between 0 and 1. At this time, the threshold coefficient? It can be experimentally determined by calculating the success rate.

The sync pattern detection unit 150 detects a sync pattern corresponding to the position of the sync pattern determined by the sync pattern determination unit 140 and the length of the sync pattern.

2A is a flowchart illustrating a process of synchronizing data using a sync pattern. Referring to FIG. 2A, in operation S200, data is input, a sync pattern is detected from inputted data S210, a frame synchronization is performed using the detected sync pattern S220, And outputting the performed data (S230).

Referring to FIG. 2B, a sync pattern detection step (S210) in the data synchronization process shown in FIG. 2A is illustrated in detail. Referring to FIG. 2B, a data stream composed of bit streams is divided into a predetermined unit length to generate a plurality of frames, and the generated frames are arranged to form a matrix (step S211).

When the matrix configuration is performed, mapping is performed one-to-one with the constants having the same absolute value and different signs corresponding to the data values of the components constituting the matrix (step S212).

When the process of mapping integers for each matrix component is completed, the mapped values of the components having the same row index or column index among the components belonging to different frames of the matrix are summed up (step S213). At this time, since the components belonging to different frames are summed up, the index to be summed depends on the direction in which the frames are arranged when the matrix is generated. Further, as shown in FIG. 5, the values mapped on the basis of the column index are added, or the values mapped on the basis of the row index are summed to obtain sum values S as shown in FIG. 5 and 6 will be described later.

, 여기서 N은 프레임의 갯수이고, n은 맵핑한 정수를 나타낸다)의 관계를 만족하는 합산값(S)들이 있는지를 확인한다.Thereafter, the absolute values of the sum values S are compared with a comparison value, and it is confirmed whether or not the sum values S equal to the comparison value exist (step S215). That is, as shown in Equation (1), the absolute value of the sum value S and the comparison value

, Where N is the number of frames and n is a mapped integer).

As a result of the check, if there are sum values S that satisfy Equation 1, it is confirmed whether these sum values S appear consecutively (Step S216). In other words, since the sync pattern is bit string, it appears continuously, so it is a process of confirming this.

If the sum values S continuously appear as a result of checking, the sync pattern length is calculated by summing the consecutive times of consecutive sum values (step S217).

It is determined whether the calculated sync pattern length matches a predetermined set value (step S218). In other words, if the set value is "9", the sync pattern length should be "9" to determine the position of the sync pattern.

As a result of the determination, if the sync pattern length matches the set value, both the position and the length information of the sync pattern in the frame are known, so that the sync pattern can be finally detected (step S219). That is, the sync pattern is for synchronizing frames, and the same pattern is inserted at the same position in each frame. Accordingly, the same integer value is mapped at the positions where the sync patterns are inserted in the respective frames, so that a multiple of the number of frames N is derived by adding all the mapped values . By applying such logic, it becomes possible to detect the positions and lengths of the sync patterns in the frame and the sync patterns corresponding thereto.

On the other hand, the detection of the sync pattern can be performed by extracting data values corresponding to the positions and lengths of the sync patterns determined in the frame. Alternatively, the sync pattern may be detected using the number of frames N and the data value before being mapped based on the sum value S corresponding to the position and the length of the sync pattern determined otherwise. For example, referring to 6 6 6 -6 6 -6 6 6 6 corresponding to the sync pattern among the sum values S shown in FIG. 5, the number of frames N is 6, It can be seen that the sync pattern is 1 1 -1 -1 -1 -1 1 1 based on mapping -1 to the value 0.

However, if there is no value corresponding to the product of the absolute value of the mapped integer n and the number N of frames in the absolute value of the sum value S in step S215, then in step S216, S are not consecutive, if the length of the sync pattern determined according to the number of consecutive times is predicted or does not match the length value of a known sync pattern, the unit length of the frame is changed to repeat steps S211 to S218 (S215-1).

In addition, this situation occurs when the unit length of the frame applied in step S211 does not match the actual frame length of the data stream. Therefore, at this time, the unit length is changed by re-predicting the unit length, and the above-described processes are repeated by re-applying the changed unit length to the frame length.

It goes without saying that the above-described steps may be appropriately added, changed or omitted depending on the situation. In other words, there is a possibility that a bit error occurs in the process of transmitting and receiving data. Therefore, in order to minimize the influence of the bit error, a value corresponding to a value equal to or greater than a preset reference value (beta) among the absolute values of the sum value S is divided into an absolute value n (Not shown) of processing the same value.

According to this, errors due to bit errors can be reduced through a simple approximation operation on the sum value (S). On the other hand, in the sync pattern detection method using the conventional correlation, when the threshold coefficient is applied, a value smaller than the block size is determined as a sync pattern, and the accuracy of the detection result is rapidly deteriorated. No threshold factor can be applied.

In this case, the reference value? Can be defined as the product of the number of frames N and the threshold coefficient? Having a value between 0 and the absolute value of the mapped integer n as described above.

 3 is a conceptual diagram of a matrix according to an embodiment of the present invention. Referring to FIG. 3, the matrix is formed by arranging a plurality of generated frames in parallel, and by giving the column index and the row index to cross each other. 3 (a), a row index 321 is sequentially assigned to a plurality of frames 1 to 6 having the same length as a unit length 310, and a row index 321 is sequentially assigned to each of the other frames 1 to 6 col < / RTI > index 320. < RTI ID = 0.0 > That is, frame 1 is arranged in one row index and frame 2 is arranged in two row index. Alternatively, a matrix may be generated such that a column index is sequentially assigned to a frame as shown in FIG. 3 (b) so that frame 1 is positioned at one column index and frame 2 is positioned at a two-column index.

Therefore, as shown in FIG. 3A, components having the same row index 320 belong to the same frame, so that the sum of the mapped values of the components having the same column index 321 is derived. On the other hand, in the case of FIG. 3 (b), the components having the same column index 320 belong to the same frame, so that the mapping values of the components having the same row index 321 are added. This matrix serves as a basis for determining the positions of the sync patterns and the length of the sync patterns.

FIG. 4 is a schematic diagram for explaining a process of mapping integers one by one to the components of the formed matrix. FIG. Hereinafter, for convenience of explanation, a case where 1 and -1 are mapped will be described as an example. Fig. 4A is an example of a matrix formed by arranging a plurality of frames before mapping. Fig. For reference, each frame is arranged to have a sequential row index as shown in FIG. 3 (a). 4 (b) is obtained by mapping the integers having the same absolute value and different signs according to the bit values of the matrix component formed as shown in FIG. 4 (a) one to one. More specifically, in FIG. 4A, the data bit value "1" is mapped to an integer "1", and "0" to an integer "-1".

4 (b) shows an example after mapping. On the other hand, if the bit value is 1, it can be mapped to -1, and when the bit value is 0, it can be mapped to 1.

5 is a conceptual diagram for summing mapped values using the same column index according to an embodiment of the present invention and determining the position and length of a sync pattern. Referring to FIG. 5, FIG. 5 assumes that a matrix is generated by sequentially assigning a row index to a frame. As described above, since the same row index is a component belonging to the same frame, the mapping values of the components belonging to the same column index are added up. According to FIG. 5, [2 2 2 0 2 0 -2 6 6 6 -6 6 -6 6 6 2 2 2] is obtained as the sum values S of the sum of the mapping values of the components belonging to the same column index .

At this time, since the frame number N is 6 and the absolute value of the mapped integer n is 1, a sync pattern can be detected on the basis that the values corresponding to 6 or -6 of the sum values above are consecutively displayed . That is, in FIG. 5, since 6 or -6 are represented in 8 rows to 16 columns, positions corresponding to columns 8 to 16 in the frame are positions of the sync patterns, and the positions of the sync patterns are 9 consecutive times. . In this way, if the mapped integer is 2 and -2, the sync pattern can be detected based on the value corresponding to the sum value of 12 or -12.

6 is a conceptual diagram for summing mapped values using the same row index according to another embodiment of the present invention and determining the position and length of a sync pattern. Referring to FIG. 6, it is assumed that a matrix is generated by sequentially assigning a column index to a frame in FIG. As described above, since the same column index belongs to the same frame, the mapping values of the components belonging to the same row index are added. 6, the sum values S of the sum of the mapping values of the components belonging to the same row index are [2 2 2 0 2 0 -2 6 6 6 -6 6 -6 6 6 2 2 2] can be obtained. However, in the case of FIG. 6, since the sum values S are 6 to 6 or 6 to 8 rows to 16 rows, positions corresponding to lines 8 to 16 in the frame are the positions of the sync patterns.

Claims (14)

A matrix generation step of generating a matrix by sequentially assigning a column index or a row index to a plurality of frames separated in parallel from a data stream;
A mapping step of mapping the data values of the matrix and integers to generate mapping values;
A summation value calculating step of summing up the mapping values corresponding to the same row index or column index to generate summation values;
Comparing the absolute values of the sum values with a comparison value;
A confirming step of confirming whether the same summation values as the comparison value are continuously present as a result of the comparison;
A sync pattern length calculation step of calculating a sync pattern length by summing consecutive times of consecutive sum values;
A determination step of determining whether the sync pattern length matches a predetermined set value; And
A sync pattern detecting step of detecting a sync pattern using a sync pattern position where the length of the sync pattern and the number of consecutive sum values appear as a result of the determination;
And detecting the sync pattern. The method according to claim 1,
If the absolute values of the sum values are not equal to the comparison value in the comparison step, or the sum values equal to the comparison value do not exist continuously in the sync pattern length calculation step, or if the sync pattern length is less than a predetermined set value And changing the unit length of the plurality of frames if the frame length does not match the unit length of the plurality of frames. The method according to claim 1,
Wherein said integers have the same absolute value and different signs. The method according to claim 1,
The detection of the sync pattern may be performed by extracting a data value corresponding to the sync pattern length and the sync pattern position or by using the number of frames and the data value before mapping on the basis of the same summation values as the continuously- Wherein the sync pattern detection method comprises the steps of: The method according to claim 1,
The relationship between the absolute value of the summation values and the comparison value is as follows:

(Where S is a summed value, N is the number of frames, and n is a mapped integer). The method according to claim 1,
Processing sum values corresponding to a predetermined reference value or more among absolute values of the sum values to a value equal to a product of the number of the plurality of frames and an absolute value of the integer to minimize the influence of bit errors of data, And detecting the sync pattern. The method according to claim 6,
The reference value is expressed by the following equation

,

(Where,?: Reference value, N: number of frames,?: Threshold coefficient, and n: mapped integer respectively). A matrix generating unit for sequentially generating a matrix by applying a column index or a row index sequentially to a plurality of frames separated in parallel from a data stream;
An integer mapping unit for mapping the data values of the matrix and integers to generate mapping values;
An adder for summing up the mapping values corresponding to the same row index or column index to generate summed values;
Comparing the absolute values of the sum values with a comparison value, calculating a sync pattern length by summing the consecutive times of the sum values when the same summation values as the comparison value are continuously present, determining whether the sync pattern length matches the preset set value A sync pattern determination unit determining whether the sync pattern is a sync pattern or not; And
A sync pattern detector for detecting a sync pattern using a sync pattern position where the length of the sync pattern and the number of consecutive sum values appear;
And a sync pattern detector. 9. The method of claim 8,
The sync pattern determination unit may determine that the absolute values of the sum values are not equal to the comparison value or if the same sum value as the comparison value does not exist continuously or if the sync pattern length does not match a predetermined set value, And the unit length of the frame is changed. 9. The method of claim 8,
Wherein said integers have the same absolute value and different signs. 9. The method of claim 8,
The detection of the sync pattern may be performed by extracting a data value corresponding to the sync pattern length and the sync pattern position or by using the number of frames and the data value before mapping on the basis of the same summation values as the continuously- A sync pattern detector characterized by. 9. The method of claim 8,
The relationship between the absolute value of the summation values and the comparison value is as follows:

(Where S is a summed value, N is the number of frames, and n is a mapped integer). 9. The method of claim 8,
Wherein the sync pattern determination unit determines summation values that are equal to or greater than a preset reference value among absolute values of the summation values to be equal to a product of the number of the plurality of frames and the absolute value of the integer, Value of the sync pattern. 14. The method of claim 13,
The reference value is expressed by the following equation

,

(Where,?: Reference value, N: number of frames,?: Threshold coefficient, and n: mapped integer respectively).

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