KR101512601B1 - Multi-layered ceramic capacitor and mounting circuit having thereon multi-layered ceramic capacitor - Google Patents

Abstract

The present invention relates to a ceramic body comprising a ceramic body in which a plurality of dielectric layers are laminated; An active layer including a plurality of internal electrodes alternately exposed through both end faces of the ceramic body with the dielectric layer interposed therebetween; An upper cover layer formed on the active layer; A lower cover layer formed under the active layer and having a thickness greater than that of the upper cover layer; And external electrodes formed to cover both ends and upper and lower surfaces of the ceramic body. Wherein a distance from an end of the lowermost internal electrode of the active layer to an end of the external electrode covering a part of the lower surface of the ceramic body is E, and a distance from the end of the external electrode to the lowermost internal electrode Of the entire thickness of the ceramic body is T, and a margin in the longitudinal direction of the ceramic body is defined as F, 1.2? E / T and satisfying the range of 30 占 퐉? F, Is A, the thickness of the lower cover layer is B, the half of the total thickness of the active layer is C, and the thickness of the upper cover layer is D, the center portion of the active layer is the ceramic (B + C) / A satisfies the following range: 1.063? (B + C) /A? 1.745.

Description

TECHNICAL FIELD [0001] The present invention relates to a multilayer ceramic capacitor and a multilayer ceramic capacitor, and more particularly to a multilayer ceramic capacitor and a multilayer ceramic capacitor,

The present invention relates to a multilayer ceramic capacitor and a mounting substrate of a multilayer ceramic capacitor.

Multilayer ceramic capacitors, which are one of the multilayer chip electronic components, are widely used as display devices such as a liquid crystal display (LCD) and a plasma display panel (PDP), computers, personal digital assistants (PDAs) And a chip type capacitor which is mounted on a printed circuit board of various electronic products such as a mobile phone and plays a role of charging or discharging electricity.

Such a multi-layered ceramic capacitor (MLCC) can be used as a component of various electronic devices because of its small size, high capacity, and ease of mounting.

The multilayer ceramic capacitor may have a structure in which a plurality of dielectric layers and internal electrodes of different polarities are alternately stacked between the dielectric layers.

Since the dielectric layer has piezoelectricity and electrostrictive properties, when a direct current or an alternating voltage is applied to the multilayer ceramic capacitor, piezoelectric phenomenon occurs between the internal electrodes and vibration may occur.

Such vibration is transmitted to the printed circuit board on which the multilayer ceramic capacitor is mounted through the external electrode of the multilayer ceramic capacitor so that the entire printed circuit board becomes an acoustic reflection surface, and a noise is generated as noise.

The vibration sound may correspond to an audible frequency in the range of 20 to 20000 Hz which gives an uncomfortable feeling to a person. The vibration sound that is uncomfortable to a person is called an acoustic noise, and research for reducing such acoustic noise is required It is true.

In addition, since the multilayer ceramic capacitor is formed by printing an internal electrode having a thickness smaller than the area of the sheet on the ceramic sheet and then laminating it, a step between the margin and the dielectric layer on which the internal electrode is formed is inevitably generated. Can be deepened at the portion where the internal electrode of the semiconductor device is formed.

When the step is generated, delamination or cracking may occur in which a part of the dielectric layers are peeled off from each other when thermal shock is applied or when stress due to bending of the printed circuit board is applied after mounting.

Therefore, moisture or other foreign matter penetrates into the exposed surface of the internal electrode through the delamination or crack, which may cause deterioration of insulation resistance of the multilayer ceramic capacitor and lower reliability. This problem can be further exacerbated particularly in a super-high-capacity product having a large number of sheets.

Japanese Patent Application Laid-Open No. 6-215978

In the related art, it is possible to reduce the noise generated by the vibration due to the piezoelectric phenomenon, to compensate the step between the margin portion and the dielectric layer on which the internal electrode is formed, and to prevent mechanical shock such as thermal shock or stress due to bending in the printed circuit board after mounting There has been a demand for a new method for a multilayer ceramic capacitor capable of suppressing the occurrence of delaminations and cracks due to the above-mentioned problems.

According to an aspect of the present invention, there is provided a ceramic body comprising: a ceramic body in which a plurality of dielectric layers are stacked; An active layer including a plurality of internal electrodes alternately exposed through both end faces of the ceramic body with the dielectric layer interposed therebetween; An upper cover layer formed on the active layer; A lower cover layer formed under the active layer and having a thickness greater than that of the upper cover layer; And external electrodes formed to cover both ends and upper and lower surfaces of the ceramic body. Wherein a distance from an end of the lowermost internal electrode of the active layer to an end of the external electrode covering a part of the lower surface of the ceramic body is E, and a distance from the end of the external electrode to the lowermost internal electrode Of the total thickness of the ceramic body satisfies a range of 1.2? E / T and 30 占 퐉? F when the shortest distance to the ceramic body is defined as T and the longitudinal margin of the ceramic body is defined as F, Is A, the thickness of the lower cover layer is B, the half of the total thickness of the active layer is C, and the thickness of the upper cover layer is D, the center portion of the active layer is the ceramic (B + C) / A satisfies the following range: 1.063? (B + C) /A? 1.745.

In an embodiment of the present invention, the ratio D / B between the thickness D of the upper cover layer and the thickness B of the lower cover layer may satisfy a range of 0.021 D / B? 0.422.

In one embodiment of the present invention, the ratio B / A of the thickness (B) of the lower cover layer to 1/2 (A) of the total thickness of the ceramic body satisfies the range of 0.329 B / A .

In one embodiment of the present invention, the ratio C / B of 1/2 (C) of the total thickness of the active layer to the thickness (B) of the lower cover layer satisfies the range of 0.146? C / B? .

In an embodiment of the present invention, the inflection points formed on both end faces of the ceramic body may be different from the thickness of the ceramic body due to the difference between the deformation ratio generated at the central portion of the active layer and the deformation ratio generated at the lower cover layer, And may be formed below the central portion.

In an embodiment of the present invention, the first and second internal electrodes may be formed such that a portion exposed through a cross section of the ceramic body tapers inward.

In an embodiment of the present invention, the first and second internal electrodes may be formed such that corner portions of the other surface that are not exposed to the outside of the ceramic body are tapered inward.

Another aspect of the present invention is a printed circuit board comprising: a printed circuit board having a pair of electrode pads on an upper portion thereof; And a multilayer ceramic capacitor mounted on the printed circuit board; Wherein the multilayer ceramic capacitor comprises: a ceramic body in which a plurality of dielectric layers are stacked; An active layer including a plurality of internal electrodes alternately exposed through both end faces of the ceramic body with the dielectric layer interposed therebetween; An upper cover layer formed on the active layer; A lower cover layer formed under the active layer and having a thickness greater than that of the upper cover layer; First and second external electrodes formed to cover both end faces of the ceramic body and connected to the pair of electrode pads by soldering; Wherein a distance from an end of the lowermost internal electrode of the active layer to an end of the external electrode covering a part of the lower surface of the ceramic body is E, and a distance from the end of the external electrode to the lowermost internal electrode Of the total thickness of the ceramic body satisfies a range of 1.2? E / T and 30 占 퐉? F when the shortest distance to the ceramic body is defined as T and the longitudinal margin of the ceramic body is defined as F, Is A, the thickness of the lower cover layer is B, the half of the total thickness of the active layer is C, and the thickness of the upper cover layer is D, the center portion of the active layer is the ceramic (B + C) / A satisfies the following range: 1.063? (B + C) /A? 1.745.

In an embodiment of the present invention, the inflection point formed on both end faces of the ceramic body is less than or equal to the height of the soldering due to the difference between the deformation rate generated at the central portion of the active layer and the deformation rate generated at the lower cover layer, .

According to an embodiment of the present invention, vibration generated in a multilayer ceramic capacitor is reduced to reduce acoustic noise generated in a printed circuit board, while compensating for a step difference in a ceramic body, thereby preventing thermal shock or warping on a printed circuit board after mounting It is possible to prevent degradation of insulation resistance of the multilayer ceramic capacitor and to improve reliability by preventing penetration of moisture or other foreign matter into the exposed surface of the internal electrode by suppressing delamination or cracking caused by mechanical impact such as stress caused by the stress It is effective.

1 is a perspective view schematically showing a part of a multilayer ceramic capacitor according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 taken along the longitudinal direction. Fig.
FIG. 3 is a cross-sectional view schematically showing the multilayer ceramic capacitor of FIG. 1 cut in the longitudinal direction to explain the dimensional relationship of components included in the multilayer ceramic capacitor.
4 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 1 is mounted on a printed circuit board.
FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor and the printed circuit board of FIG. 4 cut in the longitudinal direction.
6 is a cross-sectional view schematically illustrating a state in which a multilayer ceramic capacitor is deformed by applying a voltage in a state where the multilayer ceramic capacitor of FIG. 5 is mounted on a printed circuit board.
Figs. 7 to 13 are cross-sectional views showing various modifications of internal electrodes applied to a multilayer ceramic capacitor according to an embodiment of the present invention. Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

In the drawings, like reference numerals are used to designate like elements that are functionally equivalent to the same reference numerals in the drawings.

In order to clearly illustrate the embodiments of the present invention, when the directions of the hexahedron are defined, L, W, and T shown in the drawings indicate the longitudinal direction, the width direction, and the thickness direction, respectively. Here, the thickness direction can be used in the same concept as the lamination direction in which the dielectric layers are laminated.

In the present embodiment, for convenience of explanation, the surfaces on which the first and second external electrodes are formed in the longitudinal direction of the ceramic body are set to both the right and left end faces, and the faces intersecting perpendicularly are set as the left and right sides, .

Multilayer Ceramic Capacitors

1 and 2, a multilayer ceramic capacitor 100 according to an embodiment of the present invention includes a ceramic body 110, an active layer 115 having first and second internal electrodes 121 and 122, First and second outer electrodes 131 and 132 formed to cover the upper and lower cover layers 112 and 113 and both end faces of the ceramic body 110. [

The ceramic body 110 is formed by laminating a plurality of dielectric layers 111 and then firing the ceramic body 110. The shape and dimensions of the ceramic body 110 and the number of stacked layers of the dielectric layers 111 are not limited to those shown in this embodiment .

The plurality of dielectric layers 111 forming the ceramic body 110 are in a sintered state and the boundaries between the adjacent dielectric layers 111 are such that it is difficult to confirm without using a scanning electron microscope (SEM) Can be integrated.

The ceramic body 110 includes an active layer 115 serving as a portion contributing to capacitance formation of a capacitor and upper and lower cover layers 112 and 113 formed respectively on upper and lower portions of the active layer 115 as upper and lower margin portions .

The active layer 115 may be formed by repeatedly laminating a plurality of first and second internal electrodes 131 and 132 with a dielectric layer 111 interposed therebetween.

At this time, the thickness of the dielectric layer 111 can be arbitrarily changed according to the capacity design of the multilayer ceramic capacitor 100. The thickness of one layer may be 0.01 to 1.00 m after firing. However, It is not.

The dielectric layer 111 may include a ceramic powder having a high dielectric constant, for example, a barium titanate (BaTiO ₃ ) -based or a strontium titanate (SrTiO ₃ ) -based powder, but the present invention is not limited thereto.

The upper and lower cover layers 112 and 113 may have the same material and configuration as the dielectric layer 111 except that they do not include internal electrodes.

The upper and lower cover layers 112 and 113 may be formed by laminating a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the active layer 115 in the vertical direction, respectively. Basically, Thereby preventing damage to the second internal electrodes 121 and 122.

Further, the lower cover layer 113 may have a thicker thickness than the upper cover layer by further increasing the number of laminated layers of the dielectric layer than the upper cover layer 112.

The first and second internal electrodes 121 and 122 are a pair of electrodes having polarities different from each other and are formed by printing a conductive paste containing a conductive metal to a predetermined thickness on the dielectric layer 111, And may be electrically insulated from each other by the dielectric layer 111 disposed in the middle.

That is, the first and second internal electrodes 121 and 122 may be electrically connected to the first and second external electrodes 131 and 132, respectively, through the portions alternately exposed through both end faces of the ceramic body 110 .

Therefore, when a voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the first and second internal electrodes 121 and 122 opposing each other. At this time, the electrostatic charge of the multilayer ceramic capacitor 100 The capacitance is proportional to the area of the overlapping region of the first and second internal electrodes 121 and 122. [

The thickness of the first and second internal electrodes 121 and 122 may be determined depending on the application, and may be determined to fall within a range of 0.2 to 1.0 占 퐉 in consideration of the size of the ceramic body 110, But is not limited thereto.

The conductive metal included in the conductive paste forming the first and second internal electrodes 121 and 122 may be nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof. But is not limited thereto.

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The first and second external electrodes 131 and 132 may be formed to cover both ends and upper and lower surfaces of the ceramic body 110 by a conductive paste containing a conductive metal, ), Copper (Cu), palladium (Pd), gold (Au), or an alloy thereof, but the present invention is not limited thereto.

The first and second outer electrodes 131 and 132 are formed on the printed circuit board by adjusting distances between the first and second inner electrodes 121 and 122, It is necessary to reduce the occurrence and increase the reliability.

2, the distance from the end of the lowermost second internal electrode 122 of the active layer 115 to the end of the first external electrode 131 covering a part of the lower surface of the ceramic body 110 is denoted by E, The shortest distance from the end of the first external electrode 131 to the second internal electrode 122 at the lowermost end of the active layer 115 is T, The longitudinal margin to the end is defined as F.

At this time, the range in which the occurrence of delamination and cracking can be reduced to increase the reliability can be 1.2? E / T.

If 1.2 > E / T, the portion where the mechanical impact such as stress due to the bending of the printed circuit board concentrates is set to be coincident with or close to that of the stepped portion of the ceramic body 110, have.

Further, the margin F in the longitudinal direction of the ceramic body 110 may be set to 30 mu m or more to prevent the occurrence of delamination.

If the margin F in the longitudinal direction of the ceramic body 100 is less than 30 占 퐉, the occurrence of delamination may be increased due to insufficient margins.

Hereinafter, the relationship between the dimensions of the components included in the multilayer ceramic capacitor according to the present embodiment and the acoustic noise will be described.

The thickness of the lower cover layer 113 is set to B, the half of the total thickness of the active layer 115 is set to C, And the thickness of the cover layer 112 is defined as D.

Here, the total thickness of the ceramic body 110 means the distance from the upper surface S _{T to} the lower surface S _B of the ceramic body 110, and the total thickness of the active layer 115 corresponds to the distance Means the distance from the top surface of the first internal electrode 121 formed on the top to the bottom surface of the second internal electrode 122 formed on the lowermost portion of the active layer 115.

The thickness B of the lower cover layer 113 is a distance from the lower surface of the second internal electrode 122 formed at the lowermost portion in the thickness direction of the active layer 115 to the lower surface S _B of the ceramic body 110 And the thickness D of the upper cover layer 112 is from the upper surface of the first internal electrode 121 formed on the uppermost portion in the thickness direction of the active layer 115 to the upper surface S _T of the ceramic body 110 .

When a voltage having a different polarity is applied to the first and second external electrodes 131 and 132 formed at both ends of the multilayer ceramic capacitor 100, an inverse piezoelectric effect of the dielectric layer 111 causes the ceramic body The first and second external electrodes 131 and 132 are expanded and contracted in the thickness direction of the ceramic body 110 due to the Poisson effect, Contraction and expansion.

Here, the central portion of the active layer 115 is the portion that is most expanded and contracted at both end portions in the longitudinal direction of the first and second external electrodes 131 and 132, and becomes a factor that causes acoustic noise.

That is, in this embodiment, in order to reduce the acoustic noise, due to the difference between the strain rate generated at the center portion (CL _A ) of the active layer (115) and the strain rate generated at the lower cover layer (113) A point of inflection (PI) formed on both end faces of the ceramic body 110 may be formed at a center portion CL _C of the thickness of the ceramic body 110 or less.

At this time, in order to further reduce the acoustic noise, the ratio of the center portion CL _A of the active layer 115 to the center portion CL _C of the ceramic body 110, (B + C) / A is 1.063? C) /A ≤ 1.745.

The ratio D / B between the thickness D of the upper cover layer 112 and the thickness B of the lower cover layer 113 can satisfy the range of 0.021? D / B? 0.422.

The ratio B / A of the thickness B of the lower cover layer 113 to 1/2 of the total thickness of the ceramic body 110 can satisfy the range of 0.329 B / A? 1.522 .

The ratio C / B of 1/2 (C) of the total thickness of the active layer 115 to the thickness B of the lower cover layer 113 can satisfy the range of 0.146? C / B? 2.458 .

Experimental Example

The multilayer ceramic capacitor according to the embodiment and the comparative example of the present invention was produced as follows.

A slurry containing a powder such as barium titanate (BaTiO ₃ ) is coated on a carrier film and dried to prepare a plurality of ceramic green sheets having a thickness of 1.8 탆.

Next, a conductive paste for a nickel internal electrode is coated on the ceramic green sheet using a screen to form an internal electrode.

The ceramic green sheets without the internal electrodes were stacked in the lower part of the ceramic green sheet having the internal electrodes formed thereon in a thickness of about 370 layers. This laminate was subjected to isostatic pressing under a pressure of 1000 kgf / cm ² at 85 ° C.

The pressed ceramic laminate was cut into individual chips, and the cut chips were maintained at 230 DEG C for 60 hours in an atmospheric environment to carry out the binder removal.

Thereafter, the internal electrodes were fired at 1200 DEG C in a reducing atmosphere under an oxygen partial pressure of 10 ^-11 to 10 ^-10 atm lower than the Ni / NiO equilibrium oxygen partial pressure so that the internal electrodes were not oxidized. The chip size of the post-firing multilayer chip capacitor was about 1.64 mm x 0.88 mm (L x W, 1608 size) in length x width (L x W). Here, the manufacturing tolerance was set within a range of ± 0.1 mm in length × width (L × W), and if it was satisfied, acoustic noise measurement was performed by experiment.

Next, a multilayer ceramic capacitor was manufactured through an external electrode, a plating process, and the like.

Sample A
(탆) B
(탆) C
(탆) D
(탆) (B + C) / A B / A D / B C / B AN
(dB) Volume
Implementation rate One* 405.5 40.2 365.4 39.9 1,000 0.099 0.993 9.090 29.5 OK 2* 436.0 70.4 365.9 69.7 1.001 0.161 0.990 5.197 25.7 OK 3 * 455.5 90.8 364.3 91.5 0.999 0.199 1.008 4.012 23.1 OK 4* 508.1 24.9 361.1 269.1 0.760 0.049 10.807 14.502 31.2 OK 5 * 456.6 25.2 360.1 167.8 0.844 0.055 6.659 14.290 32.5 OK 6 * 527.3 30.2 191.0 642.4 0.419 0.057 21.272 6.325 30.3 OK 7 * 414.5 30.9 188.8 420.4 0.530 0.075 13.605 6.110 30.5 OK 8* 516.2 39.4 360.7 271.5 0.775 0.076 6.891 9.155 28.2 OK 9 * 446.0 39.8 365.5 121.2 0.909 0.089 3.045 9.183 29.1 OK 10 * 469.1 40.6 364.2 169.1 0.863 0.087 4.165 8.970 27.9 OK 11 * 416.2 40.7 360.7 70.3 0.964 0.098 1.727 8.862 28.4 OK 12 * 428.3 40.8 360.0 95.7 0.936 0.095 2.346 8.824 28.9 OK 13 * 495.9 40.9 364.9 221.0 0.818 0.082 5.403 8.922 28.1 OK 14 * 435.9 25.0 421.3 4.2 1.024 0.057 0.168 16.852 31.6 OK 15 * 420.7 70.4 365.9 39.1 1.037 0.167 0.555 5.197 25.7 OK 16 431.7 94.8 364.3 40.0 1.063 0.220 0.422 3.843 19.9 OK 17 443.0 103.8 389.1 4.0 1.113 0.234 0.039 3.749 19.3 OK 18 443.7 119.8 363.2 41.1 1.089 0.270 0.343 3.032 18.7 OK 19 447.1 147.3 362.1 22.7 1.139 0.329 0.154 2.458 17.9 OK 20 452.8 164.7 360.2 20.4 1.159 0.364 0.124 2.187 17.3 OK 21 448.7 170.3 361.0 5.1 1.184 0.380 0.030 2.120 17.2 OK 22 470.7 170.4 365.4 40.2 1.138 0.362 0.236 2.144 17.4 OK 23 491.9 220.3 360.8 41.8 1.181 0.448 0.190 1.638 16.9 OK 24 500.6 270.2 360.5 9.9 1.260 0.540 0.037 1.334 16.8 OK 25 516.9 270.4 361.8 39.7 1.223 0.523 0.147 1.338 16.7 OK 26 502.1 364.9 312.3 14.7 1.349 0.727 0.040 0.856 16.6 OK 27 407.5 421.8 189.1 14.9 1.499 1.035 0.035 0.448 16.6 OK 28 445.8 493.3 179.3 39.7 1.509 1.107 0.080 0.363 16.5 OK 29 483.7 632.0 160.1 15.2 1.638 1.307 0.024 0.253 16.4 OK 30 520.0 643.4 190.7 15.2 1.604 1.237 0.024 0.296 16.4 OK 31 486.4 685.3 121.1 45.3 1.658 1.409 0.066 0.177 16.4 OK 32 507.2 742.7 120.8 30.1 1.702 1.464 0.041 0.163 16.4 OK 33 515.2 773.9 118.2 20.1 1.732 1.502 0.026 0.153 16.4 OK 34 524.5 798.2 116.9 16.9 1.745 1.522 0.021 0.146 16.3 OK 35 * 533.4 832.4 109.8 14.8 1.766 1.561 0.018 0.132 16.3 NG 36 * 533.3 841.1 105.3 14.9 1.775 1.577 0.018 0.125 16.3 NG 37 * 534.1 849.7 101.2 16.1 1.780 1.591 0.019 0.119 16.3 NG

* Is a comparative example, AN: acoustic noise,

The data shown in Table 1 are obtained by cutting the cross section of the multilayer ceramic capacitor 100 in the longitudinal direction L and the thickness direction T at the central portion of the width direction W of the ceramic body 110 by a scanning electron microscope (SEM, Scanning Electron Microscope).

As described above, A, B, C, and D represent the total thickness of the ceramic body 110 as A, the thickness of the lower cover layer 113 as B, the total thickness of the active layer 115 The thickness of the upper cover layer 112 is defined as D,

In order to measure acoustic noise, one sample (multilayer chip capacitor) per acoustic noise measurement board was divided into upper and lower parts and mounted on a printed circuit board, and the board was attached to a measuring jig.

DC voltage and voltage fluctuations were applied to both terminals of the sample mounted on the measurement jig using a DC power supply and a function generator. Acoustic noise was measured through a microphone installed just above the printed circuit board.

In Table 1, Samples 1 to 3 are comparative examples in which the thickness (B) of the lower cover layer 113 and the thickness (D) of the upper cover layer 112 have a substantially similar cover symmetry structure, Is a comparative example in which the thickness D of the upper cover layer 112 is thicker than the thickness B of the lower cover layer.

Samples 14 to 15 and 35 to 37 are comparative examples in which the thickness B of the lower cover layer 113 is thicker than the thickness D of the upper cover layer 112, Fig.

Here, when the value of (B + C) / A is substantially equal to 1, it means that the central portion of the active layer 115 does not deviate greatly from the central portion of the ceramic body 110. The (B + C) / A value of the samples 1 to 3 having a cover symmetric structure substantially similar to the thickness (B) of the lower cover layer 113 and the thickness (D)

(B + C) / A value is greater than 1, it means that the central portion of the active layer 115 deviates upward from the central portion of the ceramic body 110. When the value of (B + C) / A is less than 1 It may mean that the central portion of the active layer 115 deviates downward from the center of the ceramic body 110.

Referring to Table 1, the ratio of the central portion of the active layer 115 to the central portion of the ceramic body 110, (B + C) / A satisfies the range of 1.063? (B + C) /A? It can be confirmed that the acoustic noise in Samples 16 to 34, which is the embodiment, is remarkably reduced to less than 20 dB.

Samples 1 to 15, in which the center portion of the active layer 115 deviates from the central portion of the ceramic body 110 and (B + C) / A is less than 1.063, The center portion of the active layer 115 has a structure deviating downward from the center portion of the ceramic body 110. [

Samples 1 to 15 in which (B + C) / A is less than 1.063 have an acoustic noise of 25 to 32.5 dB, which is less effective for reducing acoustic noise than the embodiment according to the present invention.

In the case of samples 35 to 37 in which the central portion of the active layer 115 deviates from the central portion of the ceramic body 110 and (B + C) / A exceeds 1.745, the capacitance to the target capacitance is low, Respectively.

In Table 1, the capacity implementation rate (i.e., the ratio of the capacitance to the target capacity) is indicated as "NG ", which means that the capacitance value with respect to the target capacity is less than 80% when the target capacity value is 100%.

Embodiments in which the ratio (D / B) of the thickness D of the upper cover layer 112 to the thickness B of the lower cover layer 113 satisfy a range of 0.021? D / B? 0.422, Is significantly reduced.

On the other hand, comparative examples in which the ratio (D / B) of the thickness D of the upper cover layer 112 to the thickness B of the lower cover layer 113 exceed 0.422 show no effect of reducing the acoustic noise have.

When the ratio D / B of the thickness D of the upper cover layer 112 to the thickness B of the lower cover layer 113 is less than 0.021, The thickness (B) of the cover layer 113 is excessively large, cracks or delaminations may occur, and capacitance may be low due to the low capacitance to the target capacity.

The ratio B / A of the thickness B of the lower cover layer 113 to the thickness A of the ceramic body 110 and the thickness B of the lower cover layer 113 Samples 19 to 34, which are the examples satisfying the ranges of 0.329? B / A? 1.522 and 0.146? C / B? 2.458, respectively, the ratio (C / B) of the thickness It can be seen that it is shrinking further.

On the other hand, when the ratio B / A of the thickness B of the lower cover layer 113 to the thickness A of the ceramic body 110 exceeds 1.522 or the thickness B of the lower cover layer 113 In the case of Samples 35 to 37 in which the ratio (C / B) of the thickness (C) of the active layer 115 to the active layer 115 is less than 0.146, there is a problem that the capacitance is low relative to the target capacitance,

Table 2 shows the distance E from the end of the lowermost internal electrode of the active layer 115 to the end of the external electrode covering a part of the lower surface of the ceramic body 110 and the distance E from the end of the external electrode to the active layer 115. [ Of the multilayer ceramic capacitor 100 according to the ratio of the shortest distance T to the lowermost internal electrode of the ceramic body 110 and the margin F of the ceramic body 110 in the longitudinal direction. The following numerical values of the flexural cracks and delamination are shown for each sample to indicate the number of defects in the sample.

No. T F E E / T Flexural crack Delamination One* 220 10 364.01 1.655 0 11 2* 220 20 356.09 1.619 0 4 3 220 30 348.28 1.583 0 0 4 220 40 340.59 1.548 0 0 5 220 50 333.02 1.514 0 0 6 220 75 314.68 1.430 0 0 7 220 100 297.32 1.351 0 0 8 220 125 281.11 1.278 0 0 9 220 150 266.27 1.210 0 0 10 * 220 175 253.03 1.150 One 0 11 * 220 200 241.66 1.098 3 0 12 * 220 225 232.43 1.057 5 0 13 * 220 250 225.61 1.026 10 0 14 * 160 10 331.21 2.070 0 13 15 * 160 20 322.49 2.016 0 3 16 160 30 313.85 1.962 0 0 17 160 40 305.29 1.908 0 0 18 160 50 296.82 1.855 0 0 19 160 75 276.09 1.726 0 0 20 160 100 256.12 1.601 0 0 21 160 125 237.12 1.482 0 0 22 160 150 219.32 1.371 0 0 23 160 175 203.04 1.269 0 0 24 * 160 200 188.68 1.179 2 0 25 * 160 225 176.71 1.104 5 0 26 * 170 250 177.20 1.042 7 0

* Is a comparative example, and the unit of T, E and F is 탆

Referring to Table 2, the distance E from the end of the lowermost internal electrode of the active layer 115 to the end of the external electrode covering a part of the lower surface of the ceramic body 110, In the case of Samples 10 to 13 and Samples 24 to 26 as comparative examples in which E / T is less than 1.2, the ratio of the shortest distance (T) to the lowermost internal electrode of the printed circuit board 115 It can be seen that a bending crack occurs due to coincidence or proximity with a portion where a step is generated in the inside of the ceramic body 110.

Also, in the samples 1 and 2 and the samples 14 and 15 as the comparative example in which the E / T ratio was 1.2 or more and the margin F in the longitudinal direction of the ceramic body 110 was less than 30 탆, no bending crack occurred but a defective delamination occurred .

Therefore, the distance E from the end of the lowermost internal electrode of the active layer 115 to the end of the external electrode covering a part of the lower surface of the ceramic body 110, which does not cause defects in flexural cracking and delamination experiments, (E / T) of the shortest distance T from the end of the external electrode to the lowermost internal electrode of the active layer 115 is 1.2 or more and the margin F in the longitudinal direction of the ceramic body 110 is 30 Mu m or more.

The mounting substrate of the multilayer ceramic capacitor

4 and 5, the mounting board 200 of the multilayer ceramic capacitor 100 according to the present embodiment includes a printed circuit board 210 mounted so that the multilayer ceramic capacitor 100 is horizontal, The first and second electrode pads 221 and 222 are spaced apart from each other on the upper surface of the first electrode pad 210.

In this case, the multilayer ceramic capacitor 100 is disposed such that the lower cover layer 113 is disposed on the lower side and the first and second external electrodes 131 and 132 are in contact with the first and second electrode pads 221 and 222, respectively And may be electrically connected to the printed circuit board 210 by soldering 230 in the state of FIG.

Acoustic noise may occur when a voltage is applied while the multilayer ceramic capacitor 100 is mounted on the printed circuit board 210 as described above.

The size of the first and second electrode pads 221 and 222 is equal to the size of the first and second external electrodes 131 and 132 and the first and second electrode pads 221 and 222 of the multilayer ceramic capacitor 100 The amount of the soldering 230 to be connected may be an index for determining the amount of the soldering 230 to be connected, and the magnitude of the acoustic noise may be adjusted according to the amount of the soldering 230.

6, when the multilayer ceramic capacitor 100 is mounted on the printed circuit board 210, the first and second external electrodes 131 and 132 formed at both ends of the multilayer ceramic capacitor 100 are polarized The ceramic body 110 expands and contracts in the thickness direction due to the inverse piezoelectric effect of the dielectric layer 111 and the first and second external electrodes 131 and 132 Both end portions contract and expand as opposed to the expansion and contraction in the thickness direction of the ceramic body 110 due to the Poisson effect.

Here, the central portion of the active layer 115 is the portion that is most expanded and contracted at both end portions in the longitudinal direction of the first and second external electrodes 131 and 132, and becomes a factor that causes acoustic noise.

The upper portion of the soldering 230 is caused to be pushed outward by the expansion and the lower portion of the soldering 230 is expanded by the expansion of the outside of the multilayer ceramic capacitor 100 (2) is generated due to the pushing force to the external electrode.

Therefore, as in the present embodiment, due to the difference between the strain rate generated at the center portion CL _A of the active layer 115 and the strain rate generated at the lower cover layer 113, If the inflection points formed on both end faces are formed below the height of the soldering 230, the acoustic noise can be further reduced.

Modification of internal electrode

On the other hand, impurities such as conductive foreign matter, moisture, and ions penetrate through the corner portions, which are relatively thinner than the central portion, on the surface where the internal electrodes are exposed, which may cause deterioration of insulation resistance and lower reliability.

In order to solve such a problem, internal electrodes of bottleneck patterns can be used. The present invention is applicable to the case of using internal electrodes of such a bottleneck pattern.

Figs. 7 to 13 are cross-sectional views showing various modifications of internal electrodes applied to a multilayer ceramic capacitor according to an embodiment of the present invention. Fig.

Referring to FIG. 7, the first and second internal electrodes 121 and 122 have first and second lead portions 121a and 122a extended to be alternately exposed through one end face of the dielectric layer 111, At this time, the corners where the first and second lead portions 121a and 122a and the first and second internal electrodes 121 and 122 are connected to each other may be formed to have an inclined surface tapering inward.

8, the corners connecting the first and second lead portions 121a and 122a and the first and second internal electrodes 121 and 122 may be curved.

9, the widths of the first and second lead portions 121a and 122a may be variously reduced or increased, and the widths of the first and second lead portions 121a and 122a may be inversely proportional to the widths of the first and second lead portions 121a and 122a. The area of the margin portion in the longitudinal direction of the dielectric layer 111 can be determined.

10, a corner portion connecting the first and second lead portions 121a and 122a and the first and second internal electrodes 121 and 122 is formed as a groove to form a corner portion of the dielectric layer 111, The occurrence of bending cracks and delamination can be reduced.

11, the first and second internal electrodes 121 and 122 are not provided with a separate lead portion and the first and second internal electrodes 121 and 122 have one end face of the dielectric layer 111 122c may be formed as an inclined surface so as to taper inward.

At this time, as shown in FIG. 12, the corner portions 121c and 122c of the first and second internal electrodes 121 and 122 may be curved.

13, the uncovered edge portions 121b and 122b of the first and second internal electrodes 121 and 122 may be formed as tapered inclined surfaces.

In order to minimize the occurrence of delamination, it is preferable that the longest length of the margin portion with respect to the front end face of the dielectric layer 111 is about twice the shortest length with respect to the start and end points of the corner portions 121b and 122b Do.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various changes and modifications may be made therein without departing from the scope of the invention. It will be obvious to those of ordinary skill in the art.

100; A multilayer ceramic capacitor 110; Ceramic body
111; A dielectric layer 112; The upper cover layer
113; A lower cover layer 115; Active layer
121, 122; The first and second internal electrodes
121a, 122a; The first and second lead portions
121b, 121c, 122b, 122c; Corner portion
131, 132; The first and second outer electrodes
200; Mounting substrate
210; Printed circuit board
221, 222; The first and second electrode pads
230; Soldering

Claims (12)

A ceramic body in which a plurality of dielectric layers are stacked;
An active layer including a plurality of internal electrodes alternately exposed through both end faces of the ceramic body with the dielectric layer interposed therebetween;
An upper cover layer formed on the active layer;
A lower cover layer formed under the active layer and having a thickness greater than that of the upper cover layer; And
An outer electrode formed to cover both ends and upper and lower surfaces of the ceramic body; / RTI >
A distance from the end of the lowermost internal electrode of the active layer to the end of the external electrode covering a part of the lower surface of the ceramic body is E and a shortest distance from the end of the external electrode to the lowermost internal electrode of the active layer Is T and the longitudinal direction margin of the ceramic body is defined as F, 1.2? E / T and satisfies the range of 30 占 퐉? F,
A half of the total thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, a half of the total thickness of the active layer is defined as C, and a thickness of the upper cover layer is defined as D time,
(B + C) / A satisfies a range of 1.063? (B + C) / A? 1.745, wherein the ratio of the center portion of the active layer to the central portion of the ceramic body satisfies (B + C) / A.
The method according to claim 1,
Wherein a ratio D / B between a thickness (D) of the upper cover layer and a thickness (B) of the lower cover layer satisfies a range of 0.021? D / B? 0.422.
The method according to claim 1,
Wherein a ratio B / A of a thickness (B) of the lower cover layer to a half (A) of the total thickness of the ceramic body satisfies a range of 0.329? B / A? 1.522. .
The method according to claim 1,
Wherein a ratio C / B of a total thickness (C) of the active layer to a thickness (B) of the lower cover layer satisfies a range of 0.146? C / B? 2.458. .
The method according to claim 1,
An inflection point formed on both end faces of the ceramic body is formed below a central portion of the thickness of the ceramic body due to a difference between a strain rate generated at a center portion of the active layer and a strain rate generated at the lower cover layer at the time of voltage application. Multilayer Ceramic Capacitors.
The method according to claim 1,
Wherein the first and second internal electrodes are formed such that a portion exposed through an end surface of the ceramic body is tapered inward.
The method according to claim 1,
Wherein the first and second internal electrodes are formed such that corner portions of the other surface that are not exposed to the outside of the ceramic body are tapered inward.
A printed circuit board having a pair of electrode pads on the top; And
A multilayer ceramic capacitor mounted on the printed circuit board; / RTI >
The multilayer ceramic capacitor includes:
A ceramic body in which a plurality of dielectric layers are stacked; An active layer including a plurality of internal electrodes alternately exposed through both end faces of the ceramic body with the dielectric layer interposed therebetween; An upper cover layer formed on the active layer; A lower cover layer formed under the active layer and having a thickness greater than that of the upper cover layer; First and second external electrodes formed to cover both end faces of the ceramic body and connected to the pair of electrode pads by soldering; / RTI >
A distance from the end of the lowermost internal electrode of the active layer to the end of the external electrode covering a part of the lower surface of the ceramic body is E and a shortest distance from the end of the external electrode to the lowermost internal electrode of the active layer Is T and the longitudinal direction margin of the ceramic body is defined as F, 1.2? E / T and satisfies the range of 30 占 퐉? F,
A half of the total thickness of the ceramic body is defined as A, a thickness of the lower cover layer is defined as B, a half of the total thickness of the active layer is defined as C, and a thickness of the upper cover layer is defined as D (B + C) / A satisfies a range of 1.063? (B + C) /A? 1.745 when the center of the active layer deviates from the center of the ceramic body.
9. The method of claim 8,
Wherein a ratio D / B between a thickness (D) of the upper cover layer and a thickness (B) of the lower cover layer satisfies a range of 0.021? D / B? 0.422.
9. The method of claim 8,
Wherein a ratio B / A of a thickness (B) of the lower cover layer to a half (A) of the total thickness of the ceramic body satisfies a range of 0.329? B / A? 1.522. .
9. The method of claim 8,
Wherein a ratio C / B of a total thickness (C) of the active layer to a thickness (B) of the lower cover layer satisfies a range of 0.146? C / B? 2.458. .
9. The method of claim 8,
Wherein an inflection point formed on both end faces of the ceramic body is formed below the height of the soldering due to a difference between a strain rate generated at a center portion of the active layer and a strain rate generated at the lower cover layer when a voltage is applied, .

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