KR101480954B1 - NUMA System Scheduling Apparatus and Secheduing Method Therefor - Google Patents

Abstract

The scheduling apparatus of the present invention includes: a NUMA system having a plurality of nodes each including a core executing a process, a public cache, and a memory, and acquiring memory access information per core; A NUMA system evaluation unit for evaluating memory access performance of a current process-core mapping and a future process-core mapping of the NUMA system according to the core memory access information obtained in the NUMA system; And a process scheduler that applies one of the current process-core mapping and the future process-core mapping as a process-core mapping of the NUMA system according to the evaluation result of the NUMA system evaluation unit.

Description

 [0001] NUMA System Scheduling Apparatus and Method [0002]

The present invention relates to a scheduling apparatus and method for a NUMA system. More particularly, the present invention relates to a scheduling apparatus and method capable of improving optimization and / or fairness of memory access to a NUMA system.

The asymmetric non-uniform memory access (NUMA) system has asymmetry that varies depending on the core in which the access time of the physical memory accessed by a particular CPU (Central Processing Unit) is performed. The CPU may be referred to as a core. This phenomenon is caused by the structural characteristics of the asymmetric memory system. In the asymmetric memory system, there is a time difference between accessing memory belonging to a local node and accessing a memory belonging to a remote node.

There is a need to provide a technique for optimizing the overall memory access performance of such an asymmetric memory access system while allowing fair access to the memory access time per core for the asymmetric memory access system.

Korean Registration Bulletin No. 10-1145144 (April 5, 2012)

SUMMARY OF THE INVENTION The present invention is directed to provide a scheduling apparatus and method that can optimize memory access performance for an entire NUMA system, as set forth in order to meet the needs of the prior art.

The present invention also provides a scheduling apparatus and method for allowing a memory access to a NUMA system to have fairness for each core.

The present invention also provides a scheduling apparatus and method capable of meeting the memory access requirements required for each process in the NUMA system.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

A scheduling apparatus according to an embodiment of the present invention includes: a NUMA system having a plurality of nodes each including a core for executing a process, a public cache, and a memory, and acquiring memory access information for each core; A NUMA system evaluation unit for evaluating memory access performance of a current process-core mapping and a future process-core mapping of the NUMA system according to the core memory access information obtained in the NUMA system; And a process scheduler for applying one of a process-core mapping of the current process-core mapping and the future process-core mapping to a process-core mapping of the NUMA system according to an evaluation result of the NUMA system evaluation unit.

The NUMA system scheduling method according to an embodiment of the present invention includes: acquiring memory access information per core in a NUMA system having a plurality of nodes each including a core, a common cache, and a memory for executing a process; Evaluating memory access capability of the current process-core mapping and future process-core mapping of the NUMA system in accordance with the per-core memory access information obtained in the NUMA system in the NUMA system evaluation unit; Core mapping of one of the current process-core mapping and the future process-core mapping in a process scheduler according to an evaluation result of the NUMA system evaluation unit as a process-core mapping of the NUMA system .

According to the present invention, it is possible to provide a scheduling apparatus and method capable of optimizing memory access performance for the entire NUMA system.

Also, according to the present invention, it is possible to provide a scheduling apparatus and method for allowing memory access to the NUMA system to have fairness for each core.

Also, according to the present invention, it is possible to provide a scheduling apparatus and method capable of satisfying a memory access requirement required for each process in a NUMA system.

1 illustrates a NUMA system according to an embodiment of the present invention.
2 illustrates a scheduling apparatus according to an embodiment of the present invention including the NUMA system shown in FIG.
FIG. 3 is a diagram illustrating a process of predicting a memory access latency in a scheduling apparatus according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a process of determining a cause of an increase in memory access latency in a scheduling apparatus according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a solution process according to a cause of an increase in memory access latency in a scheduling apparatus according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity of explanation and the same reference numerals are used for the same elements and the same elements are denoted by the same quote symbols as possible even if they are displayed on different drawings Should be. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

Hereinafter, a NUMA system according to an embodiment of the present invention and a scheduling apparatus and method thereof will be described with reference to the accompanying drawings.

Figure 1 illustrates a NUMA system 100 in accordance with an embodiment of the present invention. The NUMA system 100 is an asymmetric memory access (NUMA) system, which refers to a system in which memory access time or memory access latency is not uniform on a per-core basis. The NUMA system according to the embodiment of the present invention may include a plurality of nodes, and it is exemplified that the node includes two nodes 11 and 12 in FIG. In general, one process corresponds to one node, and a plurality of nodes may mean that a plurality of processors are included. Depending on the embodiment, one process may have a plurality of nodes.

The number of cores included in each of the nodes 11 and 12 is variable and may generally include 4 to 8 cores per node. 1 illustrates that the first node 11 includes the first to fourth cores core1 to core4 and the second node 12 includes the fifth to eighth cores core5 to core8. do.

In the NUMA system 100 of the present invention, the memory area is divided into 20 and dotted lines and may be referred to as the memory subsystem 20. A memory access request from the core means a request to access the memory subsystem 20.

A NUMA (100) system according to an embodiment of the present invention may include public caches 31 and 32 in a memory subsystem 20. The first public cache 31 may be shared by the four cores included in the first node 11 and the second public cache 32 may be shared by the four cores included in the second node 12. [ . In an embodiment of the present invention, the public caches 31 and 32 may be level 3 caches. Generally, each core has a level 1 (level 1) and level 2 (level 2) cache therein. Each node may also contain a level 3 cache that can be shared among the cores contained in the node. This level 3 cache may also be referred to as LLC (last-level chache).

The memory access request transmitted from the core searches the public caches 31 and 32 included in the same node and acquires desired data from the public caches 31 and 32 when a cache hit occurs. Hereinafter, this is referred to as a primary memory access request.

Each of the nodes 11 and 12 includes corresponding memories 61 and 62. That is, the first node 11 may include a first memory 61 and the second node 12 may include a second memory 62. At this time, the first memory 61 corresponds to the local memory and the second memory 62 corresponds to the remote memory with respect to the first node 11. Similarly, for the second node 12, the second memory 62 is a local memory and the first memory 61 is a remote memory. In the embodiment of the present invention, the first memory 61 and the second memory 62 may be a dual in-line memory module (DIMM), which is a memory module including a series of Dynamic Random-Access Memory (DRAM), for example.

When a cache miss occurs in the public caches 31 and 32, an actual memory access request is transmitted from the public caches 31 and 32 to the memory controllers 41 and 42 shown in FIG. Here, the actual memory access request is a request for access to the first memory 61 or the second memory 62 via the memory controller 41, 42, hereinafter referred to as a secondary memory access request.

That is, the memory controllers 41 and 42 store the local memory included in the same node 31 and 32 according to the secondary memory access request from the public caches 31 and 32 included in the same node 31 and 32, ). For example, the memory controller 41, 42 may handle approximately several gigabytes (GB) of memory accesses per second.

When a cache miss occurs in the public caches 31 and 32, access to the remote memory not included in the same node 31 and 32 is also possible. At this time, the secondary memory access requests from the public caches 31 and 32 may be transferred to the interconnection 51 and 52. For example, a secondary memory connection request from the first public cache 31 is transferred to the first interconnection 51 and then transferred to the second interconnection 52 included in the second node 12 via the first bus 71, And the second memory controller 42 may be used to achieve the connection to the second memory 62. [

Likewise, a secondary memory access request from the second public cache 32 is passed to the second interconnection 52 to be sequentially transferred to the second bus 72, the first interconnection 51 and the first memory controller 41 can be achieved.

Buses 71 and 72 are located between the interconnection 51 and 52 included in the different nodes 11 and 12, and each of the buses 71 and 72 may be unidirectional. Accordingly, two buses 71 and 72 are included between the first node 11 and the second node 12 to enable bidirectional communication. However, this is merely an embodiment, and bidirectional communication can be achieved between the first interconnection 51 and the second interconnection 52 via one bidirectional bus.

When accessing the remote memory via the interconnection 51, 52, it may have a memory access latency 1.5 times greater than accessing the local memory via the memory controller 41, 42. That is, when accessing the remote memory, it may take more time to access the local memory. At this time, the interconnection 51, 52 also has a predetermined processing capacity per hour and is generally lower than the processing capacity of the memory controllers 41, 42.

Processes can be defined as VCPUs (virtual CPUs) of applications or virtualization system software that are generally running in the operating system. The process becomes a unit of execution in the core. Each process can have its memory in any memory area. When a core executes a specific process, the core generates a memory access request to a memory area that has the memory of that process. For example, the first process (Proc. 1) may be executed in the first core (Core 1), and the memory of the first process may be included in the first memory 61 or the second memory 62. Thus, the first core may generate a memory access request to the first memory 61 or the second memory 62 when the first core executes the first process.

A process can be executed in any core and its memory can be included in a memory area included in any node. Various mappings between the process and the core to execute it are possible, and the memory of the process can be migrated. For example, the memory of the first process Proc. 1 can be migrated to the second memory 62 of the second node 12 even if it is included in the first memory 61 of the first node 11.

In Figure 1 it is illustrated that the NUMA system comprises eight processes and eight cores. At this time, the first process (Proc.1) is executed in the first core (Core1), the second process (Proc.2) is executed in the second core (core 2), the eighth process Although mapped to be executed on the eighth core (Core 8), this is merely an example, and any process can be mapped to run on any core. At one time, one process can be executed by occupying one core.

As shown in FIG. 1, in the NUMA system 100 according to the embodiment of the present invention, there are four factors described below that affect the latency of accessing the memory.

First, the memory of a particular process is located in either the local memory or the remote memory. For example, the first process Proc. 1 is running in the first core (Core 1), but the first process memory may be included in any one of the first node 11 or the second node 12. If the first process memory is included in the first memory 61 of the first node 11, it is included in the local memory and if the first process memory is included in the second memory 62 of the second node 12, It is contained in remote memory. The memory access latency can vary depending on whether the memory of the process running on the core is located in local memory or remote memory.

Second, whether or not the memory controllers 41 and 42 are overloaded. For example, if all of the first to eighth processes (Proc. 1 to Proc. 8) include the corresponding process memory in the first node 11, the first memory controller 41 of the first node 11 Only memory access occurs. In this case, an overload occurs in the first memory controller 41, which massages the queuing of the memory access request.

Third, whether or not the interconnection 51 or 52 is overloaded. For example, when the process memory of the first to fourth processes (Proc. 1 to Proc. 4) executing in the core included in the first node 11 is located at the second node 12, To the second memory controller 42 via the first interconnection 51 and the second interconnection 52. [ At this time, an overload of the interconnection 51, 52 occurs, which causes queuing of the memory access request.

Fourth, whether or not the public caches 31 and 32 are overloaded. For example, when a large number of memory access requests are generated in the execution of the first process and the second process (Proc. 1 and Proc. 2) executed in the core of the first node 11, The cache hit ratio for the first public cache 31 of the first node 11 will be relatively lower than the cache hit ratio for the second public cache 32 of the second node 12, This means that more secondary memory access requests occur. That is, overloading the public caches 31 and 32 causes a high cache miss ratio. This implies an increase in the secondary memory access request, so that the latency can be increased.

As described above, it is apparent that the memory access performance can be changed according to the access path to the process memory required for executing the process assigned to each core. That is, memory access performance may vary depending on the CPU scheduling method that determines which cores the process will run on. Therefore, it is necessary to consider the factors that affect the above-mentioned memory access latency in CPU scheduling.

In the embodiment of the present invention, a scheduling apparatus and method for optimizing memory access performance in the NUMA system 100 may be proposed. In addition, a scheduling apparatus and a method for allowing a memory access latency to be processed for each core are proposed. Thus, a normalized memory access latency per core can be provided. Also, embodiments of the present invention provide a scheduling apparatus and method that can satisfy a demand for a memory access latency on a per-process basis.

FIG. 2 illustrates a scheduling apparatus according to an embodiment of the present invention for the NUMA system shown in FIG. The scheduling apparatus 400 according to the embodiment of the present invention may be configured to include the NUMA system 100, the process scheduler 200, and the evaluation unit 300 of the NUMA system.

In the NUMA system 100, memory accesses occur in parallel for a plurality of cores, so that collisions in the shared resources, e.g., the public caches 31 and 32, the memory controllers 41 and 42 and the interconnection 51 and 52, there is a difference in latency during memory access when contention occurs. The difference in latency during the memory access affects the memory access performance of the entire NUMA system 100 and the memory access performance of each core.

The scheduling apparatus 400 according to the embodiment of the present invention can perform a process-to-core mapping that can fair memory access performance for each core while optimizing memory access performance for the entire NUMA system 100. [ In addition, the scheduling apparatus 400 according to an embodiment of the present invention can provide a memory access latency requested by a user for a specific process, for example.

In the scheduling apparatus 400 according to the embodiment of the present invention, the NUMA system 100 may acquire memory access information for each core and provide the memory access information to the process scheduler 200. The memory access information per core obtained in the NUMA system 100 may include mapping information between the current core and the process. In addition, the memory access information for each core may include location information of the process memory for each process. In addition, the memory access information for each core may include the number of accesses to the public caches 31 and 32 and the number of cache misses for each core obtained through a hardware monitoring unit (not shown). Thus, memory access patterns of processes allocated to each core can be known.

The hardware monitoring unit according to the embodiment of the present invention may be a hardware PMU (Performance Monitoring Unit) generally included in the CPU chips. A monitoring unit, referred to as a hardware PMU, can be used to store the number of occurrences of a specific event set by the user using the hardware in the CPU during instruction execution in a register area of the CPU, and to return the corresponding information when the user requests have.

Using these PMUs, the clock cycle, the number of instructions performed, the number of accesses and misses to the level 1 cache, the number of accesses and misses to the level 2 cache, the number of accesses to the level 3 cache, The number of times can be collected. In this case, in the NUMA system 100 according to the embodiment of the present invention, the level 3 cache obtained by the PMU, that is, the access count and the miss count for the public caches 31 and 32, may be used in scheduling.

The NUMA system evaluation unit 300 included in the scheduling apparatus 400 according to the embodiment of the present invention evaluates the memory access performance of the NUMA system 100 according to the specific scheduling. This performance evaluation can be performed at the request of the process scheduler 200. [ The evaluation unit 300 of the NUMA system according to the embodiment of the present invention can evaluate memory access performance by process using the memory access information per core transmitted from the process scheduler 200. [ At this time, the memory access performance per process can be evaluated through modeling using the memory access information per core.

The functions of the performance evaluation unit 300 of the NUMA system according to the embodiment of the present invention can be largely divided into the following two.

First, the memory access performance of the current process-core mapping according to the current process-core mapping is evaluated. This can be done by evaluating the process-by-process memory access latency associated with the current process-core mapping. Based on this, it is possible to evaluate the memory access performance and the memory access fairness per core of the NUMA system 100 as a whole (1-1). In addition, it can provide an increase factor of memory access latency (1-2). Such an evaluation may be performed at the request of the process scheduler 200 and the results may be returned to the process scheduler 200. [

FIG. 3 is a diagram illustrating a process of predicting a memory access latency in the scheduling apparatus 400 according to an embodiment of the present invention. More specifically, FIG. 3 illustrates a process of predicting a memory access latency in the evaluation unit 300 of the NUMA system according to an embodiment of the present invention. In FIG. 3, a primary memory access request to the memory subsystem 20 generated from the core is denoted by Refs, and this primary memory access request is passed to the public cache 30 (31, 32). When a cache miss occurs in the public cache 30, a secondary memory access request is transmitted to the memory 60 (61, 62), which is indicated as Miss in FIG.

At this time, the memory access latency (mL) for the actual memory access request, i.e., the secondary memory access request, can be obtained according to the following equation, for example.

1 sec = MPS * mL + (RPS-MPS) * cL + I * CPI (1)

Here, 1 second represents a time period of 1 second. The MPS (misses per second) represents the number of cache misses per second and the RPS (Refs per Second) for the common cache 30 (31,32) represent the number of times per second of the primary memory access request, which are obtained from the PMU in the NUMA system 100 Lt; / RTI > Also, cL (Cache Access Latency) is the latency when accessing the public cache 30 (31, 32), which can be specified in the specification of the CPU. I (# of Instructions) represents the number of instructions executed on the core, which can also be obtained from the PMU. The CPI (Cycles per Memory Subsystem) represents the number of instructions that do not cause a memory access request and can be fixed by repeated experiments.

FIG. 4 is a diagram illustrating a process of determining a cause of an increase in memory access latency in a scheduling apparatus according to an embodiment of the present invention. More specifically, FIG. 4 is a diagram illustrating a process of predicting an increase in memory access latency in the evaluation unit 300 of the NUMA system according to an embodiment of the present invention.

4, the evaluation unit 300 of the NUMA system according to the embodiment of the present invention utilizes the information on the number of cache misses (30: 31, 32) accesses and cache misses for each process, The location where the bottleneck phenomenon occurs with respect to the shared resource can be grasped. This can be done by modeling the shared resource part. That is, the memory access path can be known for each process based on the execution position of each process, that is, the information about the execution core and the position of the process memory. This allows you to know the number of memory accesses per second that are being applied to each shared resource. Such information can be used to determine the load applied to each shared resource, and it can be determined whether or not the bottleneck is caused by comparing the applied load with the maximum load that the shared resource can afford.

In Fig. 4, the predicted load for each shared resource generated by the processes (Proc. 1 to Proc. 4) performed in the first node 11 is shown. That is, the application load for the first memory controller 41, the interconnection 51, 52 and the second memory controller 42 can be predicted as follows.

CM_SUM _MC1 = A (Equation 2)

CM_SUM _ICitok = B (Equation 3)

CM_SUM _MC2 = B (Equation 4)

Where A is the cache misses per second (CMPS) for the first memory 61 included in the first node 11 and is the number of cache misses per second for the first public cache 31 per second, Indicates a cache miss. Here, the first memory 61 is a local memory. B is the CMPS for the second memory 62 included in the second node 12 and is the cache miss for the first public cache 31 per second that has to be delivered to the remote memory. The second memory 61 corresponds to the remote memory in terms of the first node 11.

CM_SUM _MC1 represents the sum of the cache misses for the i-th memory controller (the first memory controller 41 in Fig. 4). CM_SUM _ICitok represents the sum of cache misses for which memory accesses to remote memory should occur. CM_SUM _MC2 represents the sum of cache misses for which memory access to the second memory controller 42 should occur. Since FIG. 4 illustrates the case of including two nodes, the CM_SUM _ICitok and the CM_SUM _MC2 t can be illustrated as having the same value.

Second, the evaluation unit 300 of the NUMA system according to an embodiment of the present invention can also evaluate memory access performance according to future process-core mappings. This can be done by evaluating the process-by-process memory access latency associated with future process-to-core mappings. That is, the evaluation unit 300 of the NUMA system can predict and evaluate the memory access performance according to a future process-core mapping according to a request of the process scheduler 200. [ Based on this, in the case of the NUMA future process-core mapping, the memory access performance for the entire system 100 and the fairness of memory access for each core can be evaluated (2-1). It can also provide an increase in memory access latency (2-2). Such an evaluation may be performed at the request of the process scheduler 200 and the results may be returned to the process scheduler 200. [

In the future process-core mapping, the memory access performance and core access fairness evaluation (2-1) and the memory access latency increase factor (2-2) are as follows. Can be predicted in the same manner as in the case of FIG.

The memory access information of the future process - core mapping should be deduced from the current memory access information. This is because the memory access information per core obtained from the PMU is in accordance with the current process-core mapping. It can also be assumed that the same process always has a similar work load. Thus, the same RPKI (Reference Per 1000 Instructions) can be assumed regardless of the mapping. That is, it can be assumed that the number of memory access requests to the memory subsystem 20 generated per 1000 instructions is the same.

As a first step of preprocessing, RPKI for each process can be acquired as in the above (Step 1). Thereafter, the number of accesses to the public caches 31 and 32 is calculated by applying the future process-core mapping (step 2). The MPKI (Misses Per 1000 Instructions) is calculated using a table of cache miss counts for access counts of the public caches 31 and 32 created at the time of execution of the actual instruction (third step). That is, in the third step, the number of cache misses of the public caches 31 and 32 per 1000 instructions can be calculated. Using this, MPS (Missing per second) is calculated for each process (Step 4).

After the four stages of preprocessing as described above, the memory access performance and the memory access fairness evaluation (2-1) for the entire NUMA system 100 for the future process-core mapping (2-1) and the increase factor of the memory access latency (2-2) can be predicted. These (2-1) and (2-2) can be achieved in the same manner as the (1-1) and (1-2) functions for the current process-core mapping. That is, similar to the process-core mapping of the actual NUMA system 100, the load is calculated for each shared resource and compared with the maximum capacity for each resource to determine whether or not the resource is contention. Thus, MPS is increased in proportion to the MPKI, You can monitor resource-specific loads. The MPS when the load of one resource is close to the maximum capacity is defined as the inferred MPS, and the same functions as those of (1-1) and (1-2) can be performed.

The process scheduler 200 according to an embodiment of the present invention determines the process-core mapping of the NUMA system 100 and applies it to the NUMA system 100 based on the results from the evaluation unit 300 of the NUMA system. The operation of the process scheduler 200 can be performed according to the following two types.

(A) The process scheduler 200 optimizes the memory access performance of the entire NUMA system 100 and the memory access performance fairness per core based on the performance evaluation results of the current process-core mapping and all possible future process-core mapping cases. You can choose a mapping case that satisfies all. At this time, a performance score (Mcredit) may be assigned to each current and future process-core mapping case, and the mapping of the NUMA system 100 may be applied according to the process-core mapping having the highest score.

For example, if the performance of the current process-core mapping represents the highest score in terms of fairness and optimization, the process scheduler 200 allows the NUMA system 100 to maintain current process-core mappings. Also, if the performance of any future process-core mapping indicates the highest score, the process scheduler 200 may apply the NUMA system 100 to be mapped according to the corresponding future process-core mapping.

At this time, the memory access performance for the entire NUMA system 100 can be evaluated from the average value of the memory access latency for the entire system 100 indicated as follows.

수식(5)Average value of memory access latency =

Equation (5)

Where Li represents the memory access latency for process i. Mi represents the number of accesses of process i to the memory subsystem 20. At this time, the smaller the average value of the memory access latency represented by the equation (5) is, the higher the score (Mcredit) can be obtained.

In addition, the fairness of the memory access latency for each process can be obtained with a higher score (Mdredit) as the standard deviation of the memory access latency Li for each process is smaller. It shows the ideal fairness when the standard deviation of the process-specific memory access latency is zero.

According to this type, it is possible to select an optimal mapping case that satisfies both optimization and fairness needs. However, the amount of computation for determining the mapping may increase excessively.

The second type is described below.

(B) The process scheduler 200 may determine the process-core mapping by removing the increasing factors of the memory access latency of the current process-core mapping passed from the NUMA system evaluation unit 300. [

First, the factor that has the greatest influence on the increase in the process-memory access latency of the current process-core mapping predicted by the NUMA system evaluation unit 300 is identified. This process can be performed in the process scheduler 200 from the NUMA system evaluation unit 300 and transferred to the process scheduler 200 or from the NUMA system evaluation unit 300 for the increase in memory access latency.

Process scheduler 200 then changes the location of the core-to-process mapping and / or process memory in a direction that eliminates the largest cause of the increase in memory access latency to determine the future process to be evaluated in the NUMA system evaluation unit 300 - Determine the core mapping. That is, the converted core-process mapping through the overload removal process can be determined.

FIG. 5 illustrates an overload removal process according to an increase in memory access latency in a scheduling apparatus according to an exemplary embodiment of the present invention.

First, the contention resolver process in the case where the overload of the memory controller is the biggest cause of increasing the memory access latency is illustrated in FIG. 5 (a). For example, the memory of the most memory-intensive processes among the processes using the overloaded memory controller and the location of the core executing the process may be migrated to another node. It is necessary to change the position of the process memory because the overload problem can not be solved simply by changing the position of the core executing the process. The core and process memory migrated in Fig. 5 (a) are located at node 1 (n1) and are illustrated as migrating to node 4 (n4). At this time, as shown in FIG. 5 (a), it is possible to exchange the positions of the core and the process memory with the process having the least memory access among the processes executing in the node 4 migrated.

Secondly, if the overload of the interconnection is the biggest cause of increasing the memory access latency, the overload removal process is illustrated in FIG. 5 (b). In this case, the execution core location of the process that most frequently accesses the remote memory can be changed to one of the cores included in the target node where the memory of the process is located. At this time, it is possible to select and exchange a process having the least memory access among the processes running on the target node.

Third, the overload removal process is illustrated in (c) of FIG. 5 when the overhead of the common cache is the biggest cause of increasing the memory access latency. In this case, even if a remote memory access occurs, a process that can gain the greatest gain as the cache hit probability for the public cache rises can be changed to be executed in the core of another node in the currently executing core . At this time, it is possible to exchange a core that is expected to be least damaging among the processes executing in the cores of other nodes.

The performance evaluation is performed in the NUMA system evaluation unit 300 for the future process-core mapping that has undergone the overload removal process as exemplified above, and the score for the memory access performance (Mcredit) is the same as in Type 1 Loses.

Then, the score of the memory access performance (Mcredit) for the current process-core mapping is compared with the score of the memory access performance (Mcredit) for the overloaded future process-core mapping and the NUMA system 100 ) May be determined. For example, if the current core-process mapping can be maintained and the performance score for the future process-core mapping is higher if the performance score (Mcredit) for the current process-core mapping is higher, the future process- 100).

The future process-core mapping decision, mapping evaluation and application procedure through the overload removal process as described above can be repeated periodically and executed. For example, the above process can be repeatedly performed every about one second. In case of Type 2 (b), there is a disadvantage that the optimal mapping case can not be selected at a time, but the mapping can be adaptively transformed, resulting in a reduction in the calculation amount.

Although the process scheduler 200 has evaluated the performance of the process-core mapping based on the optimization of the memory access performance for the entire NUMA system 100 and the fairness of the memory access latency per core, Only the optimizations can be used as a basis for judging, or only the fairness of the memory access latency of each core can be used as a judgment criterion. In addition, a performance evaluation can be made to meet the process-specific memory access latency that meets the needs of the user.

In the scheduler apparatus 400 according to an embodiment of the present invention, the process scheduler 200 and / or the NUMA system evaluating unit 300 may include a hardware module and / or a software module (not shown) . ≪ / RTI >

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. will be. Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, It is intended that all changes and modifications derived from the equivalent concept be included within the scope of the present invention.

11, 12: a first node and a second node
20: memory subsystem
30, 31, 32: Common cache
40, 41, 42: memory controller
50,51,52: Interconnection
60, 61,
100: NUMA system
200: Process Scheduler
300: NUMA system evaluation unit
400: scheduler device

Claims (18)

A NUMA system having a plurality of nodes each including a core executing a process, a public cache and a memory, and obtaining memory access information per core;
A NUMA system evaluation unit for evaluating memory access performance of a current process-core mapping and a future process-core mapping of the NUMA system according to the core memory access information obtained in the NUMA system; And
Core mapping of one of the current process-core mapping and the future process-core mapping according to an evaluation result of the NUMA system evaluation unit as a process-core mapping of the NUMA system.
NUMA system scheduling device. The method according to claim 1,
The memory access information per core includes:
Information about the current process-core mapping, location information of a process memory for each process, and access counts to the common cache for each core, and a miss count for the common cache,
Wherein the core-specific memory access information is passed to the NUMA system evaluation unit via the process scheduler,
NUMA system scheduling device. The method according to claim 1,
The memory access performance evaluation for the current process-core mapping includes:
Wherein the at least one of the overall memory access performance evaluation for the NUMA system and the core memory access fairness evaluation based on a process-by-process memory access latency calculation result according to the current process-
NUMA system scheduling device. The method according to claim 1,
The memory access performance evaluation for the future process-core mapping includes:
A memory access performance evaluation for the NUMA system based on a process-specific memory access latency calculation according to the future process-core mapping, and a core memory access fairness evaluation for the NUMA system.
NUMA system scheduling device. 5. The method of claim 4,
The NUMA system evaluation unit prior to the evaluation of the memory access performance for the future process-
A first step of acquiring the number of memory access requests generated per 1000 instructions per process;
A second step of calculating an access count for the common cache for each process;
A third step of calculating the number of cache misses for the common cache per 1000 instructions; And
And a fourth step of calculating a number of cache misses for the common cache per second per process,
NUMA system scheduling device. 6. The method according to any one of claims 1 to 5,
The future process-core mapping includes a plurality of future process-core mappings,
Wherein the process scheduler applies to the NUMA system a process-core mapping having the highest performance evaluation among the plurality of future process-core mappings and the current process-
NUMA system scheduling device. delete 6. The method according to any one of claims 1 to 5,
The process scheduler comprising:
Determining a future process-core mapping through an overload removal process that removes the largest factor among the increase factors of the memory access latency,
NUMA system scheduling device. 9. The method of claim 8,
Wherein the overload removal process changes at least one of a location of a core that performs a process to increase the memory access latency and a location of a memory of a process that increases the memory access latency,
NUMA system scheduling device. Acquiring per-core memory access information in a NUMA system having a plurality of nodes each including a core executing a process, a public cache, and a memory;
Evaluating memory access capability of the current process-core mapping and future process-core mapping of the NUMA system in accordance with the per-core memory access information obtained in the NUMA system in the NUMA system evaluation unit; And
Core mapping of one of the current process-core mapping and the future process-core mapping in a process scheduler according to an evaluation result of the NUMA system evaluation unit as a process-core mapping of the NUMA system.
NUMA system scheduling method. 11. The method of claim 10,
The memory access information per core includes:
Information on the current process-core mapping, location information of a process memory for each process, access counts to the common cache per core, and miss counts for the public cache,
Wherein the core-specific memory access information is passed to the NUMA system evaluation unit via the process scheduler,
NUMA system scheduling method. 11. The method of claim 10,
Wherein evaluating the memory access capability for the current process-core mapping comprises:
Calculating a process-by-process memory access latency in accordance with the current process-to-core mapping to evaluate at least one of an overall memory access performance for the NUMA system and a per-
NUMA system scheduling method. 11. The method of claim 10,
Evaluating the memory access capability for the future process-to-core mapping comprises:
And evaluating at least one of a total memory access performance for the NUMA system and a per-core memory access fairness by calculating a per-process memory access latency according to the future process-core mapping.
NUMA system scheduling method. 14. The method of claim 13,
The NUMA system evaluation unit prior to the evaluation of the memory access performance for the future process-
A first step of acquiring the number of memory access requests generated per 1000 instructions per process;
A second step of calculating an access count for the common cache for each process;
A third step of calculating the number of cache misses for the common cache per 1000 instructions; And
And a fourth step of calculating a number of cache misses for the common cache per second per process,
NUMA system scheduling method. 15. The method according to any one of claims 10 to 14,
The future process-core mapping includes a plurality of future process-core mappings,
In the applying step, the process scheduler applies to the NUMA system a process-core mapping having the highest performance evaluation among the plurality of future process-core mappings and the current process-core mappings.
NUMA system scheduling method. delete 15. The method according to any one of claims 10 to 14,
Wherein in the application step, the process scheduler further comprises determining the future process-core mapping through an overload removal process that removes the largest factor of the increase in the memory access latency.
NUMA system scheduling method. 18. The method of claim 17,
Wherein the overload removal process changes at least one of a location of a core that performs a process to increase the memory access latency and a location of a memory of a process that increases the memory access latency,
NUMA system scheduling method.

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