KR101471611B1 - Multi-channel SAR-typed ADC apparatus with reference voltage fluctuation preventing scheme and method using the same - Google Patents

Abstract

An apparatus and a method for a multi-channel SAR type ADC employing a reference voltage fluctuation prevention scheme are provided. According to an embodiment of the present invention, each ADC provided in an ADC apparatus forms an input voltage, which is a voltage of an analog input signal, and a reference voltage, compares the input voltage with the reference voltage to output a comparison result as digital data, records the comparison result to be externally outputted and performs a connection operation together with another ADC to form a reference voltage. Therefore, a reference is prevented from fluctuating in a section where the input voltage and the reference voltage are compared, so that a malfunction by a reference fluctuation inputted into a comparison unit of channels being compared can be prevented, and thus a high resolution ADC can be provided.

Description

[0001] The present invention relates to a multi-channel SAR-type ADC apparatus and method using reference voltage fluctuation prevention technique,

The present invention relates to an ADC apparatus and method, and more particularly, to a multi-channel SAR type ADC apparatus and method for processing an input signal in multiple.

There are two types of analog-to-digital converters: an oversampling ADC with a fast sampling rate versus the bandwidth of the input analog signal, a Nyquist ADC with a sampling rate higher than the Nyquist sampling rate versus the bandwidth of the input analog signal, And Pipeline, Flash, and SAR-type ADCs with a quiescent sampling rate.

Flash type ADCs generally have a comparator for each reference comparison point, so the power consumption and the area occupied by the chip increase as the resolution increases. In addition, the Pipeline type ADC has op-amps to amplify the residues after comparison for each stage, and there is a lot of power consumption because the constant current flows through the amplifier.

In order to compensate for the drawbacks of a lot of power consumption, recently, successive approximation register (SAR) type ADC has been spotlighted, and much research is being conducted.

1 is a diagram showing a SAR type ADC. The illustrated SAR type ADC is basically a structure for deriving the final digital result through a plurality of rounds of comparison after one sampling and includes a CDAC 10, a comparison unit 20, a write unit 30, and a logic unit 40, .

The CDAC 10 forms an analog voltage to be compared with the sampled value using a capacitor. The comparator 20 compares the differences of the analog voltage values to produce a digital value. The recording unit 30 records the comparison result of the comparison unit 20 and the logic unit 40 receives the comparison result value recorded in the recording unit 30 and connects the necessary reference voltage to the CDAC 10.

2 is a conceptual diagram showing a cyclic conversion speed of a SAR type ADC. 2, the SAR type ADC cyclic conversion speed is calculated by the following equation: 1) a comparison time S20 by the comparison unit 20, 2) a comparison result storage time S30 by the writing unit 30, 3) The comparison result processing time (S40) by the logic unit (40), and 4) the reference settling time (S10) by the CDAC (10).

The comparison time S20 by the comparator 20 appears in inverse proportion to the magnitude of the comparator voltage difference due to the analog voltage formed in the CDAC 10. In view of this point, in recent years, the write unit 30 is implemented as an SR latch A technique of previously storing the comparison result of the comparison unit 20 in advance and reducing the comparison time 20 substantially through the desired reference operation to the CDAC 10 is widely used without having to wait for the clock signal for storage .

3 is a diagram showing a comparison between a SAR type ADC using the SR latch as the write unit 30 and a SAR type ADC using the D-FF as the write unit 30. [

When a D-FF is used as the recording unit 30 as shown in FIG. 3 (a), there is a burden of generating a clock of? 2 in order to record the output of the recording unit 30, You can see that there is setup time and hold time to record properly. Due to the hold time, the rising edge of Φ2 must precede the falling edge of Φ1, and the hold time must be designed to be wider than the minimum condition for safety because it has the same amount in all storage processes.

3 (b), when the SR latch is used as the write unit 30, since the output of the write unit 30 is output, data is recorded with a D-to-Q delay without additional clock, It is possible to record data more stably than the conventional method.

4 is a diagram showing a multi-channel SAR type ADC device. In order to increase the speed, it is often the case that the SAR type ADC is used in a plurality of channels as shown in FIG. 4 to operate at a higher conversion speed than the SAR type ADC of the single channel.

The multi-channel SAR type ADC shares the reference voltage. When the SR latch is used as the write unit 30 and the comparison result of the comparison unit 20 is derived, the delay of the write unit 30 and the logic unit 40 Leads directly to a reference operation of the CDAC 10, a large amount of charge is instantaneously removed from the reference, causing a change in the reference voltage, which ultimately affects the other channels being compared, sharing the reference, Causing the section 20 to derive an erroneous comparison result value that is independent of the analog input.

That is, in a multi-channel SAR type ADC, a reference change that may be caused by directly manipulating the reference of the CDAC 10 through the SR latch acts as an obstacle to the implementation of a high-resolution ADC.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an ADC device and method capable of preventing a reference voltage variation which can be applied to a multi-channel SAR type ADC using an SR latch have. In particular, the present invention provides an ADC apparatus and method for preventing a voltage variation from occurring in a reference of a CDAC provided in another channel connected when digital values are output from comparators of one or a plurality of channels.

According to an aspect of the present invention, there is provided an ADC device including a plurality of ADCs, each ADC including: a voltage shaping unit for forming an input voltage and a reference voltage, which are voltages of an analog input signal; A comparator for comparing the input voltage with the reference voltage and outputting a comparison result as digital data; A recording unit for recording the comparison result to the outside; A logic unit connecting the reference voltage to the forming unit; And a controller that controls the logic unit to perform the connection operation together with other logic units provided in other ADCs.

The plurality of ADCs may be combined to process analog input signals into multiple channels.

In addition, the controller can control the connection operation of the logic unit by an input controller driving clock.

The controller driving clock is a control clock for designating a first section in which the comparison section and another comparator provided in the other ADC can perform the comparison and output operation and a second section in which the comparison and output operation are not performed, When the controller driving clock designates the second section, perform the connecting operation of the logic section.

In addition, the controller may start controlling to perform the connection operation of the logic unit when the controller driving clock is changed from the first section to the second section.

The controller may control the controller to perform the connection operation of the logic unit when the recording unit has recorded the comparison result and the controller driving clock designates the second section.

In addition, the controller may be configured to determine whether the controller driving clock is changed from the second interval to the first interval while the recording unit has completed recording the comparison result and the controller is performing control to perform the coupling operation of the logic unit, And the logic unit can control to perform the connecting operation.

The recording unit may be an SR latch.

According to another embodiment of the present invention, there is provided an ADC method comprising: a plurality of ADCs each forming an input voltage and a reference voltage, which are voltages of an analog input signal; Comparing each of the plurality of ADCs with the input voltage and the reference voltage, and outputting the comparison result as digital data; Recording each of the plurality of ADCs for outputting the comparison result to the outside; And connecting the plurality of ADCs with the reference voltage at the same time.

As described above, according to the embodiments of the present invention, it is possible to prevent the reference from fluctuating in the section for comparing the input voltage and the reference voltage in the multi-channel SAR type ADC apparatus, It is possible to prevent a malfunction caused by a high-resolution ADC.

1 shows a SAR type ADC,
2 is a conceptual diagram showing a cyclic conversion speed of a SAR type ADC,
3 is a view showing a comparison between a SAR type ADC using a SR latch as a recording unit and a SAR type ADC using a D-FF as a recording unit,
4 shows a conventional multi-channel SAR type ADC device,
5 is a block diagram of a multi-channel SAR-type ADC device according to an embodiment of the present invention,
FIG. 6 is a detailed block diagram of the ADCs shown in FIG. 5,
7 is a diagram illustrating a two-channel ADC device for explaining the reference voltage fluctuation prevention, and FIG.
8 is a diagram showing the detailed configuration of the reference voltage fluctuation preventing apparatus 150 shown in FIG.

Hereinafter, the present invention will be described in detail with reference to the drawings.

5 is a block diagram of a multi-channel SAR-type ADC device according to an embodiment of the present invention. Hereinafter, for the sake of convenience of description, a "multi-channel SAR type ADC device" is abbreviated as a "multi-channel ADC device".

The multichannel ADC according to the present embodiment includes a DEMUX 210, ADCs 100-1, 100-2, ..., 100-n, and a MUX 220 as shown in FIG. do.

The demultiplexer 210 demultiplexes the input analog signals by intervals and sequentially outputs the demultiplexed signals to the ADCs 100-1, 100-2, ..., and 100-n.

The ADCs 100-1, 100-2, ..., and 100-n A / D-convert the analog signals of the corresponding period input through the DEMUX 210 and output the analog signals. The ADCs 100-1, 100-2, ..., and 100-n are coupled to process analog input signals into multiple channels and share the reference voltage.

Since the number of ADCs is n, the ADC device shown in FIG. 1 corresponds to an n-channel ADC device, where 'n' is an integer equal to or greater than 2 and determined according to requirements and specifications.

The MUX 220 multiplexes the outputs of the ADCs 100-1, 100-2, ..., 100-n and outputs a digital signal.

FIG. 6 is a detailed block diagram of the ADCs 100-1, 100-2,..., 100-n shown in FIG. Since the ADCs 100-1, 100-2, ..., and 100-n shown in FIG. 5 can be implemented with the same configuration, only one representative ADC is shown in FIG.

6, the ADC includes a CDAC 110, a comparison unit 120, an SR latch 130, a logic unit 140, and a reference voltage variation prevention unit 150. [

The CDAC 110 uses a capacitor to function as a voltage shaping element that forms the voltage of the analog input signal and forms the reference voltage to be compared with it.

The reference voltage generation by the CDAC 110 is controlled by the logic unit 140, which will be described later. Specifically, the logic unit 140 couples the reference voltage to the CDAC 110 so that the reference voltage is formed in the CDAC 110.

The input voltage formed by the CDAC 110 and the reference voltage are applied to the comparator 120. The comparator 120 compares the input voltage applied from the CDAC 110 with a reference voltage, and outputs the comparison result as digital data.

The SR latch 130 is a recording element for temporarily recording a comparison result output from the comparison unit 120 to output the comparison result to the outside. The SR latch 130 operates without a separate clock, and can be replaced with another device having the same performance.

Logic section 140 couples the reference voltage to CDAC 110. The connection operation of the logic unit 140 is controlled by the reference voltage fluctuation preventing device 150. [ That is, when the control signal is outputted from the reference voltage fluctuation preventing device 150, the logic unit 140 outputs a connection signal, and the reference voltage is connected to the CDAC 110 and applied.

The reference voltage fluctuation preventing circuit 150 operates by the 'preventive driving clock' to control the connecting operation of the logic unit 140. The inhibitor drive clock is applied to the reference voltage fluctuation preventing device 150 as well as the reference voltage fluctuation preventing device 150 provided in another ADC. That is, all the reference voltage fluctuation preventing devices 150 provided in the ADCs 100-1, 100-2, ..., and 100-n of the multi-channel ADC device are driven by the preventive driving clock.

Thus, all the reference voltage fluctuation preventing devices 150 provided in the ADCs 100-1, 100-2, ..., 100-n of the multi-channel ADC device are connected to the ADCs 100- The ADCs 100-1 and 100-n of the multi-channel ADC device are controlled so that all the logic units 140 provided in the ADCs 1, 100-2, ..., and 100- 2,..., 100-n, respectively.

To illustrate this, FIG. 7 illustrates a two-channel ADC device. In FIG. 7,? ₁ is a comparator driving clock for activating and operating the comparators 120, and /? ₁ is an inhibitor driving clock for activating and activating the reference voltage fluctuation preventors 150.

As shown in FIG. 7, both of φ ₁ (comparator driving clock) and / φ ₁ (preventing controller driving clock) are 'comparison periods in which the comparators 150 are activated to perform comparison and comparison output operations' The logical interval in which the logic units 140 generate an output signal to connect the reference voltage to the CDACs 110 in the inactive period so that the comparison units 150 do not perform comparison and comparison output operations is repeated.

7, all of the reference voltage fluctuation preventing devices 150 are operated at a time when / _{1 changes} to a high level logic interval, or more precisely, when / _{1 changes} to a high level logic interval, When all of the logic units 140 are connected to the CDAC 110 at the same time, the reference voltages are simultaneously connected to the logic units 140 when the units 150 do not perform comparison and comparison output operations.

8 is a diagram showing the detailed configuration of the reference voltage fluctuation preventing apparatus 150 shown in FIG. 8, the reference voltage fluctuation preventing circuit 150 includes an OR gate 151 and an AND gate 152. [

8, when the comparison result is completed in the SR latch 130 and an output is generated, and / phi ₁ is a logic level with a high level, the reference voltage fluctuation preventing circuit 150 outputs And the logic units 140 are all operated when the comparison units 150 do not perform comparison and comparison output operations.

8, the reference voltage fluctuation preventing device 150 generates an output by completing the comparison result recording in the SR latch 130 and generating an output in the reference voltage fluctuation preventing device 150 The logic sections 140 are all kept operating even when / ₁ is switched to the low-level comparison section.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

110: CDAC
120:
130: SR latch
140: Logic unit
150: Reference voltage fluctuation preventing device

Claims (9)

In an ADC device having a plurality of ADCs,
Each ADC,
A voltage forming unit for forming an input voltage and a reference voltage which are voltages of the analog input signal;
A comparator for comparing the input voltage with the reference voltage and outputting a comparison result as digital data;
A recording unit for recording the comparison result to the outside;
A logic unit connecting the reference voltage to the forming unit; And
And a controller for controlling the logic unit to perform the connection operation together with other logic units provided in other ADCs,
The controller comprising:
Controlling the connection operation of the logic unit by an input controller driving clock,
The controller driving clock includes:
A control section for designating a first section in which the comparison section and another comparison section provided in the other ADC can perform comparison and output operations and a second section in which the comparison and output operation are not performed,
The controller comprising:
And controls the logic unit to perform the connection operation when the controller driving clock designates the second section.
The method according to claim 1,
The plurality of ADCs include:
And the analog input signal is coupled to process multiple channels.
delete delete The method according to claim 1,
The controller comprising:
Wherein the control unit starts control to perform the connecting operation of the logic unit when the controller driving clock is changed from the first section to the second section.
The method according to claim 1,
The controller comprising:
And controls the logic unit to perform the connecting operation when the recording unit has completed recording the comparison result and the controller driving clock specifies the second section.
The method according to claim 6,
The controller comprising:
The logic section may perform the connection operation even if the controller drive clock is changed from the second section to the first section while the recording section has completed recording the comparison result and the controller is performing the connection operation of the logic section So as to perform the ADC operation.
The method according to claim 1,
Wherein,
SR latch.
The plurality of ADCs each forming an input voltage and a reference voltage, which are voltages of an analog input signal;
Comparing each of the plurality of ADCs with the input voltage and the reference voltage, and outputting the comparison result as digital data;
Recording each of the plurality of ADCs for outputting the comparison result to the outside; And
Concurrently coupling the reference voltage to the plurality of ADCs,
Wherein the connecting step comprises:
Controls a connection operation by an input driving clock,
The driving clock includes:
A control clock for designating a first section in which a plurality of ADCs can perform comparison and output operation and a second section in which the comparison and output operation are not performed,
Wherein the connecting step comprises:
And controls the coupling operation to be performed when the driving clock designates the second section.

Images