KR101465431B1 - Power conversion device and control method for semiconductor switches - Google Patents

Abstract

The present invention discloses a power conversion device and a control method for a semiconductor switch in the power conversion device. In particular, the power conversion device according to an embodiment of the present invention comprises: a DC link stage including two capacitors which are serially connected; a half-bridge circuit which includes two leg switch cells to be serially connected and which is connected in parallel with the DC link stage; two additional switches cells which are connected in series between the interconnection point of the capacitor and the interconnection point of the leg switch cells; and a resonant circuit which is connected between the interconnection point of the leg switch cells and a load terminal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power conversion apparatus,

The present invention relates to a power conversion apparatus and a method of controlling a semiconductor switch in the power conversion apparatus, and more particularly, to a power conversion apparatus using a partially modified half bridge circuit and a method of controlling the semiconductor switch in the power conversion apparatus.

Recently, researches for high efficiency and high density of power conversion devices have been actively conducted due to the development of industry and the spread of new and renewable energy. Power conversion devices are widely used in electric vehicles, wireless power systems, broadcasting communication devices, Power devices, low-voltage / high-current conversion devices, high-voltage conversion devices, and rechargeable batteries.

1 (a) and 1 (b) are circuit diagrams showing a conventional resonance converter which is generally used.

1 (a) is a resonance type converter using a full-bridge circuit 11 and FIG. 1 (b) is a resonance type converter using a half-bridge circuit 12.

The full bridge circuit 11 controls the four switch cells to use the input voltage of V _dc and the current of I / 2, but the half bridge circuit 12 controls the two switch cells so that the input of V _dc / 2 Voltage and current of I can be used. In addition, the user can configure the full bridge circuit 11 in a frequency modulation (FM) control scheme, an asymmetric duty cycle (ADC) control scheme, an asymmetric voltage cancellation (AVC) Phase shift (PS) control method can be utilized. However, in the case of configuring the half bridge circuit 12, only a frequency modulation (FM) control method and an asymmetric duty cycle (ADC) control method can be utilized.

The full bridge circuit 11 and the half bridge circuit 12 may be in a complementary relationship with each other in terms of performance, configuration, and controllability. In a power conversion device of 3 kW or less, the half bridge circuit 12 is mainly used to be.

Research is underway to improve the performance of the power conversion apparatus according to the purpose by adding new components to the conventional full bridge circuit 11 or the half bridge circuit 12 or by modifying the wiring so that the wiring is changed.

Korean Patent Laid-Open Publication No. 2011-0138997 entitled " LLC Resonant Converter of 2-Stage Output Control Type " is an H / B LLC, which is a combination of a half bridge circuit that receives DC power and supplies an AC voltage, and an LLC serial resonance circuit. And a circuit portion.

It is an object of some embodiments of the present invention to provide a power conversion device capable of various control and thereby improving efficiency by adding a switch cell connected in series between a neutral point in a DC link stage and an interconnection point in a half bridge circuit.

It is another object of the present invention to provide a method of generating a plurality of types of PWM control signals and controlling each of the semiconductor switches in the power conversion apparatus by using any one of them.

It should be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to an aspect of the present invention, there is provided a power conversion apparatus including: a DC link stage including two capacitors connected in series; A half-bridge circuit including two leg switch cells connected in series and connected in parallel to the DC link stage; Two additional switch cells serially connected between an interconnect point of the capacitor and an interconnect point of the leg switch cell; And a resonant circuit connected between the interconnection points and the bottom ends of the leg switch cells.

According to another aspect of the present invention, there is provided a power conversion apparatus comprising: a DC link stage including two capacitors connected in series; A half-bridge circuit including two leg semiconductor switches connected in series and connected in parallel with the DC link stage; Two additional semiconductor switches serially connected between the interconnect point of the capacitor and the interconnect point of the leg semiconductor switch; A detecting unit detecting a voltage of a lower capacitor connected between an interconnection point of the capacitor and the ground; And an output terminal for outputting an equivalent voltage value at every period between the interconnection point of the leg semiconductor switch and the ground or outputting an equivalent current value at every period from the interconnection point toward the lower end connected to the interconnection point, And a switching control unit for generating one of the PWM control signals and applying the generated PWM control signal to the leg semiconductor switch and the additional semiconductor switch, wherein the switching control unit generates a PWM control signal of a predetermined type according to the detected voltage, At least one of a timing of turning on and off timing of the semiconductor switch and the additional semiconductor switch is controlled differently by the plurality of types of PWM control signals, and the leg semiconductor switch and the additional semiconductor switch And is connected to the anti-parallel diode.

In addition, a method of controlling a semiconductor switch in a power conversion device according to an embodiment of the present invention is a method for controlling a semiconductor switch in a half-briidge circuit, comprising the steps of: Generating a plurality of types of PWM control signals such that an equivalent current value is output from the interconnection point to the lower end connected to the interconnection point at every period; And for the two additional semiconductor switches connected in series between the mutual connection point of the leg semiconductor switch and two capacitors connected in series in the DC link stage connected in parallel with the half bridge circuit and the mutual connection point of the leg semiconductor switch, Wherein at least one of a timing at which the leg semiconductor switch and a timing at which the additional semiconductor switch is turned on and a timing at which the additional semiconductor switch is turned on are different from each other by the plurality of types of PWM control signals And the leg semiconductor switches and the additional semiconductor switches are respectively connected to anti-parallel diodes.

The power conversion apparatus and the semiconductor switch control method as the solving means of the present invention can be easily applied to a conventional power conversion apparatus using a half bridge circuit at 3 kW or less, The loss can be minimized.

Further, by utilizing the power conversion apparatus and the semiconductor switch control method, which are the object of the present invention, the frequency modulation (FM) control scheme, the asymmetric duty cycle (ADC) control scheme, (AVC) control method, a phase shift (PS) control method, and the like.

Further, the present invention can improve the performance and efficiency of the entire system and minimize the transient state of the output voltage and the voltage unbalance through the control of appropriately switching the type of the PWM control signal.

Fig. 1 (a) and Fig. 1 (b) are circuit diagrams showing a conventional resonant converter used in general,
2 is a circuit diagram showing a power conversion apparatus according to an embodiment of the present invention,
Figure 3 is an equivalent circuit of the circuit diagram shown in Figure 2,
4 is a graph showing an example of two types of PWM control signals for controlling each semiconductor switch,
5 is a graph showing control results of the first type of PWM control signal during one period,
Figure 6 is a view showing the operation of the circuit during the t ₀ ~ t ₁ time in 5,
Figure 7 is shown the operation of the circuit of Figure 5 during at t ₁ ~ t ₂ hours,
8 is a view showing the operation of the circuit while in Fig. 5 t ₂ ~ t ₃ hours,
Figure 9 is a view showing the operation of the circuit during t ₃ t ~ ₄ h at 5,
Figure 10 is shown the operation of the circuit for the Fig. ₄ ~ t t ₅ h at 5,
FIG. 11 is a graph for explaining a problem that may be caused by the additional switch cell,
FIG. 12 is a view schematically showing an example of the type conversion of the PWM control signal,
13 is a graph showing the result of the control as shown in Fig. 12,
14 is a view schematically showing another example of the type conversion of the PWM control signal,
FIG. 15 is a graph showing the result of the control as shown in FIG. 14,
16 is a view schematically showing another example of the type conversion of the PWM control signal,
17 is a graph showing the results of the control as shown in Fig. 16,
18 is a flowchart for explaining a semiconductor switch control method according to an embodiment of the present invention,
19 is a graph showing a comparison result of performance between a power inverter and a conventional inverter according to an embodiment of the present invention,
20 is a diagram illustrating an example of utilizing a power conversion apparatus according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when a part is referred to as "including " an element, it does not exclude other elements unless specifically stated otherwise.

FIG. 2 is a circuit diagram showing a power conversion apparatus according to an embodiment of the present invention, and FIG. 3 is an equivalent circuit of the circuit diagram shown in FIG.

The power conversion apparatuses 100 and 100 'include DC link stages 110 and 110', a half bridge circuit 120, additional switch cells 131 and 132, a resonant circuit 140, a lower stage 150, And a control unit (not shown).

The DC link stages 110 and 110 'include two capacitors C _dc1 and C _dc2 connected in series.

In FIG. 2, the mutual connection point of the capacitors is a node n between the first capacitor C _dc1 and the second capacitor C _dc2 as a neutral point in the DC link stages 110 and 110 ' (N ') between the first voltage (V _dc1 ) and the second voltage (V _dc2 ) can be appreciated by one of ordinary skill in the art.

The half bridge circuit 120 includes two leg switch cells 121 and 122 connected in series and is connected in parallel with the above described DC link stages 110 and 110 '.

The additional switch cells 131 and 132 are connected to the interconnection points (n, n ') of the capacitors in the DC link stages 110 and 110' and the interconnection points a " refers to two switch cells connected in series.

As described above, the power conversion apparatuses 100 and 100 'proposed in the present invention further include the additional switch cells 131 and 132 in addition to the leg switch cells 121 and 122 constituting the general half bridge circuit, Circuit.

The leg switch cells 121 and 122 and the additional switch cells 131 and 132 are connected to the semiconductor switches S ₁ , S ₂ , S ₃ and S ₄ capable of on / A parallel diode, and the switch cell may be fabricated in the form of a single element or module.

Also, the resonant circuit 140 may be connected between the interconnection point (a) and the lower ends 150 and 150 'of the leg switch cells in the half bridge circuit 120. At this time, the resonance circuit 140 may be an LC (Inductor-Capacitor) series resonance circuit as shown in FIG. 2 and FIG. 3, but is not particularly limited. For example, the resonant circuit 140 may be implemented as an LLC (Inductor-Inductor-Capacitor) serial resonant circuit.

As shown in FIG. 2, the load terminal 150 may include a transformer having n: 1 turns ratio, bridge diodes D _s1 , D _s1 , D _s3 , D _s4 , a capacitor C ₀ , and a load resistor R ₀ . But is not limited thereto. In addition, the resonance circuit 140 may not be included according to the application to which the power conversion apparatus 100 or 100 'proposed in the present invention is applied, and the load end 150 may be variously configured.

Further, the switching control unit (not shown) is connected to the leg semiconductor switches S ₁ and S _{2 in} the leg switch cells 121 and 122 and the additional semiconductor switches S ₃ and S _{4 in the} additional switch cells 131 and 132, Off control of turn-on and turn-off control of the PWM control signal.

Hereinafter, the PWM control signal generated by the switching control unit, the operation of each constitution corresponding thereto, and the operation result will be described in more detail.

The switching control unit described above may be configured such that an equivalent voltage value V _ab is output at every period between the interconnection point a of the leg switch cell and the ground b or the resonance circuit connected to the interconnection point a from the interconnection point a, One of two types of PWM control signals may be generated such that an equivalent current value i _in is output at every cycle in a direction toward the lower stage 150 or the lower stage 150 or 150 '.

At this time, the turn-on timing of any of the semiconductor switches S _{n (n = 1, 2, 3, 4) in the} leg switch cells 121 and 122 and the additional switch cells 131 and 132 and the turn- Timing can be controlled differently by the first type PWM control signal and the second type PWM control signal.

4 is a graph showing one example of two types of PWM control signals for controlling each semiconductor switch.

The first type PWM control signal may be generated by the switching control unit as shown in the left graph of FIG. 4, and the second type PWM control signal may be generated as shown in the right graph of FIG. However, conversely, the left graph may be a PWM control signal of the second type and the right graph may be a PWM control signal of the first type.

For example, the two types of PWM control signals applied to the S ₁ semiconductor switch include a first and second turn-on timing of the first type PWM control signal and a first and second turn of the second type PWM control signal - ON timing are the same, but it can be seen that the timing at which each turn-off is different from each other.

In addition, in the case of PWM control signals of two types applied to the S ₂ semiconductor switch, the S ₁ semiconductor switch is turned off at the timing when the S ₁ semiconductor switch is first turned on in the case of the PWM control signal of the first type. It can also be seen that the second turn-off timing of the first type of PWM control signal and the first turn-off timing of the second type of PWM control signal are different from each other.

As described above, at least one of the timing at which the semiconductor switch S _n is turned on and the timing at which the semiconductor switch S _n is turned off in the leg switch cells 121 and 122 and the additional switch cells 131 and 132 are two types of PWM control Although it is controlled differently by the signal, an equivalent voltage value (V _ab ) or current value (i _in ) may be output as shown in Fig.

2 and 3, the voltage value V _ab is the output voltage of the inverter, and the current value i _in is the current flowing in the direction of the resonance circuit 140 at the mutual connection point (a) Quot;

Meanwhile, FIG. 5 is a graph showing control results of the first type PWM control signal during one period. The drive control signals of the semiconductor switches S ₁ , S ₂ , S ₃ and S ₄ , the output voltage V _ab of the inverter, the resonant network current i _in and the respective semiconductor switches S ₁ and S ₂ , S ₃ , S ₄ ) are shown.

Hereinafter, when the smart control unit generates the first type PWM control signal as shown in FIG. 5 in the circuit shown in FIG. 2, the circuit operation in each time period will be described in detail.

6 is a view showing the operation of the circuit during the t ₀ ~ t ₁ hour at 5.

The energy stored in the resonant networks (L _r , C _r ) is circulated to the subordinate _stages through the DC link stages (V _dc1 , V _dc2 ), which are the input side, for t ₀ to t ₁ . t ₀ before and the current to the antiparallel diode of the S ₁ semiconductor switch to flow and turns on the S ₁ semiconductor switch to t ₀ - If on S ₁ semiconductor switch to minimize switching losses and the zero-voltage switching (ZVS) and efficiency Can be increased. Further, even if the S ₄ semiconductor switch is turned on, the current does not flow to the additional switch cells 131 and 132 because the S ₃ semiconductor switch is blocking voltage. For reference, the D _s3 diode and the D _s4 diode in the bottom stage shown in FIG. 6 are turned on, but it can be easily understood that the current flow may vary as the connection or configuration of the bottom stage is variously changed.

7 is a view showing the circuit operation during the t ₁ ~ t ₂ hours at 5.

The S ₁ semiconductor switch is turned on as a powering period for t ₁ to t ₂ , and energy is transferred from the input side DC link stages (V _dc1 , V _dc2 ) to the lower stage. In addition, although the D _s1 diode and the D _s2 diode in the bottom stage shown in FIG. 7 are conductive, it can be easily understood that the current flow may vary as the connection or configuration of the bottom stage is variously changed.

8 is a diagram showing the operation of the circuit while also eseo t ₂ t ₃ ~ 5 hours.

the S ₁ semiconductor switch is turned off and the S ₃ semiconductor switch is turned on for a period of t ₂ to t ₃ and the current starts to flow to the further switch cells 131 and 132. As the interconnection point (n, n ') and the interconnection point (a) of the leg switch cell become conductive, the voltage used to transfer power to the lower ends 150 and 150' decreases to 1/2. Also, the S ₃ semiconductor switch operates with synchronous rectification, and the S ₄ semiconductor switch performs ZVS.

9 is a view showing the operation of the circuit during t ₃ t ~ ₄ h at 5.

During the period t ₃ to t ₄ , the semiconductor switches S ₁ , S ₃ and S ₄ are all turned off and the energy stored in the resonant networks L _r and C _r circulates through the load stages 150 and 150 '. S ₂ S ₂ the semiconductor switch in the antiparallel diode of the semiconductor switch is turned conductive state, while the zero-voltage switching (ZVS) - is turned on, it is possible to minimize switching losses and increase the efficiency with it. 8 and 9 operate in the same manner as in FIG. 7, but it can be easily understood that the current flow may vary as the connection or configuration of the lower stage is variously changed.

10 is a view showing the circuit operation during the ₄ t t ₅ h at ~ 5.

the S ₂ semiconductor switch is turned on as a powering period for t ₄ to t ₅ hours and the energy stored in the resonance networks L _r and C _r is transferred to the load stages 150 and 150 '. In addition, the diodes in the lower stage shown in FIG. 10 operate in the same manner as in FIG. 6, but it can be easily understood that the current flow may vary as the connection or configuration of the lower stage is variously changed.

6 through 10, the semiconductor switches S ₁ , S ₂ , S ₃ , and S _{4 in the} leg switch cells 121 and 122 and the additional switch cells 131 and 132 are connected in series to the inverse parallel diodes, The resonance circuit 140 connected between the connection point (a) of the switch cell and the lower ends 150 and 150 'to charge / discharge energy, and the PWM control signal. That is, before the PWM control signal for turning on or off each semiconductor switch is applied to the gate, the voltage across the semiconductor switch can be made zero by the above-described circuit configuration, Soft switching is possible under the conditions.

The power conversion apparatus proposed in the present invention can be applied to a frequency modulation (FM) control system, an asymmetrical duty cycle (ADC) control system, an asymmetric voltage cancellation (AVC) control system, a phase shift PS) control method or the like.

In particular, the present invention can be easily applied to existing power conversion apparatuses using a half bridge circuit at 3 kW or less, and can minimize losses through zero voltage soft switching.

Further, in the case of a conventional power conversion apparatus using a half bridge circuit or a full bridge circuit, V _dc . However, in the case of the power conversion apparatus proposed in the present invention, a voltage switch of 1/2 * V _dc voltage stress is applied, so that durability and stability can also be advantageous.

In addition, even if there is a change in the load terminal or the input terminal, the fluctuation range of the switching frequency can be minimized, the efficiency increase effect can be expected when operating with a low load, and the positive (+) and negative Equal.

Meanwhile, FIG. 11 is a graph for explaining a problem that may occur due to the additional switch cell.

The operation of the additional switch cells 131 and 132 connected in series between the interconnection point n and n 'and the interconnection point a of the leg switch cell as shown in FIG. 11 causes the capacitor C _dc1 , and C _dc2 are unbalanced.

Specifically, when the first type PWM control signal shown in FIG. 4 is applied, the voltage V _dc1 of the first capacitor C _dc1 in the DC link stages 110 and 110 'gradually increases, The voltage V _dc2 of the capacitor C _dc2 gradually falls. In addition, when the second type PWM control signal shown in FIG. 4 is applied, the voltage V _dc1 of the first capacitor C _dc1 in the DC link stages 110 and 110 'gradually falls, The voltage V _dc2 of the capacitor C _dc2 gradually rises.

In order to solve the voltage unbalance problem and improve the efficiency of the power conversion and the performance of the entire system, the power conversion apparatus 100, 100 'according to another embodiment of the present invention includes a detection unit (Not shown).

The detection unit can detect the voltage of the lower capacitor (C _dc2 in case of FIG. 2) connected between the connection point (n, n ') of the capacitor in the DC link stages 110 and 110' and the ground b.

The switching control unit may generate a PWM control signal of a predetermined type together with the type switching of the PWM control signal according to a result of comparing the voltage detected by the detecting unit with a predetermined upper limit threshold value or a lower limit threshold value, The PWM control signal can be applied to the leg switch cells 121 and 122 and the additional switch cells 131 and 132. [

That is, the switching control unit outputs an equivalent voltage value at every cycle between the interconnection point (a) and the ground (b) of the leg semiconductor switch, or outputs the voltage value from the interconnection point (a) Any one of a plurality of types of PWM control signals is generated and output to the leg semiconductor switches S ₁ and S ₂ and the additional semiconductor switches S ₃ and S ₄ so that an equivalent current value is output every period .

At this time, the leg semiconductor switches S ₁ and S ₂ and the additional semiconductor switches S ₃ and S ₄ are connected to the anti-parallel diodes, respectively.

FIG. 12 is a view briefly showing an example of the type switching of the PWM control signal, and FIG. 13 is a graph showing the result of the control as shown in FIG.

When the voltage detected by the detecting unit exceeds the predetermined upper limit threshold value or is lower than the lower limit threshold value, the switching control unit stops generating the first type PWM control signal and outputs the second type PWM control signal, It can be generated after the set transient time.

In other words, according to an example, each switch cell in the power conversion apparatuses 100 and 100 'operating as an inverter is operated by the PWM control signal of the first type (or the second type) before the predetermined transient time , Each switch cell is turned off during a predetermined transient time, and each switch cell can be operated by a PWM control signal of a second type (or first type) which is a type converted after a predetermined transient time.

In addition, the power converters 100 and 100 'proposed by the present invention can be used for various applications other than inverters. When the DC-DC converter is operated, the transient state of the output voltage May occur. In order to improve this, a scheme other than a method of appropriately controlling the transient time will be further described below.

14 is a view briefly showing another example of the type conversion of the PWM control signal, and FIG. 15 is a graph showing the result of the control as shown in FIG. 14

When the voltage detected by the detecting unit exceeds a predetermined upper limit threshold value or is lower than the lower limit threshold value, the switching control unit stops generating the first type PWM control signal and generates the transient operation control signal for a predetermined transient time The second type PWM control signal can be generated.

At this time, the transient operation control signal is a control signal for operating the first semiconductor switch in the leg switch cells 121 and 122 and the second semiconductor switch in the additional switch cells 131 and 132 at a predetermined fixed duty ratio, And a control signal for turning off the third semiconductor switch in the leg switch cells 121 and 122 and for turning on the fourth semiconductor switch in the further switch cells 131 and 132.

Here, the fixed duty ratio may be preset to 50%, the first semiconductor switch when also reference 2 may be in the S _first semiconductor switch (or S _2, a semiconductor switch), the second semiconductor switch S _1, the semiconductor switches ( Or an S ₂ semiconductor switch). The third semiconductor switch may be an S ₃ semiconductor switch (or an S ₄ semiconductor switch), and the fourth semiconductor switch may be an S ₄ semiconductor switch (or an S ₃ semiconductor switch).

In other words, according to another example, each switch cell in the power conversion apparatuses 100 and 100 'operating as an inverter by the PWM control signal of the first type (or the second type) operates before the predetermined transient time , Each switch cell is operated by a transient operation control signal for a predetermined transient time, and each switch cell is operated by a second type (or first type) PWM control signal of a type converted after a predetermined transient time . Thus, during the transient time, some switch cells are turned off, but the remaining switch cells are not turned off and can be operated by a Semi half-bridge operation algorithm to reduce the transient state of the output voltage.

FIG. 16 is a view briefly showing another example of the type switching of the PWM control signal, and FIG. 17 is a graph showing the result of the control as shown in FIG.

When the voltage detected by the detecting unit exceeds a predetermined upper limit threshold value or is lower than the lower limit threshold value, the switching control unit stops generating the first type PWM control signal and immediately outputs the second type PWM control signal, Can be generated.

In other words, according to another example, each switch cell in the power converters 100 and 100 'operating as an inverter is operated by the PWM control signal of the first type (or second type), and the predetermined transient time Each of the switch cells can be operated by a second type (or first type) PWM control signal that is an immediately converted type without a transient operation control signal. This can minimize transient transients and voltage imbalances.

A method of controlling the semiconductor switches S ₁ , S ₂ , S ₃ and S ₄ in the power conversion apparatuses 100 and 100 'according to the embodiments of the present invention will be described with reference to FIG. 18 I will explain. 18 is a flowchart for explaining a semiconductor switch control method according to an embodiment of the present invention. For reference, the reference numerals of the components shown in Figs. 2 and 3 are used for convenience of explanation.

First, the power conversion apparatuses 100 and 100 'or the switching control unit generates a plurality of types of PWM control signals (S1100).

At this time, the PWM control signal of each type is equivalent to a voltage value equivalent to each period between the mutual connection point (a) of the two leg semiconductor switches S ₁ and S ₂ connected in series in the half bridge circuit 120 and the ground (b) Or to control the semiconductor switches so that an equivalent current value is output at every cycle in the direction from the interconnect point (a) toward the lower stage (150, 150 ') connected to the interconnect point (a).

Subsequently, the power conversion device 100 or 100 'or the switching control is generated in the step S1100 of generating the leg semiconductor switches S ₁ and S ₂ and the two additional semiconductor switches S ₃ and S ₄ (Step S1200).

At this time, the additional semiconductor switches S ₃ and S ₄ are connected to the interconnection points (n, n ') of two capacitors connected in series in the DC link stage 110 connected in parallel with the half bridge circuit 120, (a).

At least one of the timing of turn-on and turn-off of the leg semiconductor switches (S ₁ , S ₂ ) and the further semiconductor switches (S ₃ , S ₄ ) And the leg semiconductor switches S ₁ and S ₂ and the additional semiconductor switches S ₃ and S ₄ are connected to the anti-parallel diodes, respectively.

In addition, the power conversion apparatus 100, 100 'can detect the voltage (C _{dc2 in} the case of FIG. 2) of the lower capacitor connected between the connection point n and n' of the capacitor and the ground b, The voltage can be compared with a preset upper limit threshold value or a predetermined lower limit threshold value.

In this case, the above-described applying step S1200 determines any one of the PWM control signals generated according to the comparison result and outputs the generated PWM control signals to the leg semiconductor switches S ₁ and S ₂ and the additional semiconductor switches S ₃ and S ₄ .

Specifically, if the detected voltage exceeds the upper threshold value or is less than the lower threshold value, step S1200 of applying the PWM control signal of one of the plurality of types instead of the PWM control signal of the applied type immediately Or after a predetermined transient time. For example, if the first type of PWM control signal is being applied, a second type of PWM control signal, which is a type converted immediately or after a predetermined transient time, may be applied.

If the detected voltage exceeds the upper threshold value or is lower than the lower threshold value, the applying step (S1200) may, after applying the transient operation control signal for a predetermined transient time instead of the PWM control signal of the applied type, Of the PWM control signal of the PWM control signal. For example, if the first type PWM control signal is being applied, the second type PWM control signal, which is the converted type after application of the transient operation control signal, may be applied.

At this time, the transient operation control signal is a control signal for operating any one of the leg semiconductor switches S ₁ and S ₂ and the additional semiconductor switches S ₃ and S ₄ at a predetermined fixed duty ratio, And a control signal to turn off the remaining one of the leg semiconductor switches (S ₁ , S ₂ ) and turn on the other one of the additional semiconductor switches (S ₃ , S ₄ ).

19 is a graph showing a comparison result of performance between a power inverter according to an embodiment of the present invention and a conventional inverter.

In order to compare the performance, the power conversion device including the modified half bridge circuit proposed by the present invention is controlled by an asymmetrical voltage-elimination (AVC) control method, and the power conversion device (inverter) including the conventional half bridge circuit Frequency modulation (FM) control scheme and asymmetric duty cycle (ADC) control scheme.

Referring to the first graph of FIG. 19, the power conversion scheme according to the present invention increases by at least 77% from the conventional frequency modulation control scheme in terms of the inverter output power factor (PF) relative to the load variation. And 29%, respectively.

In the second graph of FIG. 19, the power conversion scheme according to the present invention is reduced by at least 35% from the conventional frequency modulation control scheme in terms of the inverter switching variation width (f _sw / f ₀ ) It can be seen that it shows a decrease by more than 20% more than the asymmetric duty cycle control method.

In the third graph of FIG. 19, the power conversion scheme according to the present invention is reduced by 18% or more from the conventional frequency modulation control scheme in terms of the load variation vs. resonance current magnitude (I _{in , peak} ) Cycle control method by 30% or more.

It can be seen that the power conversion scheme proposed by the present invention exhibits higher efficiency than the existing system in view of the performance comparison result considering a plurality of indicators.

20 is a diagram illustrating an example of utilizing a power conversion apparatus according to an embodiment of the present invention.

As shown in FIG. 20, the power conversion apparatuses 100 and 100 'proposed in the present invention can be utilized as a drive inverter of an induction heating system (for example, an induction heating apparatus, etc.) which has already been commercialized. In addition, it can be applied to various applications such as a drive inverter for a wireless power system, an SMPS for an electronic product, and a charger for an electric vehicle. Further, as described above, the performance and efficiency of the entire system can be improved through the control of appropriately switching the type of the PWM control signal.

Meanwhile, each of the components or all of the power conversion devices 100 and 100 'shown in FIG. 2 and FIG. 3 may be configured as a' module '. The term 'module' refers to a hardware component such as software or a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and the module performs certain roles. However, a module is not limited to software or hardware. A module may be configured to reside on an addressable storage medium and may be configured to execute one or more processors. The functionality provided by the components and modules may be combined into a smaller number of components and modules or further separated into additional components and modules.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: power converter 110: DC link stage
120: half bridge circuit 121, 122: leg switch cell
131, 132: additional switch cell 140: resonant circuit
150:

Claims (13)

A power conversion apparatus comprising:
A DC link stage including two capacitors connected in series;
A half-bridge circuit including two leg switch cells connected in series and connected in parallel to the DC link stage;
Two additional switch cells serially connected between an interconnect point of the capacitor and an interconnect point of the leg switch cell;
A switching control unit for generating a PWM control signal for controlling the turn-on or turn-off of the semiconductor switch included in the leg switch cell and the semiconductor switch included in the additional switch cell; And
And a resonance circuit connected between an interconnection point and an underside of the leg switch cell,
The switching control unit
Wherein an equivalent voltage value is output every period between the mutual connection points of the leg switch cells and the ground or an equivalent current value is outputted from the mutual connection point to the resonant circuit connected to the interconnection point or the lower end, Type PWM control signal,
Wherein at least one of a timing at which the leg switch cell and a certain semiconductor switch in the additional switch cell is turned on and a timing at which the semiconductor switch is turned off are controlled differently by the two types of PWM control signals.
The method according to claim 1,
Wherein said leg switch cell and said additional switch cell each comprise an anti-parallel diode connected to said semiconductor switch and said semiconductor switch, respectively.
3. The method of claim 2,
Wherein the leg switch cell and the semiconductor switch in the additional switch cell are soft switched by the PWM control signal and the resonant circuit connected between the anti-parallel diode, the interconnection point of the leg switch cell and the lower terminal.
delete A power conversion apparatus comprising:
A DC link stage including two capacitors connected in series;
A half-bridge circuit including two leg semiconductor switches connected in series and connected in parallel with the DC link stage;
Two additional semiconductor switches serially connected between the interconnect point of the capacitor and the interconnect point of the leg semiconductor switch;
A detecting unit detecting a voltage of a lower capacitor connected between an interconnection point of the capacitor and the ground; And
Wherein a plurality of types of PWMs are provided so that an equivalent voltage value is output every period between the mutual connection points of the leg semiconductor switches and the ground or an equivalent current value is outputted from the interconnection point to the lower end connected to the interconnection point, And a switching control unit for generating one of the control signals and applying the control signal to the leg semiconductor switch and the additional semiconductor switch,
Wherein the switching control unit generates a PWM control signal of a predetermined type according to the detected voltage,
At least one of a timing at which the leg semiconductor switch and the additional semiconductor switch is turned on and a timing at which the additional semiconductor switch is turned off are controlled differently by the plurality of types of PWM control signals,
Wherein the leg semiconductor switch and the additional semiconductor switch are respectively connected to anti-parallel diodes.
6. The method of claim 5,
When the detected voltage exceeds a predetermined upper threshold value or is lower than a lower threshold value, the switching control section stops generating the first type PWM control signal and immediately outputs the second type PWM control signal, which is the switched type, Or after a predetermined transient time.
6. The method of claim 5,
When the detected voltage exceeds a predetermined upper limit threshold value or is lower than a lower limit threshold value, the switching control unit stops generating the first type PWM control signal and generates the transient operation control signal for a predetermined transient time period The PWM control signal of the second type, which is the converted type,
Wherein the transient operation control signal is a control signal for operating either one of the leg semiconductor switches and the additional semiconductor switch at a predetermined fixed duty ratio,
And a control signal to turn off the remaining one of the leg semiconductor switches and to turn on the other one of the additional semiconductor switches.
8. The method of claim 7,
Wherein the fixed duty ratio is preset to 50%.
6. The method of claim 5,
And a resonance circuit connected between an interconnection point and an underside of the leg semiconductor switch.
A method of controlling a semiconductor switch in a power conversion device,
An equivalent voltage value is output every period between the interconnection points of the two leg semiconductor switches connected in series in the half-briidge circuit and the ground, or the voltage value is output every period from the interconnection point toward the lower end connected to the interconnection point Generating a plurality of types of PWM control signals so that an equivalent current value is output for each of the plurality of types of PWM control signals; And
For the two additional semiconductor switches connected in series between the mutual connection point of the leg semiconductor switch and two capacitors connected in series in the DC link stage connected in parallel with the half bridge circuit and the mutual connection point of the leg semiconductor switch, The method comprising the steps of:
At least one of a timing at which the leg semiconductor switch and the additional semiconductor switch is turned on and a timing at which the additional semiconductor switch is turned off are controlled differently by the plurality of types of PWM control signals,
Wherein the leg semiconductor switch and the additional semiconductor switch are respectively connected to anti-parallel diodes.
11. The method of claim 10,
Detecting a voltage of a lower capacitor connected between an interconnection point of the capacitor and ground; And
And comparing the detected voltage with a predetermined upper limit threshold value or a lower limit threshold value,
Wherein the applying step determines and applies any one of the generated PWM control signals according to a comparison result of the comparing step.
12. The method of claim 11,
If the detected voltage exceeds or is less than the upper threshold value, the applying step may immediately apply the PWM control signal of any of the plurality of types instead of the PWM control signal of the type of applied Or after a predetermined transient time.
12. The method of claim 11,
Wherein when the detected voltage exceeds or is below the upper threshold value, the applying step applies the transient operation control signal for a predetermined transient time instead of the PWM control signal of the type that was applied, Of the PWM control signal,
Wherein the transient operation control signal is a control signal for operating either one of the leg semiconductor switches and the additional semiconductor switch at a predetermined fixed duty ratio,
And a control signal to turn off the remaining one of the leg semiconductor switches and to turn on the other one of the additional semiconductor switches.

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