KR101457876B1 - A deterioration monitoring system for a distributing board on based hybrid temperature sensors with mater and slave device - Google Patents

Abstract

The present invention relates to a system for monitoring the deterioration of a distributing board based on a hybrid temperature sensor having a master HTS temperature sensor and a sub-HTS temperature sensor in which each touch type temperature sensor is installed in a plurality of installation points in which overheat is predicted in the distributing board and which comprises the master HTS temperature sensor and the sub-HTS temperature sensor in a common bus on one line to form a common bus type circuit. The present invention comprises a hybrid temperature sensor unit which comprises a plurality of HTS temperature sensors and obtains the temperature array data by sensing the temperature of the distributing board and a monitoring device which determines the problems of the distributing board by using the temperature array data. An HTS temperature sensor touches the distributing board and senses the temperature. The HTS temperature sensor is connected to the common bus and transmits temperature data through the common bus. One among the HTS temperature sensors (master HTS temperature sensor) controls different HTS temperature sensors (sub-HTS temperature sensor) excluding the master HTS temperature sensor through the common bus and transmits the temperature data measured in the sub-HTS temperature sensor to the monitoring device.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid temperature sensor based on a master and a sub,

A contact type temperature sensor is provided at a plurality of facility points where overheating is expected in the switchboard, and a master which implements the common bus type circuit by constituting the temperature sensor as a master and a sub on one common bus line And a sub-hybrid temperature sensor based on the hybrid system.

The present invention also relates to a hybrid temperature sensor comprising a master and a sub which are configured to automatically sense a point where heat is generated by contact resistance between an electric distribution board and a distribution board and to output an alarm and a shutoff signal using a hybrid temperature sensor composed of a master and a sub, Sensor-based switchgear deterioration monitoring system.

Generally, power equipment such as switchgear, breaker, transformer, transformer, and bus bar in the switchgear is required to detect the overheating by measuring the temperature in most cases. For example, the switch and the breaker include the lead-in and lead-out terminal blocks, respectively, and it is necessary to detect the temperature of the lead-in terminal and the lead-out terminal block to judge whether or not they are deteriorated by overheating. In addition, the contact resistance between busbars and busbars, busbars such as busbars and branch lines, and cables, etc., is increased due to loosening of connecting parts and foreign materials, and the like, have.

In particular, all electricity supply is made through a converter. At some point of the converter, when the contact resistance is increased by the loosening of the screw or the like, heat is generated, which causes the surrounding wire coating to melt, resulting in a short circuit due to insulation breakdown. Short-circuiting leads to fire. Because of this danger, the electrical manager must monitor the screw loosening of the electrical supply system from time to time, but it is not only difficult to monitor from time to time, but even more difficult to find. There is also a point where inspection is possible only when it is in a disconnected state.

Techniques for detecting and reporting overheating as described above are presented. As an example, by attaching a temperature tube to a bus-bar connection terminal of a switchboard and acquiring a change in the color of the temperature tube by the heat of the terminal portion through the camera, A heat sensing and remote control device of an ASSEMBLY has been proposed in which an external image of an ASSEMBLY is acquired and a door of the ASSEMBLY can be automatically controlled remotely.

Also, in order to supply low-voltage, large-current to facilities in each factory, a bus bar is typically connected to each equipment and a switchboard or supplies a reduced-pressure AC voltage to the equipment at a switchboard, and is connected to the booth bar, And a plug-in box control device arranged to be spaced apart from the bus bar so as to receive and analyze information detected from the detection sensor through each input terminal, Patent Document 2].

However, in spite of the fact that the temperature needs to be detected using the temperature sensor in such a large number of tens groups, there is a problem of excessive wiring of the contact type temperature sensor, delays and errors in temperature detection and calculation processing, The bias of the DC bias power supply for each sensor is limited and the mounting of the sensor is extremely limited.

[Patent Document 1] Korean Patent No. 10-1190244 (issued October 12, 2012) [Patent Document 2] Korean Published Patent Application No. 10-2012-0077742 (published on July 10, 2012)

The object of the present invention is to provide a contact type temperature sensor at a plurality of facility points where overheating is expected in a switchboard and to provide the temperature sensor to a master and a sub- And a hybrid temperature sensor based master and sub that implements a common bus type circuit.

In order to accomplish the above object, the present invention is directed to a hybrid temperature sensor based hybrid temperature sensor system composed of a master and a sub, comprising a plurality of HTS temperature sensors and detecting a temperature inside a switchboard to obtain temperature array data, A temperature sensor unit; And a monitoring device for determining the presence or absence of an abnormality of the power plant by using the temperature array data, wherein the HTS temperature sensor is contacted with the power plant to sense the temperature, the HTS temperature sensor is connected to a common bus, One of the HTS temperature sensors (hereinafter referred to as a master HTS temperature sensor) transmits temperature data through a common bus and controls a plurality of HTS temperature sensors (hereinafter referred to as sub HTS temperature sensors) other than the master HTS temperature sensor And collects the temperature data measured by the sub HTS temperature sensor and transmits the data to the monitoring device.

The present invention is also directed to a hybrid temperature sensor based master and slave sub-system deterioration monitoring system, which supplies power to the HTS temperature sensor via the common bus.

The present invention also provides a hybrid temperature sensor based hybrid temperature sensor monitoring system comprising a master and a sub, wherein the master HTS temperature sensor comprises a sub HTS sensor connected on a common bus using a unique 32-bit code of each sub HTS sensor HTS temperature sensors are addressed on a common bus of one line, with each sub HTS temperature sensor having its own code.

The HTS temperature sensor is connected to the common bus via a 3-state port, and is connected to the common bus via a pull- up) connected through resistors. And maintains a high level when there is no signal transmission.

The present invention also provides a hybrid temperature sensor based hybrid temperature sensor monitoring system comprising a master and a sub, wherein the HTS temperature sensor is connected to an internal capacitor on the common bus, The internal capacity is charged when a signal is inputted and the power is supplied by a charged internal capacity when a bus signal of a low level is inputted from the common bus.

According to another aspect of the present invention, there is provided a hybrid temperature sensor based on a hybrid temperature sensor, wherein the master HTS temperature sensor includes a metal oxide semiconductor field effect transistor (MOSFET) transistor connected in parallel with a pull- .

The HTS temperature sensor may be configured to output a DC voltage using a negative temperature coefficient thermistor and a resistor. Alternatively, the HTS temperature sensor may be configured to output a DC voltage using a negative temperature coefficient thermistor And a measuring circuit for converting a DC voltage or current caused by the offset voltage into a temperature.

The present invention relates to a hybrid temperature sensor-based hybrid temperature sensor monitoring system comprising a master and a sub, wherein the HTS temperature sensor comprises a 2-byte temperature register for storing temperature data and an overtemperature alarm register for overheating alarm in an EEPROM memory, Byte alarm trigger register structure, the HTS temperature sensor performing a temperature conversion on the sensed value, storing a predefined two complement alarm trigger value stored in the first and second alarm trigger registers, And if the temperature value is greater than or equal to the value stored in the first alarm trigger register or if the temperature value is less than or equal to the value stored in the second alarm trigger register, And the master HTS temperature sensor executes an alarm search command to determine whether all And an alarm flag state of the sub HTS temperature sensor is confirmed.

As described above, according to the hybrid temperature sensor based on the hybrid temperature sensor constructed by the master and the sub, according to the present invention, the temperature sensors installed in the switchboard are communicated by a single common bus type circuit, , And temperature measurement errors can be solved.

FIG. 1 is a block diagram of a configuration of a hybrid temperature sensor based monitoring system configured by a master and a sub, according to an embodiment of the present invention. FIG.
2 is a block diagram of a configuration of a thermopile hybrid temperature sensor unit according to the present invention.
3 is a configuration diagram of a hybrid temperature sensor according to an embodiment of the present invention.
4 is an equivalent circuit of a temperature sensor array of a hybrid temperature sensor according to an embodiment of the present invention.
5 is a circuit diagram showing a bias power supply of a temperature sensor according to an embodiment of the present invention;
6 is a structural diagram of an alarm trigger register according to an embodiment of the present invention;
7 is a block diagram of a 32-bit ROM code according to an embodiment of the present invention;
8 is a bit structure diagram of a configuration register according to an embodiment of the present invention.
9 is a bit structure diagram of a CRC register according to an embodiment of the present invention;
10 is a flow diagram illustrating a method for accessing an HTS sensor by a common bus in accordance with an embodiment of the present invention.
11 is a flow diagram of a ROM instruction in accordance with an embodiment of the present invention.
12 is a circuit diagram showing a bidirectional input / output interface for pull-up according to an embodiment of the present invention;
13 is a circuit diagram showing a unidirectional input / output interface for pull-up according to an embodiment of the present invention;
14 is a block diagram of a hardware configuration of a controller according to the present invention;
15 is a circuit block diagram of the CPU block of the controller according to the present invention.
16 is a configuration diagram of a switch input circuit according to the present invention;
17 is a table showing input values of input ports of a switch input circuit according to the present invention;
18 is a configuration diagram of an Ethernet block according to the present invention.
19 is a circuit block diagram of an Ethernet block according to the present invention;
20 is a circuit block diagram of an LCD control block according to the present invention.
21 is a schematic circuit diagram of an LCD control part used in a controller according to the present invention;
22 is a configuration circuit diagram of a light control portion according to the present invention;
23 is an LCM_LEDA output waveform diagram in a stable state according to the present invention.
24 and 25 are circuit configuration diagrams of a NAND flash memory block which is a memory configuration according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

In the description of the present invention, the same parts are denoted by the same reference numerals, and repetitive description thereof will be omitted.

First, the configuration of a hybrid temperature sensor based on a master and a sub, according to an embodiment of the present invention, will be described with reference to FIG.

As shown in FIG. 1, the hybrid temperature sensor based hybrid system according to an embodiment of the present invention includes a hybrid temperature sensor unit 20, a monitoring device 30, And a remote server 40. In addition, it may further comprise a display device 50 for displaying the monitoring status of the monitoring device 30.

The hybrid temperature sensor unit 20 is composed of a plurality of sub HTS sensors 21. [ The sub HTS sensor 21 is installed at an installation point where overheating is expected in the interior of the switchboard 10 and measures the heat of the facility 11 provided in the switchboard 10.

The equipment or the equipment 11 provided inside the switchboard 10 can be used for various applications such as a bus bar, a vacuum breaker VCB, a power transformer PT for a meter, a MOF, a load break switch (LBS) , Various mold-type insulation devices, device connection parts, and components requiring insulation deterioration prediction. For example, it is a matter of course that the present invention can be applied to a monitoring device for a facility such as a molded case circuit breaker (MCCB) and various distribution lines, which are low-voltage side constituent devices inside a switchgear.

Meanwhile, the hybrid temperature sensor unit 20 and the monitoring device 30, the monitoring device 30, and the remote server 40 are connected by a network to perform data communication. Preferably, the hybrid temperature sensor unit 20 and the monitoring device 30 are connected to the Internet by the UDP protocol, and the monitoring device 30 and the remote server 40 are connected to the Internet by the TCP protocol.

The hybrid temperature sensor unit 20 is constituted by a sensor module for sensing the temperature of the component equipment 11 in a power plant including high voltage devices such as a bus bar, a breaker, MOF, CT, PT and a transformer as described above.

Preferably, the HTS sensors 21 and 23 constituting the hybrid temperature sensor unit 20 are configured to output a DC voltage using a negative temperature coefficient thermistor (NTC thermistor) and a resistor. Or the HTS sensors 21 and 23 are constituted by a measuring circuit for converting the DC voltage or current caused by the offset voltage of the transistor into a temperature.

On the other hand, the HTS sensors 21 and 23 are connected to the common bus 22 to transmit the temperature data through the common bus 22 and receive power through the common bus 22. [ The hybrid temperature sensor unit 20 includes a master HTS sensor 23 that controls each sub HTS sensor 21 via a common bus 22. [ The master HTS sensor 23 collects the temperature data measured by each sub HTS sensor 21 via the common bus 22 and transmits it to the monitoring device 30. The master HTS sensor 23 may act as a master either of the HTS sensors, or may separately configure a specific controller that controls the HTS sensors.

Next, the monitoring apparatus 30 receives the temperature array composed of the series of temperatures measured from the hybrid temperature sensor unit 20, and analyzes the temperature data of the received temperature array to determine whether or not the abnormality is present.

The monitoring device 30 can display the temperature data of the temperature array for each facility or generate and display thermal image data. That is, the monitoring apparatus 30 stores an image of a layout configuration or a layout configuration with respect to an area inside the switchboard 10 and displays the temperature at each facility or each facility location using the stored configuration diagram, The temperature array can be displayed as an infrared image.

Then, the monitoring device 30 compares the measured temperature of the corresponding area with the reference temperature or obtains the temperature rising value for each facility to determine whether or not the abnormality is present for each of the components. In addition, the monitoring device 30 displays temperature data or thermal image for each facility on the display, or notifies the manager of the detection of the abnormality when the abnormality is detected.

Preferably, the monitoring device 30 may be attached to the switchboard 10. For example, the hybrid temperature sensor unit 20 can be installed inside the switchboard 10, and the monitoring device 30 can be installed outside the switchboard 10. At this time, the temperature data is acquired from the HTS sensor 21 installed therein, and the monitoring apparatus 30 can analyze the temperature data to determine whether or not there is an abnormality in the switchboard 10.

The remote server 40 is a device having a computing processing function such as a personal computer (PC) or a server device. The remote server 40 is connected to the monitoring device 30 via a network, and receives temperature array data or judged data from the monitoring device 30 .

The remote server 40 can share the role with the monitoring device 30 and can process it. For example, the monitoring device 30 monitors the abnormality by performing a simple comparison by obtaining facility-specific or point-specific temperature data in real time, and the remote server 40 obtains a thermal image from the temperature array, And performs functions such as setting or managing the functions of the display device. In particular, the remote server 40 has excellent performance such as data storage capacity and computing ability, and the monitoring apparatus 30 may be inferior in performance to the remote server 40 as equipment installed in the field. In consideration of such a difference in performance, the functions between the remote server 40 and the monitoring apparatus 30 can be shared. Hereinafter, it will be described that the monitoring device 30 performs all the above functions.

Also, the display device 50 is connected to the monitoring device 30 to display the monitoring status. The display device 50 is connected to the monitoring device 30 via RS-485 (MODBUS).

Next, the configuration of the hybrid temperature sensor unit 20 according to an embodiment of the present invention will be described with reference to FIG.

2, the hybrid temperature sensor unit 20 according to an embodiment of the present invention includes a plurality of sub HTS sensors 21, a common bus 22, and a master HTS sensor 23. As shown in FIG.

The HTS sensor 21 has a temperature sensor element, such as a negative temperature coefficient thermistor (NTC thermistor), to measure the temperature in the facility. Particularly, the HTS sensor 21 is installed at an installation point where overheating is expected in the interior of the switchboard 10, and measures the heat of the facility 11 provided inside the switchboard 10.

Next, the common bus 22 is used as a bus system, a control line, or a communication line, and is also used as a power supply power line. The common bus 22 is configured as a bus system under the control of the master HTS sensor 23 so that each sub HTS sensor 21 is controlled or temperature data is transferred. Alternatively, the common bus 22 constitutes one bus system, and has a bus master, and transmission can be controlled by the bus master. The master HTS sensor 23 can serve as the bus master.

In the bus system, the microprocessor or master HTS sensor 23 identifies the sub HTS sensor 21 connected on the common bus 22 using the unique 32-bit code of each sub HTS sensor 21 and identifies the ID do. Each sub HTS sensor 21 has its own code so that it can address several sub HTS sensors 21 on the common bus 22 of one line.

That is, the master HTS sensor 23 controls the communication of the common bus 22, also controls each sub HTS sensor 21, and collects the temperature data from the sub HTS sensor 21. Thus, the master HTS sensor 23 acts as a master hybrid temperature sensor (HTS) device, and the sub HTS sensor 21 acts as a slave HTS device or slave device. Hereinafter, the master HTS sensor 23 is also referred to as a master HTS device, a master device, a master device, and the sub HTS sensor 21 is also referred to as a subordinate HTS device, a sub HTS device, or a slave device .

Next, the configuration of the HTS sensors 21 and 23 will be described in more detail with reference to FIG.

As shown in FIG. 3, in the control line, all devices such as the HTS sensors 21 and 23 are connected to the bus 22 via the 3-state port. Therefore, pull-up resistance is required. That is, the power source is connected to the resistor and normally maintains a high level state. It can be switched to a low level state by a signal or the like transmitted on the bus. However, when a signal or the like is not transmitted on the bus, it maintains a high level state.

As an important feature of a hybrid temperature sensor (HTS), dependent HTS devices other than the master HTS device are configured to operate the sensor module without the need for an external DC bias power supply.

When the common bus is in the High state, the dependent HTS device is powered through the Cout pin. In particular, the power of the dependent HTS is supplied through the pull-up resistor. A high-level high bus signal is configured to charge an internal capacitor (Cin) that supplies power to a dependent HTS (sub-HTS) device for when the bus level is low.

It is also possible to detect the temperature by storing the unique serial number of the dependent HTS device 21 using the memory map of the 32-bit ROM so that the number of sub-HTS sensors can be mounted on the distribution board and the distribution board without being restricted by the number .

In the EEPROM memory, which is a temporary storage location, the master HTS sensor 23 is connected to a 2-byte temperature register for storing the digital temperature output from the HTS sub HTS sensor 21 and a 1-byte alarm trigger register structure for over- . Since the register is nonvolatile (EEPROM), it has a function of storing its own data when the sensor device power is turned off.

Next, the temperature sensor element included in the HTS sensors 21 and 23 receives temperature data as a temperature array Qn in the HTS sensor.

The temperature sensor element is configured to output a DC voltage using a negative temperature coefficient thermistor (NTC) and a resistor. Alternatively, the temperature sensor element is constituted by a measuring circuit which converts a DC voltage or current caused by an offset voltage of the transistor into a temperature.

The temperature sensor array Qn according to the transistor offset voltage implements the temperature sensor using the temperature dependent characteristic of the offset voltage Vbe between the base of the silicon transistor and the emitter as shown in FIG.

In transistors Q ₃ and Q ₄ , I _T is divided into currents I _C1 and I _C2 of equal magnitude. Transistor Q ₂ is the current density of J ₁ Q ₁ as a connection the two transistors Q ₁ and equal in parallel is doubled, the current density J ₂ Q _2. Therefore, the voltage V _T developed across resistor R is:

[Equation 1]

Where K is Boltzmann's constant, q is the charge of the electron and T is the absolute temperature.

In the above equation, the voltage V _T at both ends of R is proportional to the absolute temperature T, and the current I _C2 flowing in R is also proportional to the absolute temperature.

As described above, the hybrid temperature sensor HTS constitutes a circuit so that a current proportional to the absolute temperature is outputted, and performs temperature detection by setting the sensitivity of the hybrid temperature sensor to 1 μA / K. For example, at 25 ° C. (298.2K) So that a current of 298.2 μA is output.

This analog signal is converted into a digital value through A / D conversion and processed by a microprocessor to realize a temperature sensor that detects temperature at multiple points.

Meanwhile, the power circuit of the hybrid temperature sensor is configured to operate the sub HTS device without supplying the local external power. This is particularly useful for temperature measurement applications where a large number of points of temperature require remote temperature sensing or are highly constrained.

Figure 5 shows that when the bus is in a High state, it gets power from the common bus through the Cout pin. That is, power is supplied through the common bus. The control circuit for this is shown. Charges are charged in the capacitor Cin in the sub HTS device while the bus is in a high level. And the charged charge provides power when the bus is in a low state.

The common bus and capacitor (Cin) can provide enough power for the sub HTS device for most tasks while the specified timing and voltage requirements are met.

However, if the HTS device performs temperature conversion or data copy from the EEPROM's temporary memory, the operating current can be as high as 2.0 mA. This current can cause an unacceptable voltage drop in the weak common pullup resistor, and more current can be supplied by the capacitor Cin. Therefore, to ensure that the HTS has sufficient supply current, it is necessary to provide a strong pullup function on the common bus whenever temperature conversion occurs or whenever data is copied from the temporary memory to the EEPROM.

As shown in FIG. 5, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used to directly hold the common bus on the rail. This solves the problem with the power supply in advance. In other words, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor connected to the common bus in parallel with the pull-up resistor is provided on the master HTS temperature sensor side.

In addition, the HTS device itself has a digital temperature sensor architecture. The resolution of the temperature sensor shall be 9, 10 bits, which corresponds to the user-configurable increments of 0.5 ° C and 0.25 ° C, respectively. The default resolution for power-up is 10 bits.

In the low power idle state, the HTS power-up executes the Convert command to start the temperature measurement and A / D conversion. After conversion, the resulting temperature data result is stored in the 2-byte temperature register of the temporary memory, and the HTS device returns to the idle state. The HTS output data is calibrated in Celsius and the temperature data is stored in the temperature register as a complement of 2 in 16-bit sign extension.

The sign bit S indicates a positive or negative temperature; Positive numbers are S = 0 Negative numbers are S = 1. If the HTS is configured with 10 bit resolution, all bits in the temperature register contain valid data.

3, the HTS sensor 23 may be provided with an alarm trigger register so as to perform an alarm (ALARM) signal operation.

As shown in FIG. 6, after the HTS device performs the temperature conversion, the temperature value is compared with the user defined 2's complement alarm trigger value stored in the 1 byte T _H and T _L registers. The sign bit (S) indicates when the value is positive or negative: S = 0 for positive numbers and S = 1 for negative numbers.

Because the T _H and T _L registers are non-volatile (EEPROM), they retain data even when the device is powered off.

If the result of the temperature measurement is greater than or equal to the set threshold T _H , or equal to or less than the set threshold T _L , then an alarm condition exists and an alarm flag is set within the HTS device. The alarm flag is updated after all temperature measurements and, therefore, if the alarm condition is extinguished, the alarm flag is turned off after the next turn of temperature conversions.

The master HTS device can issue an Alarm Search command to check the alarm flags of all sensor elements on the common bus. As an alarm setting flag, all sensor elements respond to commands. So that the master HTS device can accurately determine that another dependent HTS device has experienced an alarm condition. If an alarm condition exists and the T _H or T _L setting is changed, another temperature conversion should be performed to verify the alarm condition.

As shown in FIG. 7, each HTS sensor includes a unique 32-bit code stored in a ROM (ROM). The least significant 8 bits of the ROM code contain the common code of the HTS and the next 16 bits contain the unique sensor serial number. And the remaining most significant 8 bits include a cyclical redundancy check (CRC) byte. The ROM function control logic associated with the 32-bit ROM code allows the HTS to operate as a common device using the protocol.

As shown in Figure 8, byte 4 of the temporary memory contains a configuration register. The user can set the conversion resolution of the HTS sensor using the R0 and R1 bits in the configuration register. The power-up default of these bits is R0 = 1 and R1 = 1.

The error detection code (CRC) byte is provided as part of the 32-bit ROM code of the HTS and is in the ninth byte of the temporary memory. The ROM code CRC is calculated in the first 24 bits of the ROM code and is contained in the most significant byte of the ROM.

The temporary memory error detection code (CRC) is calculated from the data stored in the temporary memory. Therefore, this is changed when the data in the temporary memory is changed when it is changed.

The error detection code (CRC) provides a bus master (or master HTS sensor) as a data validation method when data is read from the HTS sensor. To ensure that the data is read correctly, the bus master (or master HTS sensor) must recalculate the CRC from the received data. This value should then be compared to the other ROM code. If the calculated CRC matches the read CRC, the data is received without error.

The comparison of the CRC values and the decision to continue operation are determined entirely by the bus master. The polynomial function is as follows.

&Quot; (2) "

The bus master (or master HTS sensor) can recalculate the CRC.

It is possible to compare the CRC value from the HTS sensor using a polynomial generator as shown in FIG.

The circuit of FIG. 9 consists of a shift register and XOR gates, and the shift register bits are initialized to zero. Starting with the least significant bit of the ROM code or the least significant bit of byte 0 in the temporary memory, one bit shifts to the shift register at a time.

After shifting from ROM to the 24th bit or from the temporary memory to the most significant bit of byte 7, the polynomial generator will contain the recalculated CRC.

Next, the 8-bit ROM code or temporary memory CRC from the HTS sensor must be shifted into the circuit. At this point, if the recalculated CRC is correct, the shift register will contain all zeros.

Next, the common bus system 22 will be described in more detail.

The common bus system uses one bus master (or master HTS sensor) to control one or more sub HTS devices. If there are multiple sub-HTS devices on the common bus, the system is multi-drop and all data and instructions transmit the least significant bits over the common bus.

The common bus has only one data line, and each device (master or sub HTS) is interfaced to the data line via the 3-state port. When the sensor device is not transmitting data, each device allows the data line to be released. The common port is an open drain with internal circuitry.

The common bus requires an external pullup resistor of about 6 kΩ. Thus, the idle state of the common bus is high. If for some reason it is necessary to temporarily suspend transmission / reception, the bus must remain idle if it wishes to resume transmission / reception.

If the common bus is inactive (high level) for too long during the recovery period, an infinite recovery time can occur between the bits. If the bus is held low for more than a few hundreds of microseconds, all components of the bus can be reset. It is also necessary to provide a strong pullup to the common bus whenever temperature conversion or EEPROM writing occurs to ensure that there is sufficient supply current during temperature conversion.

Next, a method for accessing the HTS sensor by the common bus will be described.

As shown in FIG. 10, a method for accessing the HTS sensor by a common bus includes (a) initializing step (S10); (b) a ROM command execution step (S20); And (c) HTS function command execution step S30.

It is very important to perform this sequence every time the HTS sensor is accessed, because some steps in the sequence do not respond in the event of an error or failure. The exception to this rule is the ROM command and the Alarm Search command. After executing one of these ROM commands, the master returns to the initial initialization step (S10) again.

First, the initialization step S10 will be described.

All signal processing on the common bus begins with an initialization sequence. The initialization sequence consists of a response pulse sent by the sub HTS after the reset pulse sent by the bus master. The response pulse causes the bus master to know that the sub HTS device is on the bus and ready to operate.

Next, the ROM command execution step S20 will be described.

After the master detects the response pulse on the common bus, it can execute the command of the ROM. The ROM command operates on the native 32-bit ROM code of each sub HTS device and allows the master to specify a specific device if there are a lot of sub HTS devices on the common bus. These commands allow the master to determine how much and what kind of bus exists on the bus or whether the device has experienced a notification state. Each instruction is 8 bits.

The master device causes the appropriate ROM command to be executed before executing the HTS function command. A flowchart showing a method for operating the ROM command is shown in Fig.

Next, the HTS function command execution step (S30) will be described. The HTS function command includes a search command, a read command, a skip command, an alarm search command, and the like.

First, a search command will be described.

The seek command allows the master to identify the ROM code of all sub-HTS devices on the bus and to allow the master to determine the number of sub-HTSs and its device type when powering up at system startup. The master learns the ROM code through a search ROM cycle as many times as the master needs to identify all sub HTS devices.

After all the search ROM cycles, the bus master or master HTS sensor 23 must return to the initialization step S10 in the transmit / receive sequence.

Next, the read command will be described.

The read command is used when one sub HTS is assigned to the common bus. The bus master reads the 32-bit ROM code of the sub HTS without going through the ROM search procedure.

Subsequently, the match instruction following the 32-bit ROM code sequence allows the bus master to address a particular sub HTS device to the multi-drop bus. Only sub-HTSs that exactly match the 32-bit ROM code sequence respond to functional commands issued by the master. All other sub HTSs on the common bus wait for a reset pulse.

Next, the skip command is described.

The skip command can be used by the master to simultaneously address all devices on the common bus without transmitting any ROM code information. For example, by executing the convert command after the skip command, the master enables all HTSs on the common bus to perform temperature conversions at the same time. This sequence can save time by the master reading directly from the device without transferring the 32-bit ROM code. If there is more than one sub HTS sensor, this sequence will cause data collision on the bus because several devices attempt to transmit data at the same time.

Next, the alarm search command will be described.

The alarm search command is the same as the search command except for the sub HTS sensor to which the alarm flag setting will respond. This command allows the master device to determine if any HTS experiences an alarm condition during the most recent temperature conversions. During all alarm search cycles, the bus master must return to the (initialization) step (S10) in the transmit / receive sequence.

Next, a common bus master configuration method will be described.

The common bus implemented in the present invention is a simple signaling system that performs half duplex communication between the master controller and one or more sub HTSs sharing a common data line. Both the power supply and the data communication take place over a single line, providing the core functionality for systems that need to minimize interconnects.

Common bus technology requires a common bus master to separate devices on the bus and generate waveforms for transmitting and receiving signals. The method of configuring the master is composed of two kinds according to the selection of the unidirectional and bidirectional input / output elements.

The common bus master is compatible with host circuits, which are microcontrollers that operate from 3V to 5V. Circuits that do not involve protocol translation can be used with hosts that operate with power supplies below 3V. In this case, a voltage level converter is needed between the master and the common bus sub HTS.

Figure 12 shows the most basic circuit of the master.

The circuit of Figure 12 requires some storage space in the bidirectional port and program memory and the advantage of the common bus of this circuit is that it can be simply implemented so that the voltage levels are compatible between the master and sub HTS using only a pullup resistor .

This requires additional port pins to implement strong pullups, depending on the sub HTS and pull-up voltage. The maximum operating voltage on the common bus is determined by the characteristics of the bidirectional port, and if the common bus has more than one sub HTS, the value of the pullup resistor R needs to be reduced to 2K ?. Considering the communication speed, the circuit is implemented by applying a microcontroller with a low clock frequency and a low clock cycle to the instruction cycle.

Figure 13 is another basic circuit similar to Figure 12, which requires two extra unidirectional ports and pull-down transistors, and some storage space in the program memory. The advantage of the circuit of FIG. 13 is the circuit used when the bidirectional port is not used. However, timing is created through software, which can increase the initial software development time and cost. Depending on the sub HTS and pull-up voltage, an additional port pin is needed to implement a strong pull-up. The maximum operating voltage on the common bus is determined by the characteristics of the bidirectional port and the value of one or more sub HTS and R on the common bus needs to be reduced to 2K ?.

Next, the hardware configuration of the controller implemented by the monitoring apparatus 30 according to the embodiment of the present invention will be described with reference to FIG. 14 to FIG.

As described above, the power / room deterioration monitoring system receives the temperature data from the hybrid temperature sensor unit 20 and displays the image data on the TFT LCD window as an image screen. The system monitors the surface temperature value of the object to be measured through the Ethernet communication line, Sensor module.

In addition, the surface temperature data is received, and the temperature data is displayed on a 4.3-inch TFT LCD. At this time, temperature change by temperature data is monitored and compared with the alarm set value, and an event is recorded while the alarm is raised according to the determination result. As shown in FIG. 1, for example, a sensor module (sensor unit) capable of connecting up to four sensors, a monitoring device or a controller, and a remote monitoring PC server may be used.

As shown in FIG. 14, an example of a hardware feature of the controller implemented by the monitoring device 30 can be implemented as follows.

As the processor, a 32-bit EISC architecture microphone processor (Architecture Microcontroller) is adopted. The microprocessor has a 5-stage pipelining, 108 MIPS (at 108 MHz System Clock) instruction processing speed, and 16 MBytes SRAM memory. It also has an LCD controller, RGB 888 or 565 output, and 800 x 600 resolution in RGB mode. In addition, the LCD employs a 4.3-inch TFT color LCD, with a resolution of 480 x 272, RGB-stripe color, digital interface, Ethernet communication UDP protocol and RS-485 MODBUS communication.

The circuit configuration of the CPU block of the controller is shown in Fig. The CPU is adStar (D16MF512), the clock (CLOCK) is 10MHz X-TAL, and the power source (VCC) is 3.3V. The switch input uses the 74HC148 to minimize the number of input ports. The internal memory consists of 16 MBytes of SRAM and 512 KBytes of FLASH.

The configuration of the switch input circuit is shown in FIG. Eight CPU input ports are required to configure the switch input circuit. It is desirable to use an external 74HC148 IC to solve with four ports.

The switch input port is configured by assigning the port (PORT) P0.0 to P0.3 of the CPU. When the logic input value of P0.3 changes from 'High' state to 'Low' state, the logic input value from CPU Port P0.0 to P0.2 is substituted into the table of FIG. 17 to know which switch is pressed .

As shown in the table of FIG. 17, when the switch is depressed, the logic of the switch input is changed from 'High' to 'Low'. Logic 'High' specifies H and 'Low' specifies L. An 'X' indicates that the input logic is high or low.

The configuration of the Ethernet block is shown in Fig. It is an Ethernet configuration diagram using a general ENC28J60 Ethernet chip. Particularly, the circuit configuration of the Ethernet block is shown in Fig.

As shown in FIG. 19, an Ethernet chip (ENC28J60) is used to transmit and receive data to and from the 2D array sensor module. Also, the Ethernet chip is designed to control through the SPI communication interface of the CPU.

The SPI communication interface pins are:

- ETH_INT0: Interrupts the CPU when data is received.

- ETH_SI: Port for writing data or command from CPU to Ethernet chip

- ETH_SO: The port used by the CPU to read the status of the data or Ethernet chip from the Ethernet chip.

- ETH_SCK: The output port of the clock required to synchronize with each bit when sending and receiving data to and from the Ethernet chip.

- ETH_CS: This is an output port that selects a chip during data transmission / reception with an Ethernet chip. When the low signal is output, it means that it is selected.

It is desirable to design the clock speed at 25 MHz.

Next, the circuit configuration of the LCD control block is as shown in Fig. 20 and Fig.

The function of each signal line in the block diagram of FIG. 20 is as follows.

LCD Color R0-R7 Data: Red color data

LCD Color G0-G7 Data: Green color data

LCD Color B0-B7 Data: Blue color data

LCD Dot Clock: A synchronous clock signal for applying a dot corresponding to the minimum unit point of the LCD screen

LCD H Sync: Synchronization signal indicating the start of horizontal scanning

LCD V Sync: Synchronization signal indicating the start of vertical scanning

LED_A: Anode pole output of LED for LCD backlight

LCD_K: Cathode pole output of LCD backlight LED

In Fig. 21, as a design circuit of the LCD control part used in the controller, the relationship with the signal lines specified in Fig. 20 is as follows

LCD Color R0-R7 Data: LCD_R0 ~ LCD_R7

LCD Color G0-G7 Data: LCD_G0 ~ LCD_G7

LCD Color B0 to B7 Data: LCD_B0 to LCD_B7

LCD Dot Clock: PVCLK

LCD H Sync: PHSYNC

LCD V Sync: PVSYNC

LED_A: LCM_LEDA

LCD_K: LCD_LEDK

22 is a constituent circuit of the light control section, and the relationship with the signal lines specified in the circuit configuration is as follows

LED_A: LCM_LEDA

LCD_K: LCD_LEDK

The output voltage of the controller has a PWM waveform and the LCM_LEDA output waveform in a stable state outputs a PEAK value of about 30V at intervals of 6uSec as shown in FIG.

Finally, the circuit configuration of the NAND flash memory block which is the memory configuration is shown in FIGS. 24 and 25. FIG.

The attributes of the control signals shown in the memory block diagram of FIG. 24 are as follows.

NF_nBusy: Port state indicating whether NAND flash memory is in operation or read / write or erase operation is ready. Ready state when it is 'H', busy when it is 'L' condition

NF_nRE: Control signal to read data from NAND Flash, 'L' signal and read data from NF_D0 ~ NF_D7 port.

NF_nCS: A control signal that allows the NAND flash memory chip to be selected. When the chip is busy, this control signal is ignored.

NF_CLE / SD_CLK: This control signal alternately selects and outputs a control signal when controlling NAND flash or SD memory. When controlling the NAND flash, it is used to send the NAND flash control command to the command register. When controlling SD memory, it is used as a port to output clock signal of SD memory. NF_nWE Command is transmitted when control signal rises to 'H'.

NF_ALE / SD_CMD: Control output used when address value is transferred to NAND flash address register, address is transferred when NF_nWE control signal rises to 'H'.

NF_nWE: Control output used when forwarding command or address with NF_CLE or NF_ALE control signal _

NF_nWP: Write Protect control output to prevent accidental erase / write operation when power of NAND flash memory is switched, and read / write data to NAND flash memory when logic value is 'H' It becomes.

The invention made by the present inventors has been described concretely with reference to the embodiments. However, it is needless to say that the present invention is not limited to the embodiments, and that various changes can be made without departing from the gist of the present invention.

10: Switchboard 11: Configuration equipment
20: Temperature sensor part 21: Sub HTS sensor
22: Common bus 23: Master HTS sensor
30: Monitoring device 40: Remote server

Claims (8)

1. A hybrid temperature sensor based on a master and a sub, comprising:
A hybrid temperature sensor unit including a plurality of HTS temperature sensors for sensing temperature inside the switchgear and acquiring temperature array data; And
And a monitoring device for determining the presence or absence of an abnormality in the power plant by using the temperature array data,
The HTS temperature sensor contacts the switchgear facility to sense the temperature,
The HTS temperature sensor is coupled to a common bus to transmit temperature data over a common bus,
One of the HTS temperature sensors (hereinafter referred to as a master HTS temperature sensor) controls a plurality of HTS temperature sensors (hereinafter referred to as sub HTS temperature sensors) other than the master HTS temperature sensor via a common bus, Collects the data and transmits it to the monitoring apparatus,
Supplying power to the HTS temperature sensor through the common bus,
The HTS temperature sensor is connected to the common bus through a 3-state port and is connected through a pull-up resistor when connected to the common bus. And maintains a high level state when there is no signal transmission. The hybrid temperature sensor based hybrid temperature sensor system according to claim 1,
delete The method according to claim 1,
The master HTS temperature sensor uses the unique 32-bit code of each sub HTS sensor to identify the sub HTS sensors connected on the common bus and to distinguish the IDs so that each sub HTS temperature sensor has its own code, HTS temperature sensors are addressed to a common bus on a line of the sub-HTS temperature sensor.
delete The method according to claim 1,
The HTS temperature sensor is connected to an internal capacitor on the common bus and charges the internal capacity when a high level bus signal is input through the common bus, And the power is supplied by the charged internal capacity when a bus signal is input. The hybrid temperature sensor based hybrid temperature sensor system according to claim 1,
The method according to claim 1,
Wherein the master HTS temperature sensor comprises a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor connected in parallel with a pull-up resistor to the common bus.
The method according to claim 1,
Wherein the HTS temperature sensor is configured to output a DC voltage using a negative temperature coefficient thermistor and a resistor or a measuring circuit that converts a DC voltage or current caused by an offset voltage of the transistor into a temperature A hybrid temperature sensor based master and slave based switchgear deterioration monitoring system.
The method according to claim 1,
The HTS temperature sensor comprises a 2-byte temperature register for storing temperature data and a 1-byte alarm trigger register structure for overheating alarm in an EEPROM memory as a temporary storage location,
The HTS temperature sensor performs a temperature conversion on the sensed value, compares the predefined two complement alarm trigger value stored in the first and second alarm trigger registers with the converted temperature value, If the temperature value is lower than or equal to the value stored in the first alarm trigger register, or if the temperature value is lower than or equal to the value stored in the second alarm trigger register,
Wherein the master HTS temperature sensor executes an alarm search command to check the alarm flags of all the sub HTS temperature sensors on the common bus. ≪ RTI ID = 0.0 > A < / RTI > .

Images