KR101446336B1 - Semiconductor memory device having recess type balancing capacitors - Google Patents

Abstract

The present invention is directed to a semiconductor memory device comprising a recessed type of balancing capacitor. The semiconductor memory device includes a plurality of memory cell blocks, an edge sense amplifier block including edge sense amplifiers to which bit lines of half of the outermost memory cell blocks among the memory cell blocks are connected to a first input, And a balancing capacitor portion including balancing capacitors coupled to the balancing bit lines to provide balancing bit lines coupled to a second input. The balancing capacitors are arranged in a direction orthogonal to the balancing bit lines, arranged over a region where a predetermined number of balancing bit lines are arranged, a balancing capacitor and a balancing bit line are connected through a contact, and formed as a recess type capacitance structure do.

Edge dummy cell, balancing capacitor, recess type, edge sense amplifier

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device having recessed type balancing capacitors,

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a recessed type balancing capacitor.

Cost reduction is becoming more important in DRAMs. Therefore, reduction of chip size is most effective. Until now, miniaturization process technology has been promoted to reduce the size of the memory cell, but from now on it is necessary to reduce the chip size by changing the memory arrangement.

In a DRAM, a method of arranging a memory cell composed of a 1-transistor and a 1-capacitor and a sense amplifier for sensing and amplifying memory cell data is an important design item that determines the DRAM chip size. A method of arranging a memory cell array including a sense amplifier is broadly classified into an open bit line method and a folded bit line method.

In the open bit line method, memory cells are arranged at all intersections where an arbitrary word line and a bit line intersect, which is a suitable arrangement method for obtaining a chip having the largest density and a small area of a memory cell. A sense amplifier typically compares a stored reference in a memory cell with a known reference. In a sense amplifier in the open bit line scheme, a complementary bit line is connected to a bit line connected to a different memory cell array. In the layout design of the sense amplifier, one sense amplifier block is arranged at a 2-bit line pitch. In the folded bit line method, since one sense amplifier is disposed in a 4-bit line pitch, the layout design of the sense amplifier is easier than the open bit line method. However, in the folded bit line method, the area of the memory cell is twice as large as that of the open bit line method, so that the chip size is increased.

On the other hand, in the open bit line type memory cell array, half of the bit lines of the outermost memory cell array are connected to the sense amplifiers one by one but the remaining half are left as a dummy. That is, dummy cells of a half block size are arranged in the outermost memory cell array. Thus, there is a disadvantage in that the memory cells are arranged more than the intended memory capacity of the entire memory cell array, thereby unnecessarily oversizing the chip size.

It is an object of the present invention to provide a semiconductor memory device which replaces edge dummy cells with recessed type balancing capacitors.

According to an aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory cell blocks, a sense amplifier including sense amplifiers connected between bit lines of adjacent memory cell blocks disposed between the memory cell blocks, Blocks, half of the outermost memory cell blocks among the memory cell blocks, are connected to the first input, and the balance sense bit lines connected to the second inputs of the sense amplifiers And a balancing capacitor portion including balancing capacitors coupled to the balancing bit lines. The balancing capacitors are arranged in a direction orthogonal to the balancing bit lines, arranged over a region where a predetermined number of balancing bit lines are arranged, a balancing capacitor and a balancing bit line are connected through a contact, and formed as a recess type capacitance structure do.

According to embodiments of the present invention, the balancing capacitors are formed in an N-well region formed in the semiconductor substrate and serving as a lower conductive film of the balancing capacitor, a recessed type formed in the N-well from the surface of the semiconductor substrate An upper conductive film in contact with the balancing bit line through the contact embedded in the conductive film, and a dielectric film formed in the recessed type between the N-well region and the upper conductive film.

According to embodiments of the present invention, the semiconductor memory device may be configured such that the N-well region can be biased to the ground voltage through the N-plug region and the semiconductor substrate outside the periphery of the N- Voltage. ≪ / RTI >

According to embodiments of the present invention, memory cell blocks may have an open bit line structure in which memory cells are disposed at all intersections where word lines and bit lines intersect.

According to embodiments of the present invention, the balancing capacitors may be set to have the same capacitance as the capacitance of the bit lines of the outermost memory cell block.

According to embodiments of the present invention, the edge sense amplifiers may further include a switching unit for connecting a balancing bit line and a second input of the edge sense amplifier in response to a sensing enable signal for activating the edge sense amplifiers.

According to embodiments of the present invention, the edge sense amplifiers are configured the same as the sense amplifiers, and the transistors constituting the edge sense amplifier can be set larger than the sizes of the transistors constituting the sense amplifiers.

According to embodiments of the present invention, each of the sense amplifier and the edge sense amplifier includes an equalizer section for precharging the bit line and the balancing bit line to the bit line precharge voltage in response to the equalizing signal, a sense amplifier, A sensing unit for sensing and amplifying memory cell data of a memory cell block connected to a word line selected in response to a sensing enable signal for activating an amplifier to charge-balance the bit line and the balancing bit line, And a data line selector for transferring the data of the bit line and the balancing bit line to the data line pair.

According to embodiments of the present invention, the sensing unit includes a first sensing unit connected to a first power supply line driven by a power supply voltage and configured by PMOS transistors cross-connected to a bit line and a balancing bit line, And a second sensing unit connected to a second power line to be driven and composed of NMOS transistors cross-connected to the bit line and the balancing bit line.

According to the semiconductor memory device of the present invention, a conventional edge dummy cell is replaced with a balancing capacitor, and a chip size is reduced by using a recessed type balancing capacitor having a large capacitance per unit area.

In order to fully understand the present invention and the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings, which are provided for explaining exemplary embodiments of the present invention, and the contents of the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a view illustrating a semiconductor memory device according to an embodiment of the present invention. 1, a memory cell array 10 of a typical open bit line structure is compared with a memory cell array 20 of an open bit line structure of the present invention. The memory cell array 10 having a typical open bit line structure includes a plurality of memory cell blocks 11, 12, 13 and 14 arranged therein and sense amplifiers 11, 12, 13 and 14, (15, 16, 17, 18) are arranged. In the memory cell blocks 11, 12, 13, and 14, DRAM cells composed of a 1-transistor and a 1-capacitor are arranged at an intersection where word lines and bit lines cross each other. Each of the memory cell blocks 11 and 14 disposed at the outermost edge of the memory cell array 10 has half of the bit lines connected to sense amplifiers 15 and 18, ). In order to eliminate the chip size overhead due to the memory cells connected to the dummy bit lines in the outermost memory cell blocks 11 and 14, the memory cell array 20 of the open bit line structure of the present invention is provided.

The memory cell array 20 of the open bit line structure of the present invention has a plurality of memory cell blocks 21, 21, 22, and 23 having DRAM cells each consisting of a 1-transistor and a 1-capacitor at an intersection at which word lines and bit lines cross, 22 and 23 are arranged and sense amplifiers 24, 25 and 26 are arranged between the memory cell blocks 21, 22 and 23, respectively. Each of the memory cell blocks 21 and 23 disposed at the outermost portion of the memory cell array 20 is connected to the edge sense amplifier blocks 27 and 28. The edge sense amplifier blocks 27 and 28 include edge sense amplifiers 30 and 31 and balancing capacitor portions 32 and 33.

The edge sense amplifiers 30 and 31 are connected to half the bit lines (hereinafter referred to as "bit lines") in the memory cell blocks 21 and 23 and sense memory cell data connected to the bit lines Is connected to balancing capacitors connected to a balancing bit line (hereinafter referred to as "complementary bit line") for holding a reference voltage level. If the capacitance of the bit line and the capacitance of the complementary bit line are different from each other, the edge sense amplifiers 30 and 31 cause the bit line precharge instruction noise to be interfered with the sensing operation. Accordingly, a balancing capacitor is connected to the complementary bit line to equalize the capacitance of the complementary bit line to the capacitance of the bit line equally.

Fig. 2 is a view for explaining the edge sense amplifier 30 of Fig. 2, the edge sense amplifier 30 includes an equalizer unit 34, sensing units 35a and 35b, and a data line selection unit 36. As shown in FIG. The edge sense amplifier 30 is the same as the normal sense amplifier and the edge sense amplifier 31 in the sense amplifier blocks 24, 25, The equalizer 34 precharges the bit line BL and the complementary bit line BLB to the bit line precharge voltage VBL in response to the equalizing signal PEQ. The sensing units 35a and 35b sense and amplify the memory cell MC data of the memory cell block 21 connected to the selected word line WL in response to the sensing enable signals SAE and / SAE. The first sensing unit 35a is composed of PMOS transistors connected to the first power line LA driven by the power supply voltage VDD and cross-connected to the bit line BL and the complementary bit line BLB . The second sensing unit 35b is composed of NMOS transistors connected to the second power supply line LAB driven by the ground voltage VSS and cross-connected to the bit line BL and the complementary bit line BLB . The data line selection unit 36 transfers the data of the bit line pair BL and BLB to the data line pair DL and DLB in response to the column selection signal CSL. The edge sense amplifier 30 is the same as the normal sense amplifier in the sense amp blocks 24, 25, and 26 of Fig. The sizes of the PMOS transistors and the NMOS transistors in the sensing portions 35a and 35b of the edge sense amplifier 30 are made larger than those of the normal sense amplifiers 24 and 25 and 26, .

FIG. 3 is a view for explaining the balancing capacitor unit 32 of FIG. 1 in detail. 3, the balancing capacitor unit 32 includes balancing capacitors BCap connected between a balancing bit line BBL and a ground voltage VSS, and a balancing capacitor 32 connected between the balancing bit line BBL in response to a sensing enable signal SAE. (BBL) of the edge sense amplifier 30 and a complementary bit line (BLB) of the edge sense amplifier 30. The switching unit 60 is composed of the NMOS transistors connected between the balancing bit line BBL and the complementary bit line BLB. Balancing capacitors BCap are arranged as shown in FIG.

Referring to FIG. 4, the balancing bit lines BBL0-BBL3 in the balancing capacitor portion 32 are arranged in parallel with the complementary bit lines BLB0-BLB3 of the edge sense amplifier 30. [ Balancing capacitors 70, 71, 72, and 73 are disposed in a direction orthogonal to the balancing bit lines BBL0 to BBL3. The balancing capacitors 70, 71, 72 and 73 are connected to the balancing bit lines BBL0-BBL3 via the contacts 80, 81, 82 and 83, respectively. In the present embodiment, each of the balancing capacitors 70, 71, 72, and 73 is described as being disposed over four balancing bit lines BBL0 to BBL3. This is accomplished by using four balancing bit lines BBL0-BBL3 to implement the balancing capacitors 70, 71, 72, 73 having the same capacitance as the respective capacitances of the bit lines BL0-BL3 connected to the edge sense amplifier 30. [ ) Is required to be disposed. The balancing capacitors 70, 71, 72, and 73 may be formed of a resistive type capacitance structure to minimize the area. Capacitance structures of the recess type are increased in capacitance per unit area according to the type thereof. In this case, the balancing capacitors 70, 71, and 71 are provided across three balancing bit lines (BBL0 to BBL2) 72 may be formed. As a result, the area occupied by the balancing capacitor 73 is reduced, the area of the balancing capacitor portion 32 is reduced, and the area of the memory cell array 20 (FIG. 1) is also reduced.

5 is an enlarged view of part A of the balancing capacitor unit 32 of FIG. 5, the balancing capacitors 72 and 73 have a structure in which the dielectric film 91 and the first to third upper conductive films 92, 93, and 94 are disposed on the active region 85. The X-X 'cross-sectional view of the region of the contact 82 connecting the balancing capacitor 72 and balancing bit line BBL2 is shown in FIG.

Referring to FIG. 6, an N-well 90 is formed on a semiconductor substrate 100 of a first conductivity type, for example, a P-type. The N-well 90 serves as the lower conductive film of the balancing capacitor 72. A recess type dielectric film 91 is formed in the N-well 90 and a first upper conductive film 92 is formed on the dielectric film 91 in a recessed manner. Second and third upper conductive films 93 and 94 are sequentially stacked on the first upper conductive film 92. The balancing bit line BBL2 is connected to the second upper conductive film 93 through the contact 82 embedded in the conductive film. The N-well 90 is biased to the ground voltage VSS through the N-plug 95 and the P-type semiconductor substrate 100 outside the N-well 90 is also biased via the P- And is biased at the ground voltage VSS.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1 is a view illustrating a semiconductor memory device according to an embodiment of the present invention.

2 is a view for explaining the edge sense amplifier of Fig.

3 is a view for explaining the balancing capacitor unit of FIG.

Figure 4 is a diagram illustrating the placement of balancing capacitors in the balancing capacitor portion of Figure 3;

5 is an enlarged view of a portion A of the balancing capacitor portion of FIG.

6 is a cross-sectional view taken along the line X-X 'of the balancing capacitor of FIG.

Claims (10)

A plurality of memory cell blocks; Sense amplifier blocks disposed between the memory cell blocks, the sense amplifier blocks including sense amplifiers to which bit lines of adjacent memory cell blocks are connected; An edge sense amplifier block including edge sense amplifiers in which bit lines of half the outermost memory cell blocks of the memory cell blocks are connected to a first input; And And a balancing capacitor unit providing balancing bit lines connected to a second input of the edge sense amplifiers and including balancing capacitors connected to the balancing bit lines, Wherein the balancing capacitors are arranged in a direction orthogonal to the balancing bit lines and disposed over a region where predetermined balancing bit lines are disposed, the balancing capacitor is connected to the balancing bit line via a contact, Wherein the memory cell is formed of a capacitance structure. 2. The method of claim 1, wherein the balancing capacitors An N-well region formed in the semiconductor substrate and serving as a lower conductive film of the balancing capacitor; An upper conductive layer formed in a recess type from the surface of the semiconductor substrate into the N-well and contacting the balancing bit line through the contact embedded in the conductive film; And And a dielectric film formed in a recessed manner between the N-well region and the upper conductive film. The semiconductor memory device according to claim 2, wherein the semiconductor memory device And the N-well region is biased to a ground voltage through the N-plug region. The semiconductor memory device according to claim 3, wherein the semiconductor memory device And the semiconductor substrate outside the periphery of the N-well region is biased to the ground voltage through the P-plug region. The memory cell block of claim 1, And an open bit line structure in which memory cells are arranged at all intersections where word lines and bit lines intersect. 2. The method of claim 1, wherein the balancing capacitors And a capacitance equal to a capacitance of bit lines of the outermost memory cell block. 2. The apparatus of claim 1, wherein the edge sense amplifiers Further comprising a switching unit for connecting the balancing bit line and the second input of the edge sense amplifier in response to a sensing enable signal for activating the edge sense amplifiers. 2. The apparatus of claim 1, wherein the edge sense amplifiers And the transistors constituting the edge sense amplifier are larger than the sizes of the transistors constituting the sense amplifiers. 9. The apparatus of claim 8, wherein each of the sense amplifier and the edge sense amplifier An equalizer for precharging the bit line and the balancing bit line to a bit line pre-charge voltage in response to an equalizing signal; Sensing and amplifying memory cell data of the memory cell block connected to a selected word line in response to a sensing enable signal for activating the sense amplifier and the edge sense amplifier to charge the bit line and the balancing bit line Sensing unit; And And a data line selector for transferring data of the bit line and the balancing bit line to a pair of data lines in response to a column select signal. 10. The apparatus of claim 9, wherein the sensing unit A first sensing unit connected to a first power supply line driven by a power supply voltage and configured by the PMOS transistors cross-connected to the bit line and the balancing bit line; And And a second sensing unit coupled to a second power supply line driven by a ground voltage and comprising NMOS transistors cross-connected to the bit line and the balancing bit line.

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