KR101421153B1 - Memristor-based Memory Circuit for Reading-out the Resistance of Memristor without Resistance Drift Using Capacitors - Google Patents

Memristor-based Memory Circuit for Reading-out the Resistance of Memristor without Resistance Drift Using Capacitors Download PDF

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KR101421153B1
KR101421153B1 KR1020120038970A KR20120038970A KR101421153B1 KR 101421153 B1 KR101421153 B1 KR 101421153B1 KR 1020120038970 A KR1020120038970 A KR 1020120038970A KR 20120038970 A KR20120038970 A KR 20120038970A KR 101421153 B1 KR101421153 B1 KR 101421153B1
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memristor
current
switch
memory
capacitor
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KR20130116535A (en
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김형석
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전북대학교산학협력단
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

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Abstract

A memristor-based memory circuit is provided that uses a capacitor to read the value of the mem- berress resistor without changing the mem- orress resistor value. The MEMS memory circuit for reading the contents of the MEMSistor without changing the resistance according to the present embodiment includes: a MEMSistor; A capacitor in series with the memristor; A second switch connected in series with the memristor; A third switch connected in parallel with the capacitor and providing a path through which current can be discharged to ground through the second switch and the memristor when a strong input current pulse for storing the resistance value is applied to the memristor; A differential amplifier that measures the voltage across the memristor represented by the current source current when reading the resistance value from the memristor; A strong current used to store information in the memristor or a current source that supplies a weak current to read the contents of the memristor; And a first switch for providing a path through which the current for reading the resistance value from the memristor is charged into the capacitor, then flows through the memristor in the opposite direction to that of the capacitor, and is discharged to ground via the second switch. As a result, the sum of the amount of the total charges passing through the memristor in the forward direction and the amount of charges passing in the reverse direction due to the capacitor discharge are equal to each other, resulting in a change in the resistance value of the memristor.

Description

[0001] The present invention relates to a memristor-based memory circuit for reading a memristor resistance value without changing a resistance value of a memristor using a capacitor,

The present invention relates to a memory circuit, and more particularly, to a memory circuit based on a memristor and a method of operating the same.

Since the end of Moore's Law has been anticipated for over a decade, many new technologies have been proposed in the memory industry. One such method is the MLC (Multi-Level Cell) technology, which stores multiple bits in a memory device in the form of multi-level information.

Currently commercially available MLC NAND memory is evolving into a technology that stores four states (two bits per memory) per memory element. Most of these MLC memory methods are PRAM (Phase Change RAM) technologies using transistors except resistance-based RRAMs.

Recently, a memory device called memristor has been successfully developed, which uses a pinched hysteresis loop phenomenon in a thin film made of titanium dioxide between platinum electrodes.

When a voltage or a current value is applied to a specific material, it has been found that the resistance value changes nonlinearly. Thus, it has been used as a name such as ReRAM or RRAM. However, the cause of the change in the resistance value has not been clarified. This is explained by the principle of the memristor that the resistance of a material is changed by a magnetic field or an electric field (simply flux) that appears when a current or voltage is applied.

The characteristics of memristors are prominent in ultra-small nano-devices made of flux-influenced materials. Memister-based memory has many advantages over conventional transistor-based memory. One thing is that it is very small, since the size of the initial stage of development is less than one-tenth of the RAM, and the magnitude of the benefits will become even more evident as the memristor fabrication technology develops.

A memristor is a new device that can store information in the form of a resistance value, but it can produce very small memories, but when the stored information is read due to the physical characteristics of the memristor, There is a problem that a change in the value of the memristor resistance occurs unintentionally.

In order to solve this problem, a method is used in which a pulse signal for reading a memory is input in the form of a double pulse so as to offset the changes in the resistance value changed by the forward pulse and the reverse pulse of the doublerette, There is a problem that the change of the resistance value can not be avoided when the circuit is not simple and the pulse areas in the forward direction and the reverse direction are different.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a method and apparatus for preventing a change in content of a memristor memory by a current applied when reading a resistance value stored in a memristor in a memristor- A memory-based memory circuit that reads the memristor resistance value without changing the value of the memristor resistance by using a charge-repelling capacitor is provided.

According to an aspect of the present invention, there is provided a memory circuit comprising: a memristor; A capacitor in series with the memristor; A second switch connected in series with the memristor; A third switch connected in parallel with the capacitor and providing a path through which current can be discharged to ground through the second switch and the memristor when a strong input current pulse for storing the resistance value is applied to the memristor; A differential amplifier that measures the voltage across the memristor represented by the current source current when reading the resistance value from the memristor; A strong current used to store information in the memristor or a current source that supplies a weak current to read the contents of the memristor; And a first switch for providing a path through which the current for reading the resistance value from the memristor is charged to the capacitor, then flows through the memristor in a direction opposite to that of the capacitor, and is discharged to the ground via the second switch, Read the contents of the memristor without change.

When the first switch is opened, the second switch is closed, the third switch is opened, a read current pulse having a narrow pulse width and a small magnitude is applied, and the voltage appearing across the memristor during the application of the read current pulse is varied And the current stored in the capacitor is stored in the capacitor by closing the first switch at the end of the read current pulse, The resistance value is reversed by a resistance value changed during application of the read current pulse so that the resistance value is restored to the original state. You can read the contents.

Further, after the first switch is opened and the second switch and the third switch are simultaneously closed, a current having a large pulse width and a large magnitude is applied to the memristor, and this current flows through the third switch to the ground The information can be stored by varying the resistance value by the amount of current flowing through the memristor.

In addition, a plurality of memories are included, one memory cell is composed of one second switch and one memristor, and each memory cell is grouped into one memory group, and one memory group A current source, one discharging second switch, one current storing capacitor and one grounding first switch, so that the individual memory cells in the memory group can be selected by the second switch.

In addition, a plurality of memory groups are arranged in parallel in parallel, and a first switch for discharging, a capacitor for charging only, and a third switch for ground are provided individually for each memory group, Dimensional parallel memory read and write structure that enables a plurality of memories to be simultaneously read and written, one memory for each memory group, by selecting a plurality of groups at the same time.

In addition, a two-dimensional sequential memory in which a charge-only capacitor, a third switch for grounding, and a first switch for discharging are shared by using only one memory circuit in each memory circuit, Read and write structures.

In addition, memristors can include memory devices that store information using resistive characteristics, ReRAM, RRAM, and memory devices using resistance change characteristics such as phase change memories.

To increase the linearity of the memristor operation, a complementary connection circuit can be used in which two memristors are connected in opposite polarities instead of a single memristor.

As described above, according to the present invention, the current passing through the memristor is stored in the capacitor by the read current pulse applied to read the resistance value of the memristor, and from the moment the read pulse is terminated to the capacitor While all the stored charges are discharged, the current flows in the opposite direction, and by reversing the resistance of the memristor, it is possible to return to the original resistance value. As a result, the sum of the total amount of charges passing through the memristor in the forward direction and the amount of charges passing in the reverse direction due to the capacitor discharge are equal to each other, resulting in a change in the resistance value of the memristor.

FIG. 1 is a graph showing a nonlinear curve between a flux and a charge to explain a nonlinear characteristic of a memristor,
Fig. 2 is a circuit diagram of a resistors of the present invention, which is provided in a conceptual description of reading a resistance value of a memristor without changing a resistance value of a memristor using a capacitor,
3 shows a memory circuit for reading a MEMSROR resistance value without changing a MEMSRITOR resistance value by using a capacitor,
FIG. 4 is a diagram showing a memory circuit that reads a MEMS resistance value without changing a MEMS resistance value by using a capacitor in a plurality of MEMS memories composed of one-dimensional columns;
FIG. 5 is a view showing a memory circuit that reads a MEMS resistance value without changing a MEMS resistance value by using a capacitor in a plurality of MEMS memories constituted by two-dimensional columns;
Figure 6 shows a complementary memristor circuit combining two memristors in opposite directions,
7 is a graph showing changes in voltage (a), change in current (b), and change in the resistance of the memristor when a singlet read pulse is applied to the memory circuit according to the present embodiment,
FIG. 8 is a graph showing a relationship between (a) voltage change, (b) current change, (c) memristor resistance value change, and Fig.
Fig. 9 is a table showing changes in resistance value when using the singlet and doublet pulse for the case of using the resistance change prevention circuit according to the present embodiment and for the case of not using the resistance change prevention circuit according to the present embodiment.

Hereinafter, the present invention will be described in detail with reference to the drawings.

One. Memristor

The charge q is defined as the temporal integration of the current i, and is expressed as Equation 1 below.

Figure 112012029799058-pat00001

Equivalently, the current i is the time derivative of the charge q and is expressed as: " (2) "

Figure 112012029799058-pat00002

Similarly, the flux,

Figure 112012029799058-pat00003
Is defined as the time integral of the voltage v and is expressed as Equation 3 below.

Figure 112012029799058-pat00004

Equivalently, the voltage v is a temporal derivative of the charge q, and is expressed as Equation 4 below.

Figure 112012029799058-pat00005

Here, if the equation (4) is divided by the equation (2), the membrane resistance R defined by the following equation (5) can be obtained.

Figure 112012029799058-pat00006

According to equation (5), the memristor resistance R is

Figure 112012029799058-pat00007
It can be defined by the local slope at the operating point of the characteristic curve. if,
Figure 112012029799058-pat00008
If the characteristic curve is nonlinear, it means that the resistance value of the MEMSR can also be changed when the operating point moves.

E.g,

Figure 112012029799058-pat00009
If the characteristic curve is as shown in Fig. 1 (a), the memristor resistance R is calculated as shown in Fig. 1 (b)
Figure 112012029799058-pat00010
It can be displayed on the coordinate axis. Here,
Figure 112012029799058-pat00011
Function
Figure 112012029799058-pat00012
Inverse function.

In Fig. 1 (b)

Figure 112012029799058-pat00013
It is possible to change the resistance of the memristor as shown in Equation (6) below.

Figure 112012029799058-pat00014

Meanwhile,

Figure 112012029799058-pat00015
Is an integration of time with respect to the voltage, it can be expressed by the following Equation (7).

Figure 112012029799058-pat00016

here,

Figure 112012029799058-pat00017
Is the initial value of the flux.

According to Equations (6) and (7), the value of the memristor resistance is defined as a slope in the flux-charge curve, meaning that a different value of the resistivity of the memories can be obtained at different states of charge or flux.

Therefore, by applying the +/- current or voltage applied to the memristor, the charge or flux value can be changed, which means that the resistance value can also be changed.

When the amount of charge changed to change the memristor resistance value is? Q, the amount of change in the resistance? M at this time can be calculated by the following equation (8).

Figure 112012029799058-pat00018

Where R ON is the minimum resistance value, R OFF is the maximum resistance value, D is the width of the middle of the memristor, μ v is the mobility, and w i (t) is the width of the low resistance region inside the memristor at time t.

As a result, the value of the memristor resistance can be changed according to the applied current. Since the resistance of this memristor is the same resistance as a normal resistor, but it is variable, it will be simply referred to as "membrane" or "M" below.

2. Memristor  Based memory

When memristor is used as memory, pulse is used as input signal. Large and large pulses change the resistance of memristor, so it is used for storing information. Narrow and small pulses are used to read the resistance value of memristor .

In general, a memristor is more frequent than when reading information. If the reading of the memristor is repeated for a long time, the resultant charge accumulates in the memristor, undesirably changing the resistance of the memristor.

Since this corresponds to an error in the information programmed into the memristor, in order to utilize the memristor particularly as a nonvolatile memory, it is necessary to prevent the change of the memristor resistance value when reading the contents of the memristor.

To do this, double-pulse pulses are used in which two identical-sized pulses of opposite polarity are generated. However, if the area of the pulses in the opposite direction of the doublet is not exactly the same, then the problem of changing the resistance of the memristor also occurs.

In order to solve this problem, in the present embodiment, a capacitor is connected in series to the memristor, and the current flowing in the memristor is stored in the capacitor while reading the resistance value of the memristor, and then the charges stored in the capacitor When charging, it flows through the memristor in the reverse direction, and the resistance change of the memristor is returned to the origin.

2, when a current for reading the resistance value of the memristor M 140 is applied to the memristor M 140 connected in series to the capacitor C 150, A voltage proportional to the resistance value of the lister M (140) appears.

However, since the resistance of the memristor M (140) changes according to the amount of charge flowing through the memristor M (140) applied from the outside, the charge passing through the memristor M (140) After the MEMS M 140 resistance read pulse ends, the switch SW1 120 is closed so that the charge stored in the capacitor C 150 is discharged (020).

Meanwhile, the change in the resistance value of the memristor M (140) varies depending on the direction and amount of the charge moving through the memristor M (140). When the capacitor C (150) is charged, All of the charges are stored in the capacitor C 150, and when the capacitor C 150 is discharged, the charged charges are discharged in the opposite direction again. Therefore, the resistance change of the memristor M 140 is zero.

When the current pulse I S is applied to the memristor M 140 in FIG. 1, the same current flows through the memristor M 140 and charges the capacitor C 150. During the time t 1 , Assuming that the total charge applied is Δq, and the resistance value changed by this is ΔM, the resistance change of the memristor M (140) after the elapse of the time t 1 is expressed by the following equation (9).

Figure 112012029799058-pat00019

On the other hand, when the capacitor C 150 is charged and the capacitor C 150 is discharged by closing the switch SW1 120 after the memory readout pulse of the MEMSER M 140 has elapsed, The resistance M of the memristor M (140) increases as shown in Equation (10) below.

Figure 112012029799058-pat00020

As a result, the resistance value of the memristor M (140) becomes as shown in the following equation (12), and the original resistance value is returned to.

Figure 112012029799058-pat00021

3. Memristor  Based memory circuit

3.1 Circuit configuration

3 is a circuit diagram of a memristor-based memory, in accordance with a preferred embodiment of the present invention. The memristor-based memory circuit according to this embodiment is capable of reading the resistance value of the memristor without changing the resistance value of the memristor.

3, the memristor-based memory circuit according to the present embodiment includes current sources I S 110, SW 1 120, SW 2 130, memristor M 140, capacitor C 150, An SW3 160, and a differential amplifier 170. [

The current source Is 110 functions as a strong current used for storing information in the memristor M 140 or a power source for supplying a weak current in order to read the content of the memristor M 140.

The capacitor C 150 is connected in series to one end of the MEMSER M 140 and the SW2 130 is connected in series to the other end. The SW3 160 is connected in parallel to the capacitor C 150. The SW3 160 generates a strong input current pulse for storing the resistance value in the memristor M 140 And functions as a switch for providing a path for allowing a current to flow to the ground via the SW2 130 and the MEMSER M 140 when applied.

The differential amplifier 170 is a means for measuring the voltage across the memristor M 140 indicated by the current source Is 110 and reading the resistance value of the memristor M 140.

The SW1 120 flows through the MEMS M 140 in a direction opposite to that when the capacitor C 150 is charged after the current for reading the resistance value from the memristor M 140 flows through the SW2 130 And serves as a switch for providing a path to ground.

3.2 Memristor  How to Read Resistance

3, the method of reading the resistance value of the memristor M 140 without changing the resistance by the memristor read pulse turns on the SW1 120 and turns off the SW2 130, A read pulse having a small pulse width and a small pulse width is applied to the current source Is 110 while the SW3 160 is turned on and the MEMS transistor M 140 is turned on while the read current pulse is applied, The voltage appearing at both ends may be read through the differential amplifier 170.

When the output value of the differential amplifier (170) and V x, memristor resistance value of M (140) M x is applied to the size of the V x as shown in equation (12) below the current value

Figure 112012029799058-pat00022
. ≪ / RTI >

Figure 112012029799058-pat00023

All the current passed through the memristor M (140) while the read current pulse is applied is stored in the capacitor C (160) connected in series with the memristor M (140), and the SW1 120 is closed (M) 140 in a direction opposite to when the charge stored in the capacitor C (160) is stored in the capacitor C (160), and is changed inversely by the resistance value changed during the application of the read current pulse As a result, the resistance value is returned to the original state.

3.3 Memristor  How to write resistors

The method of storing the resistance value in the memristor M 140 in the circuit diagram of the memristor-based memory shown in FIG. 3 includes the steps of turning off the SW1 120 and turning off the SW2 130 and the SW3 160 simultaneously A write current pulse having a large pulse width and a large magnitude is applied to a current source Is 110 to flow to the memristor M 140 and the write current pulse flows to the ground through the SW3 160, It is sufficient to store information by changing the resistance value by the amount of current flowing in the lister M (140).

3.4 One dimensional Memristor  How to configure the memory circuit

In order to construct a memory circuit including a plurality of memristors, one memory cell 180 is formed of one SW2 and one memristor M as shown in FIG. 4, and the memory cells 180 are grouped It is sufficient to configure the memory group 200 in the line.

The memory cells 180 constituting the memory group 200 share the current source Is 110, the SW1 120, the capacitor C 150, and the SW3 160. In addition, the memory cells 180 constituting the memory group 200 are selected by SW2, and the individual memory cells 180 are connected to the memory read / write and the capacitors C () by the same principle as when there is one memory cell. 150), thereby enabling the reading and writing of the contents of the memories without changing the resistance.

3.5 Two Dimensional Memristor  How to configure the memory circuit

In order to construct a memory circuit including a plurality of memristors in two dimensions, a plurality of memory groups are arranged in parallel in a plurality of rows as shown in FIG. 5, / Discrete capacitor C 150 and the grounding SW3 160 are separately provided.

By using the memory group selection switch SW4 230, at least one memory group can be selected at the same time, so that a plurality of memories can be simultaneously read and written by one memory for each memory group.

4. Other

In order to improve the linearity of the memristor operation in the memory circuit shown in Figs. 3 to 5, a complementary connection circuit in which two memristors are connected in opposite polarities as shown in Fig. 6 can be used instead of a single memristor .

In addition, the memristor includes all memories using resistance characteristics such as MEMRistor, ReRam, RRAM, and Phase Change Memrory, which store information using resistive characteristics.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

5. Computer simulation

MATLAB simulation was performed on the TiO 2 memristor model using the memory circuit presented in the above example. Used parameter R ON = 116Ohm, R OFF = 16KOhm, D = 10nm, μ V = 10 -14 m 2 V -1 S -1, w 0 ( low resistance region thickness at the time of maximum resistance) = 0.01D, w 0 (Low resistance region thickness at the time of minimum resistance) = 0.99D, M = 8KOhm and C = 0.1pF.

The input current pulse was a single-pulse pulse with a size of 30 uA and a width of 5 ns and a double pulse with a size of 30 uA and a width of 10 ns. Since it is difficult to make a doublet pulse having the same pulse area with an ideal bipolarity, simulation was performed assuming that the total area is a different double pulse as long as +/- 3%.

7 is a change value of the resistance of the memristor when a single pulse is used. In this case, the change in the resistance value of the memristor was ΔM = -2.762 × 10 -5 Ohm. After allowing the capacitor to discharge for 7 ns, the change in the resistance of the mem- ory was ΔM = -4.38 × 10 -9 Ohm, which reduced the change in resistance by about 10 -4 . Also, it was found that the resistance value decreased during reading of the memristor resistance value increased during the discharging period of the capacitor to reach the value before reading.

8 shows a change in the resistance value of the memristor when a double pulse is used, and ΔM = -6.842 × 10 -7 Ohm. When using the doublet, and after discharging the charged drop in the capacitor for 2 ns, the change in the resistance was reduced to? M = -7.183x10 -8 Ohm. Also, it was found that the resistance value decreased during reading of the memristor resistance value increased during the discharging period of the capacitor to reach the value before reading.

A detailed comparison between the case where the capacitor is used and the case where the single -ret and double-letter input signals are applied in the case where the capacitor is used according to the present embodiment is shown in the table shown in Fig. It can be seen that the memory circuit according to the present embodiment remarkably reduces the change of the resistance value of the memristor in the case of using the single or double pulse. In addition, when the same discharge time was allowed, it was confirmed that the change of the resistance value was smaller in the case of the single-let than in the case of the double-let.

110: current source I S 120: SW1
130: SW2 140: Memister M
150: Capacitor C 160: SW3
170: differential amplifier 180: memory cell
200: Memory group 220: Row select
230: SW4 240: Column select

Claims (8)

Memristor;
A capacitor in series with the memristor;
A second switch connected in series with the memristor;
A third switch connected in parallel with the capacitor and providing a path through which current can be discharged to ground through the second switch and the memristor when a first input current pulse for storing a resistance value is applied to the memristor;
A differential amplifier that measures the voltage across the memristor represented by the current source current when reading the resistance value from the memristor;
A current source for supplying a first current for storing information to the memristor or a second current for reading the content of the memristor; And
And a first switch for providing a path through which the current for reading the resistance value from the memristor is charged into the capacitor, then flows through the memristor in a direction opposite to that of the capacitor, and is discharged to the ground via the second switch,
Wherein the magnitude of the first current is greater than ten times greater than the magnitude of the second current.
The method according to claim 1,
Opening the first switch, closing the second switch, applying a read current pulse with a narrow pulse width and a small pulse width while the third switch is open, and applying a voltage appearing across the memristor to the differential amplifier Read through,
All current through the memristor during the read current pulse is stored in a capacitor connected in series with the memristor,
The first switch is closed at the end of the read current pulse so that the charge stored in the capacitor is discharged through the memristor in a direction opposite to that when the charge is stored in the capacitor and is reversely changed by the resistance value changed during the application of the read current pulse, And the result is that the resistance value is returned to the original state.
The method according to claim 1,
The first switch is opened and the second switch and the third switch are closed at the same time. Then, a current having a large pulse width and a large magnitude is applied to the memristor, and this current flows through the third switch to the ground, And the information is stored by changing the resistance value by the amount of current flowing in the memristor.
4. The method according to any one of claims 1 to 3,
The memristor memory circuit includes a plurality of memristors and a plurality of second switches,
One of the plurality of second switches and one of the plurality of memristors constitutes one memory cell of the plurality of memory cells,
A plurality of memory cells constitute a single memory group,
The memory group shares one current source, one discharging third switch, one current storing capacitor and one grounding first switch,
Wherein the memory cell constituting the memory group is selected by the second switch.
5. The method of claim 4,
A plurality of memory groups are arranged in parallel in parallel,
It is possible to simultaneously read and write several MEMS memory cells, one MEMS memory cell for each memory group, by connecting a selection switch to select a memory group for each MEMS group so that each memory group can be selected at the same time. A two-dimensional parallel memory MEMS memory circuit with a read and write structure to read the contents of the memories without changing the resistance.
5. The method of claim 4,
When the charge-only capacitor, the third switch for grounding, and the first switch for discharging are shared by using only one each in the entire memory circuit, a two-dimensional sequential MEMORY MEMORY CIRCUIT FOR READING MEMBER CONTENTS WITH RESISTANCE TO CHANGE WITH MEMORY READ AND WRITE STRUCTURE.
4. The method according to any one of claims 1 to 3,
The memristor includes at least one of a memristor, a ReRam, an RRAM, and a PCM (Phase Change Memory: phase change memory) for storing information using the resistive characteristic. Memorystor memory circuit for betting.
4. The method according to any one of claims 1 to 3,
To improve the linearity of memristor operation, a memristor memory circuit is used to read the contents of the memories without changing the resistance using a complementary connection circuit with two memristors connected in opposite polarities instead of a single memristor.
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