KR101414887B1 - Multi-level inverter and method for operating the same - Google Patents

Abstract

The present invention provides a multi-level inverter with high reliability in operation and a method for driving the same. The method for driving the multi-level inverter having a plurality of unit power cells comprises the steps of detecting the current from a cell control unit provided in correspondence to the unit power cells; determining a polarity by a gradient of the detected current; calculating a compensation voltage by the determined polarity; and providing an output voltage on which a dead time is compensated by utilizing the compensation voltage calculated by the cell control unit.

Description

Multi-level inverter and method of driving same

The present invention relates to an inverter, and more particularly, to a multi-level inverter and a driving method thereof.

Recently, multilevel inverters have been attracting attention as a topology for high voltage, high capacity inverter systems. In the electric power industry, it is necessary to develop a high-voltage power equipment to operate and configure an efficient and flexible power system such as a flexible ac transmission system (FACTS), an electric motor drive system, and an industrial facility Has developed a high-capacity and high-capacity inverter that is a power conversion device for variable frequency and direct-current conversion.

There are three types of multilevel inverters: a diode clamp inverter, a series H-bridge inverter, and a flying capacitor inverter. Among them, series H-bridge inverters consist of unit power cells with independent DC-Link by connecting low-voltage H-bridge in series. In addition, the series H-bridge inverters have the same total voltage and sum of voltages of each unit series cell, and the output voltage can be varied according to the number of cells. However, the biggest disadvantage of H-bridge inverters is that they must supply independent DC-Link power. There is also a control method in which the master controller takes charge of the overall control in the controller configuration, and the entire voltage is generated by the voltage generation of each cell controller by introducing the distributed control concept.

A controller for controlling a system having a multi-level inverter is mainly composed of a master unit, which is a main controller, and a unit power cell control unit, respectively. The main controller is responsible for the main acceleration / deceleration control such as instantaneous power failure, restart, speed search, emergency stop, auto energy save, self diagnosis, S / L, auto tuning, frequency limit, On the other hand, in the cell control unit, overcurrent, undervoltage, overcurrent, arm short circuit, ground fault, fuse open, heat sink overheat, overcurrent, overcurrent, H / W error, Cell output phase loss, Input phase loss, etc.

The present invention provides a multi-level inverter and a driving method thereof in a highly reliable operation manner.

According to another aspect of the present invention, there is provided a method of driving a multi-level inverter including a plurality of unit power cells, the method comprising: detecting a current in a cell controller provided corresponding to the unit power cell; Determining a polarity by a slope of the detected current; Calculating a compensation voltage by the determined polarity; And providing a dead time compensated output voltage using the compensation voltage calculated by the cell controller.

When the determined polarity is negative, the compensation voltage is calculated by multiplying the command voltage provided by the main controller by the rate of change per unit time, and when the determined polarity is negative, And a negative value of a value obtained by multiplying the command voltage provided by the controller by the change rate per unit time is used as the compensation voltage.

In addition, the current detection unit is provided with current detectors corresponding to the unit power cells, and is detected for each unit power cell.

In addition, the present invention provides a power management system comprising: a unit controller provided corresponding to a plurality of unit power cells arranged correspondingly to a predetermined output; And a main controller for providing a command voltage to the unit controller, wherein the unit controller comprises: a current detector for detecting a current of a corresponding unit power cell; And a control voltage supply unit for providing a dead time compensated output voltage to a corresponding unit power cell using a change amount of the current detected by the current detection unit and a command voltage from the main controller.

The control voltage supply unit may include a voltage command value calculation unit for calculating a voltage required for the control using the command voltage provided by the main controller; A dead time compensation unit for providing the dead time compensated output voltage by using a change amount of a current to a voltage output from the voltage command value calculation unit; And a gate signal generator for converting the dead time compensated output voltage into a form capable of receiving the unit power cell.

By using the driving method of the multi-level inverter proposed in the present invention, even if a hardware defect occurs in the system configuration, the set performance can be outputted in the same manner, so that the reliability of the system can be improved. In addition, the maintenance cost of the system can be reduced because no additional setting change is required. By detecting the current for each unit power cell, the current can be detected more safely against the voltage, and a more accurate value can be detected.

1 is a block diagram of a multi-level inverter system for explaining the present invention.
FIG. 2 is a block diagram of a board implementing the multilevel inverter system of FIG. 1;
FIG. 3 is a circuit diagram of a unit power cell of the multilevel inverter of FIG. 1, and is a block diagram showing an inverter configuration in which unit power cells are connected in series. FIG.
4 is a block diagram illustrating a method of generating a total system output voltage command value in a master master controller and then sending it to a controller in each phase;
5 is a block diagram of a multi-level inverter using a control method according to an embodiment of the present invention.
FIG. 6 is a block diagram illustrating a dead time compensator for dead time compensation of the unit power cell controller of FIG. 5;
7 is a waveform diagram showing the operation of the dead-time compensator of Fig.
8 is a flowchart showing the operation of the dead time compensator of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

1 is a block diagram of a multi-level inverter system for explaining the present invention. 2 is a block diagram of a board implementing the multilevel inverter system of FIG.

1, the H-bridge multilevel inverter includes a phase-shift transformer 10, a unit power cell 20, and a master controller 30 for exchanging information with a unit power cell. do. The phase shift provides a voltage to the DC-Link unit (smoothing unit) provided inside the unit power cell 20 separated and isolated.

In the following, each unit power cell (for example, U1 / U2 / U3 / U4 / U5 / U6) is configured to output a signal having one phase, ) To provide one phase voltage signal. A cell controller (not shown) included in each unit power cell exchanges data with the master controller 30 through an optical cable.

FIG. 2 shows a system configuration implementing a multi-level inverter. The controller of the system is mainly composed of a master controller, which is a main controller, and a unit power cell controller, respectively. The master controller and the unit power cell controller exchange signals through optical communication.

Master controller 30 is responsible for main acceleration / deceleration control such as instantaneous power failure, restart, speed search, emergency stop, auto energy save, self diagnosis, S / L, auto tuning, frequency limit, do. The master controller 30 sends an output voltage command, a synchronous signal, an electric motor overheat, and the like to the optical communication in the form of an overcurrent, an overvoltage, an overcurrent, an arm short, Ground fault, Fuse open, Heat sink overheat, H / W fault, Cell output phase loss, Input phase loss.

FIG. 3 is a circuit diagram of a unit power cell of the multilevel inverter of FIG. 1, showing an inverter configuration in which unit power cells are connected in series.

Referring to FIGS. 1 to 3, the master controller receives each unit power cell voltage and provides voltage reference information to the unit power cell. Each unit power cell receives the DC-Link voltage, generates an output voltage, and applies it to the motor as a load. The frequency of the voltage output from the unit power cell is variable, and is used to control the torque and speed of the electric motor.

As described above, the controller constituting the inverter system is composed of the main controller and the cell controller. The main controller has built-in control block for the motor variable-speed controller and calculates the required voltage / current value. It also performs system-level monitoring and diagnostics, monitoring, protection, MMI, communications, and other ancillary functions. The cell controller is located in each cell and has a monitoring and protection function for each cell according to the set value of the system controller. The main controller is connected to the high-speed link composed of each cell controller and optical cable, and transmits and receives data using serial communication. The communication between the main controller and the cell controller uses CAN.

FIG. 4 is a block diagram showing a method in which a master master controller generates an overall system output voltage command value and then sends it to each controller. As shown in FIG. 4, the master controller 10 generates an overall system output voltage command value and sends it to each of the cell controllers 21, 22, and 23 via CAN communication. The main controller accepts the motor speed and the inverter output current to perform the motor speed and current control. The voltage reference value of the phase 3, which is the output of the current controller, is synchronized with each phase, and data is transmitted to the cell controller through the CAN communication using the optical cable.

The cell controller generates the PWM signal using the DC-Link voltage of the unit power cell and the voltage reference value of the main controller. AVR (auto voltage regulation), one of widely used methods, determines the output frequency in V / F ratio after receiving the average voltage reference value as the input voltage in the cell by sensing the DC-Link voltage of the cell controller The voltage is applied.

The master controller 10 transfers the output value of each phase to the cell controller for safe acceleration / deceleration of the motor. That is, for the three-phase output, the master controller 10 transmits the output voltage to each unit power cell, and calculates and outputs the output voltages A, B, and C for each phase to each cell controller. The voltage delivered to each unit power cell is calculated for each control cycle in the master controller, and each unit power cell controller outputs each cascade output voltage by the information transmitted at each control cycle.

Here, a problem arises. In order to prevent the top lock of the power device (IGBT) included in each unit power cell, dead time exists in each unit power cell. The output voltage of the bridge inverter is determined by the complementary switching of the two IGBTs at the top and the bottom. If both switches become conductive, the device will be severely damaged, so it will turn on with a slight time difference. Time is called. If the loss of the dead time is not compensated, there occurs a problem that the voltage of each phase is output as much as the dead time. In order to compensate each dead time, the polarity of the current is needed when generating each output voltage. In the inverter according to FIGS. 1 to 4, since the control command is not changed to each cell, normal compensation is difficult to achieve.

The present invention proposes a dead time compensation method for individual unit power cell controllers of a high voltage, dedicated current detection device used in a multi-level inverter. In the multi-level inverter, the same current flows through the unit power cells connected in series by phase, and the voltages output at this time are different from each other. In the unit power cell controller, the output current is detected in each unit power cell by using the polarity of each current, and the dead time is compensated. This is a problem that can not be solved when the master controller described in Figs. 1 to 4 controls the voltage value of each phase in the operation of the multilevel inverter. If the dead time compensation is not successful, the magnitude of the output voltage of the multi-level inverter may become low, which causes the quality of the output waveform of the multi-level inverter to be deteriorated.

5 is a block diagram of a multi-level inverter using a control method according to an embodiment of the present invention.

Referring to FIG. 5, the controller of the multi-level inverter system according to the present embodiment includes a master controller 110 and a cell controller. The master controller 110 incorporates a main controller for motor acceleration / deceleration and calculates the required voltage / current value. The master controller 110 is connected to each cell controller through a high-speed link of an optical cable, and uses the same to safely exchange data. The master controller 100 receives the speed of the motor 510 and the inverter output current to perform motor speed and current control. The voltage reference value of the phase 3, which is the output of the current controller, is synchronized with each phase, and data is transmitted to the cell controller through the CAN communication using the optical cable. A cell controller for controlling each unit power cell 210 generates a PWM signal using a DC-Link voltage of the unit power cell 210 and a voltage reference value of the main controller.

The current sensor 600 is inserted into each unit power cell 210 to detect a current flowing through each unit power cell. The current sensor 600 is able to withstand the low voltage of the unit power cell and detect the noise level of each unit power cell directly to the cell controller. Since the current sensor 600 can obtain the detection value in CT by using the power of the unit power cell 210, a general-purpose low voltage type voltage CT for general use may be used.

5, the current sensor 600 is disposed between the switching element and the output terminal of the unit power cell and senses the current flowing to the output terminal (see the inside 211 of the unit power cell).

The transformer 310 is used to supply a separate power source to each cell 210 and to obtain a very low input terminal THD (Total Harmonic Distortion) by forming a multi-pulse type zigzag transformer on the secondary side taps. The unit power cells (② to ⑤) are independent power cells of a single-phase inverter structure constituting the U phase. The unit power cells (6) to (9) are independent power cells of a single-phase inverter structure constituting the V-phase. The unit power cells (10 to 13) are independent power cells of a single-phase inverter structure constituting the W phase. The unit power cells for providing the U, V, and W phase voltages are connected in series with each other, and their outputs are phase-shifted to obtain a multi-level output voltage for driving the motor.

The electric motor 510 is a three-phase high-voltage electric motor used as a load. The master controller 110 is a main control unit for controlling the entire system, and is connected to each unit power cell (2 to 13) by optical communication because of insulation and noise. The inside of the unit power cell 211 represents a power cell constituting each unit power cell (2 to 13) and has a structure of a single-phase inverter. The inside of the unit power cell 211 is implemented in the form of an H-Bridge composed of IGBTs. By connecting these unit power cells in series, each phase of the cascaded high-voltage inverter can be achieved. Also, the unit controller may return the unit power cell information to the main controller to operate the current controller at the system level.

6 is a block diagram illustrating a dead time compensator for dead time compensation of the unit power cell controller of FIG. FIG. 7 is a flowchart showing the operation of the dead-time compensator of FIG. 6, and FIG. 8 is a waveform diagram of the operation of the dead-time compensator of FIG.

Referring to FIG. 6, the dead time compensator includes a voltage command value calculator 100, a dead time compensator 200, and a gate signal generator 300. The gate signal generator 300 includes a reference pulse generator 310 and a dead time generator 320.

The controller of each unit power cell operates with a great advantage in terms of total output voltage and current by controlling the dead time in each individual cell as shown in FIG. 8 when generating each output voltage. Using the voltage command value for the frequency in the signal received from the master controller, the voltage command value calculation unit generates the voltage value for each unit power cell according to each unit power cell. The dead time compensator 200 determines a current polarity of a voltage value (varef) for each unit power cell output from the voltage command value calculation unit 100 and provides a voltage value (varef ') obtained by adding each compensation value. The gate signal generator 300 generates the gate signals A + and A- using the voltage value varef 'for each unit power cell.

The cell controller in each unit power cell of the multilevel inverter according to the present embodiment reflects the switching dead time compensation value, which is the internal operation of the inverter, in the polarity discrimination of the current from the current detection element (15) as shown in the flowchart of FIG. .

In the multilevel inverter system according to the present embodiment, the master controller for controlling the system transfers only the frequency command information related to acceleration / deceleration to the unit power cells, and the unit power cell controller takes charge of the voltage output of each unit power cell according to the distributed control concept. At this time, the polarity of the current flowing in the unit power cell is determined, and the dead time is compensated for the voltage in each unit power cell. These parts can be seen as better voltage and current characteristics in the whole system.

By using the driving method of the multi-level inverter proposed in the present invention, even if a hardware defect occurs in the system configuration, the set performance can be outputted in the same manner, so that the reliability of the system can be improved. In addition, the maintenance cost of the system can be reduced because no additional setting change is required. By detecting the current for each unit power cell, the current can be detected more safely against the voltage, and a more accurate value can be detected.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims (3)

A method of driving a multi-level inverter having a plurality of unit power cells,
Detecting a current in a cell controller corresponding to the unit power cell;
Determining a polarity by a slope of the detected current;
Calculating a compensation voltage by the determined polarity; And
And providing a dead time compensated output voltage using the compensation voltage calculated by the cell controller
And a driving method of the multi-level inverter.
The method according to claim 1,
The step of calculating the compensation voltage
When the determined polarity is positive, the compensating voltage is obtained by multiplying the command voltage provided by the main controller by the rate of change per unit time,
And when the determined polarity is negative, a negative value of a value obtained by multiplying a command voltage provided by the main controller by a rate of change per time is used as the compensation voltage.
3. The method of claim 2,
Wherein the current detection unit detects currents by detecting unit power cells each having a current detection unit corresponding to the unit power cells.

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