KR101401172B1 - System for Controlling Multi Level Inverter and Method for the same - Google Patents

Abstract

A multi-level inverter control system according to an embodiment of the present invention includes a multi-level inverter in which a plurality of unit cells are connected in series; A cell controller for generating a first signal for controlling the unit cell; And a second controller for converting a first signal transmitted from the cell controller into a first optical signal and transmitting the first optical signal to the unit cell, converting a second signal transmitted from the unit cell to a second optical signal, And an I / O interface unit electrically shielding the cell controller operating at a voltage lower than the unit cell from the unit cell,
According to the present invention, the main controller and the cell controller can be isolated from the high voltage of the unit cell.

Description

[0001] The present invention relates to a multi-level inverter control system, and more particularly,

The present invention relates to an inverter control system, and more particularly, to a control system of a multilevel inverter and a control method thereof.

The far-level inverter is a high-voltage, large-capacity inverter that can connect a plurality of single-phase inverters (hereinafter referred to as "cell inverters") in each phase and obtain a high voltage by using a semiconductor for low-voltage power in each cell inverter .

In particular, recently, a multi-level inverter has been applied to a reactive power compensation system in accordance with a demand for applying a reactive power compensating device for improving power quality for system stabilization and maintaining a constant supply voltage.

A control system for controlling such a multi-level inverter can be roughly divided into a centralized control system and a distributed control system. In the centralized control system, only each cell inverter gating amplifier and some protection circuits are built in, and all control operations are performed in the main controller. Such a centralized control system concentrates control and monitoring of the entire system, so that it is easy to perform batch control and simple processing of data processing and sequence processing. However, since the load of the main controller becomes large and a lot of signal lines between the main controller and the cell are required .

1 is a diagram showing an embodiment of a distributed control system among multi-level inverter control systems according to the related art.

1, in the case of the distributed control system 10 shown in Fig. 1, in addition to the main controller 11 for calculating the voltage command value for controlling the acceleration and the shift of the electric motor, the main controller 11 (12a to 12n, 13a to 13n, 14a to 14n) for performing PWM voltage control and phase control in accordance with a voltage command value calculated by the voltage command value calculated by the voltage command value calculation unit 12a to 12n, 13a to 13n , 14a to 14n generate a gating signal or perform a cell-by-cell protection operation.

The distributed control system 10 uses only communications between the cell controllers 12a to 12n and 13a to 13n and 14a to 14n and the main controller 11 to exchange data such as voltage / The number of signal lines is smaller than that of the centralized control system, the load of the main controller is small, and the protection operation of each cell is easy, thereby improving the reliability of the entire system.

However, in the distributed control system 10 of such a multi-level inverter, the cell inverter having high voltage is electrically connected to the cell controller, so that the structure of the cell controller is complicated to protect the cell controller from high voltage, And there is a problem that the unit price is increased due to the use of high voltage parts.

The present invention has been made to solve the above problems and it is an object of the present invention to provide a multilevel inverter control system capable of electrically isolating a main controller and a cell controller from an inverter of a unit cell which receives a high voltage and driving the main controller and the cell controller at a relatively low voltage And a control method thereof.

It is another object of the present invention to provide a multi-level inverter control system and a control method thereof that can minimize the influence of noise due to switching of an inverter of a unit cell.

According to an aspect of the present invention, there is provided a multi-level inverter control system including: a multi-level inverter having a plurality of unit cells connected in series; A cell controller for generating a first signal for controlling the unit cell; And a second controller for converting a first signal transmitted from the cell controller into a first optical signal and transmitting the first optical signal to the unit cell, converting a second signal transmitted from the unit cell to a second optical signal, And an I / O interface unit for electrically shielding the cell controller operating at a lower voltage than the unit cell from the unit cell.

According to another aspect of the present invention, there is provided a method of controlling a multi-level inverter, the method comprising: transmitting a voltage command value of a unit cell calculated by a main controller to a cell controller to control reactive power; Generating a PWM-type gating signal for driving the inverter using a DC link voltage, which is a voltage across the capacitor connected in parallel to an inverter of the unit cell, and the voltage command value, and outputting a first signal including the gating signal Outputting from the cell controller to the first board of the I / O interface unit; Converting the first signal into a first optical signal and outputting the first optical signal to a second board of the I / O interface unit.

According to the present invention, there is an effect that the main controller and the cell controller can be electrically separated from the high voltage of the unit cell.

In addition, according to the present invention, it is not necessary to protect the main controller and the cell controller from high voltage, the system configuration is easy, and the main controller and the cell controller can be manufactured as low voltage parts, which is economical.

In addition, according to the present invention, since the main controller and the cell controller are electrically isolated from the high voltage, the risk of electric shock of the user due to the high voltage can be reduced.

In addition, according to the present invention, it is possible to minimize interference due to noise due to switching of a high voltage and a large current due to use of an optical signal, thereby improving reliability of data.

Also, according to the present invention, the communication period can be further shortened by connecting the cell controllers grouped into the plurality of groups to the main controller through the communication channel allocated to each group.

Further, according to the present invention, since the transmission / reception data in the cell control period or the main control unit and the transmission / reception data in the cell control period are transmitted and received using the optical cable, the communication distance can be increased and the scale of the control system can be easily extended .

1 is a diagram showing an embodiment of a distributed control system among multi-level inverter control systems according to the related art.
2 is a diagram illustrating the configuration of a multi-level inverter control system according to an embodiment of the present invention.
3 is a block diagram illustrating an embodiment of a main controller in a multi-level inverter control system according to the present invention.
4 is a diagram showing an embodiment of an I / O interface unit in a multi-level inverter control system according to the present invention.
5 is a diagram illustrating a configuration of a multi-level inverter control system according to another embodiment of the present invention.
6 is a flowchart illustrating a method of controlling a multi-level inverter according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a configuration of a multi-level inverter control system according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating an embodiment of a main controller in a multi-level inverter control system according to the present invention.

2 and 3, the multi-level inverter control system 100 according to an embodiment of the present invention includes a main controller 110, a plurality of cell controllers 120a to 120n, 130a to 130n, 140a to 140n A plurality of unit cells 160a to 160n, 170a to 170n and 180a to 180n, a reactor 190, a transformer 200, a switching gear 210, and a sensing board (not shown) 220).

The main controller 110 calculates the voltage command values of the unit cells 160a to 160n, 170a to 170n and 180a to 180n connected to each of the phases at each of the phases and supplies them to the cell controllers 120a to 120n, 130a to 130n, 140a to 140n. A digital signal processing unit 111, an I / O input terminal 113, a communication interface unit 115, and a sensing terminal 117.

A digital signal processor (DSP) 111 may include a plurality of CAN drivers for communicating with a plurality of cell controllers 120a to 120n, 130a to 130n, and 140a to 140n. Hereinafter, for convenience, the digital signal processor 111 includes two CAN drivers.

In one embodiment, the digital signal processor 111 may include a first CAN driver 111a and a second CAN driver 111b. A plurality of cell controllers 120a to 120n connected to the plurality of unit cells 160a to 160n, 170a to 170n, or 180a to 180n included in one phase through the I / O interface unit 150, 130a to 130n, and 140a to 140n may be configured as a first cell group and a second cell group. That is, the cell controllers 120a to 120n, 130a to 130n, and 140a to 140n may include three first cell groups and three second cell groups.

The first cell groups of each phase are connected in series to the first CAN driver 111a of the main controller 110 and the second cell groups of each phase are connected to the second CAN driver 111b of the main controller 111, Respectively.

More specifically, the plurality of cell controllers 120a to 120n, 130a to 130n, and 140a to 140n include four cell controllers including a first cell group 120a cell controller, four cell controllers 130a including a cell controller 130a, And four cell controllers including four cell controllers including a 120n cell controller, four cell controllers including a 130n cell controller, and four cell controllers including a 140n cell controller. Wherein the first cell groups of each phase are connected in series to the first CAN driver 111a of the main controller and the second cell groups of each phase are connected to the second CAN driver of the main controller (111b).

As described above, the first cell group of each phase is connected by one CAN communication channel using the first CAN driver 111a, and the second cell group is connected by one CAN communication 111b using the second CAN driver 111b. Channel, it is possible not only to shorten the communication cycle, but also to improve the data reliability.

The main controller 110 calculates the voltage command value for each phase by performing the reactive power control according to the voltage magnitude of the power system and outputs the calculated voltage command value to the cell controller 120a To 120n, 130a to 130n, and 140a to 140n. At this time, the output current direction command of each phase is a command indicating whether the direction of the output current of each phase is ground or truth phase.

The main controller 110 also receives status information of the unit cells 160a to 160n, 170a to 170n, and 180a to 180n connected to the cell controllers 120a to 120n, 130a to 130n and 140a to 140n of the respective phases And transmits a command for controlling the operation of the cell controllers 120a to 120n, 130a to 130n and 140a to 140n of each phase to the cell controllers 120a to 120n, 130a to 130n and 140a to 140n of each phase according to the state information do.

Specifically, main controller 110 includes an emergency stop command to command an emergency stop for protection of system 100, a reset command to initialize and restart system 100 in response to system 100 failure, An initial charge command for charging the capacitor of the inverter, or a gating signal output command to the cell controllers 120a to 120n, 130a to 130n, 140a to 140n of each phase.

In one embodiment, the emergency stop command, the reset command, the initial charge command, and the gating signal output command may be included together in the first frame including the output voltage command value and the output current direction command of each phase described above have.

The main controller 110 synchronizes the PWM phases of the cell inverters with respect to each phase so as to prevent a circulating current between the cell inverters, and outputs a PWM synchronization command to each of the cell controllers 120a to 120n, 130a to 130n and 140a to 140n send.

In addition, the main controller 110 sends a read or write request of interface (HMI: Human Management Interface) data for monitoring and controlling the inverter to the cell controllers 120a to 120n, 130a to 130n and 140a to 140n of the respective phases, Frame, and receive the response from the cell controllers 120a to 120n, 130a to 130n, 140a to 140n of each phase in a frame form.

The I / O input terminal 113 inputs at least one of the ON / OFF control signal of the switching gear 210, the temperature signal of the transformer 200, and the temperature signal of the reactor 190 to the main controller 110. The main controller 110 uses the on / off control signal of the switching gear 210, the temperature signal of the transformer 200, and the temperature signal of the reactor 190 to control the reactive power of the power system 300.

The communication interface unit 115 provides various communication interfaces between the main controller and the external device. In one embodiment, the communication interface unit 115 includes an SPI (Serial Peripheral Interface) communication interface 115a for outputting an analog signal to the DAC, an SCI (Serial Communication Interface) communication interface 115b, And an Ethernet communication interface 115c that supports Ethernet communication.

At this time, the SPI (Serial Peripheral Interface) communication interface 115a may be connected to a scope for monitoring the main controller 110, and the SCI (Serial Communication Interface) communication interface 115b may be connected to RS- (Human Management Interface) for monitoring and controlling the cell inverter, and the Ethernet communication interface 115c may be connected to a device such as a host computer, an HMI, or the like.

The sensing terminal 117 measures at least one of the system voltage V1 of the power system, the load current I1 of the power system, and the output current I2 of the three-phase multi-level inverter, And senses a signal output from the board 220. 3, the sensing board 220 is shown as separate from the main controller 110. However, in another embodiment, the sensing board 220 may be included in the main controller 110. FIG.

The cell controllers 120a to 120n, 130a to 130n and 140a to 140n receive the voltage command values of the main controller 110 and control the unit cells 160a to 160n, 170a to 170n, 180a to 180n, 1 < / RTI >

For this purpose, the cell controllers 120a to 120n, 130a to 130n and 140a to 140n may include a DSP (Digital Signal Process) supporting a CAN driver (not shown) for connection with the main controller 110.

A plurality of cell controllers 120a to 120n, 130a to 130n, and 140a to 140n included in each of the phases A, B, and C have the same or similar characteristics. Therefore, Will now be described with reference to FIG.

The cell controller 120a receives the voltage command value from the main controller 110 and outputs a first signal for controlling the unit cell 160a to the first board 151. [

In one embodiment, the first signal includes a gating signal for the top inverter of the first leg, a gating signal for the top inverter of the second leg, a gating on-off control signal, And a 4-bit signal including a 4-bit signal. In this case, the top inverter of the first leg is connected to the upper side of the inverters connected in series to one branch of the H-Bridge inverters included in the unit cell, and the top inverter of the second leg is connected to the H- It is the inverter connected above the inverter connected in series to the other branch of the inverter.

The cell controller 120a may receive the DC link voltage of the unit cell 160a from the first board 151 of the I / O interface unit 150. [ At this time, the DC link voltage is a voltage across the capacitor connected to the inverter included in the unit cell 160a.

Specifically, the cell controller 120a calculates an average value of the DC link voltage when a frame including the DC link voltage and status information request of each cell controller 120a from the main controller 110 is received, (110). In addition, the cell controller 120a transmits the status information of the cell controller 120a to the main controller 110a. At this time, the state information of the cell controller 120a includes whether or not the unit cell operates, whether the unit cell is stopped, and whether the unit cell is malfunctioning.

4 is a diagram showing an embodiment of an I / O interface unit in a multi-level inverter control system according to the present invention. Hereinafter, an embodiment of the I / O interface unit 150 will be described with reference to FIGS. 2 and 4. FIG.

The I / O interface unit 150 converts the first signal transmitted from the cell controller 120a into a first optical signal and transmits the first optical signal to the unit cell 160a, Signal to a second optical signal and transmits the signal to the cell controller 120a to electrically shield the unit cell 160a operating at a high voltage and the cell controller 120a operating at a low voltage.

The I / O interface unit 150 includes a first board 151 connected to the cell controller 120a and a second board 153 connected to the unit cell 160a. And the first board 151 and the second board 153 are connected by an optical signal.

The first board 151 is connected to the cell controller 120a and converts the first signal received by the cell controller 120a into a first optical signal.

In one embodiment, the first signal includes a PWM type gating signal for driving an inverter of the unit cell 160a, and the second signal includes a capacitor connected in parallel to an inverter included in the unit cell 160a. And a temperature of the heat sink of the unit cell 160a.

In another embodiment, the first signal is a PWM first gating signal gs1 for the top inverter 161T of the first leg leg1, a top of the second leg leg2 A second gating signal gs2 of the PWM type for the inverter 162T, a gating on / off control signal gon for determining whether the inverter included in the unit cell is driven, and a gating on / off control signal gon for determining whether the DC link voltage and the heat sink temperature And an analog sensing channel selection signal (ass) for selection.

In one embodiment, the first board 151 may include a first gating signal gs1, a second gating signal gs2, a gating on-off control signal gon, The channel selection signal ass may be formed into one frame and converted into a first optical signal.

The first board 151 receives the DC link voltage Vdc or the heat sink temperature H.Temp applied to both ends of the capacitor 163 from the second board 153 as optical signals, .

The second board 153 receives the first optical signal from the first board 151 and outputs the inverter driving signals gd1 to gd4 of the unit cell 160a to the gate driver 230. [

The first inverter drive signal gd1 is a drive signal for driving the top inverter 161T of the first leg leg1 and the second inverter drive signal gd2 is a drive signal for driving the bottom of the first leg leg1, The third inverter drive signal gd3 is a drive signal for driving the top inverter 162T of the second leg leg2 and the fourth inverter drive signal gd4 is a drive signal for driving the inverter 161B, Is a drive signal for driving the bottom inverter 162B of the second leg leg2.

The first inverter drive signal gd1 is calculated using the PWM gating signal gs1 for the top inverter 161T of the first leg leg1 and the second inverter drive signal gd2 is calculated using the PWM gating signal gs1 for the top inverter 161T of the first leg leg1, Inverts the PWM type gating signal gs1 for the top inverter 161T of the first leg leg1.

Similarly, the third inverter drive signal gd3 is calculated using the PWM-type gating signal gs2 for the top inverter 162T of the second leg leg2, and the fourth inverter drive signal gd4 is calculated using the PWM- Inverts the PWM type gating signal gs2 for the top inverter 162T of the second leg leg2.

At this time, the gate driver 230 is connected between the second board 153 and the unit cell 160a to drive the inverter of the unit cell 160a and detect an overcurrent signal from the unit cell 160a .

4, the gate driver 230 may be a separate device separate from the second board 153. However, the gate driver 230 may be connected to the I / O interface 150 or the second board 153 153).

The second board 153 receives the overcurrent from the gate driver 230 and can block the inverter driving signals gd1 to gd4 when an overcurrent is generated.

The second board 153 is connected to the unit cell 160a to convert a second signal transmitted from the unit cell 160a into a second optical signal. The second signal is a DC link voltage (Vdc) and a heat sink temperature (H.Temp) that are applied across the capacitor 163 from the unit cell 160a. The second optical signal is the DC link voltage (Vdc) or the heat sink temperature (H.Temp) selected according to the analog sensing channel selection signal (ass).

The plurality of unit cells 160a to 160n, 170a to 170n and 180a to 180n are connected in series to constitute a three-phase multilevel inverter.

The far-level inverter is a high-voltage, large-capacity inverter that can obtain a high voltage by connecting a plurality of unit cells in series for each phase. The three-phase unit cells 160a to 160n, 170a to 170n and 180a to 180n include A phase unit cells 160a to 160n, B phase unit cells 170a to 170n, and C phase unit cells 180a to 180n. .

The unit cells 160a to 160n, 170a to 170n and 180a to 180n are connected to the H-bridge inverters 161T, 161B, 162T and 162B, the H-bridge inverters 161T, 161B, 162T and 162B And a bypass switch 164 connected to the H-bridge inverters 161T, 161B, 162T, and 162B.

The reactor 190 may be connected to one end of the A phase unit cells 160a through 160n, the B phase unit cells 170a through 170n and the C phase unit cells 180a through 180n, Are connected to the transformer 200. [

The transformer 200 is connected to the switching gear 210 and the other end of the switching gear 210 is connected to the power system in parallel.

In one embodiment, the multilevel inverter control system 100 according to the present invention may be configured as a STATCOM (Static Synchronous Compensator) that is connected in parallel to a system to compensate for reactive power of the system.

Thus, by configuring the STATCOM using the multilevel inverter control system 100 according to the present invention, the power system can be stabilized by compensating for the reactive power of the system.

5 is a diagram illustrating a configuration of a multi-level inverter control system according to another embodiment of the present invention.

5, the multi-level inverter control system 100 according to an embodiment of the present invention includes a main controller 110, a plurality of cell controllers 120a to 120n, 130a to 130n, 140a to 140n, I O interface unit 150, a plurality of unit cells 160a to 160n, 170a to 170n and 180a to 180n, a reactor 190, a transformer 200, and a switching gear 210. [ In the embodiment of FIG. 5, one of the first boards exchanges optical signals with a plurality of second boards. In order to avoid duplication, the following description will focus on differences from the multilevel inverter control system 100 described in FIG. 2 .

The I / O interface unit 150 includes a first board 151 connected to the cell controllers 120a through 120n, 130a through 130n and 140a through 140n and a second board 151 connected to the unit cells 160a through 160n, 170a through 170n, 180a through 180n And the first board 151 is connected to the plurality of second boards 153a to 153n through an optical signal.

In one embodiment, the first board 151 may be coupled to the four second boards 153a through 153n with optical signals. In this case, one cell controller can be connected to four unit cells through the I / O interface unit 150. [ That is, the number of cell controllers controlling the same number of unit cells is reduced as compared with the embodiment of FIG. Accordingly, the number of the cell controllers serially connected through the CAN communication of the main controller 110 is reduced, and the control signal output cycle of the unit cell through one CAN communication line is shortened.

6 is a flowchart illustrating a method of controlling a multi-level inverter according to an embodiment of the present invention.

As shown in FIG. 6, first, a voltage command value for unit cell control is calculated in the main controller (S1100). A multi-level inverter control system connected in parallel to the grid improves power efficiency by compensating for reactive power. Therefore, in order to control the reactive power, the main controller calculates the voltage command value of the unit cell for each phase and outputs it to the cell controller.

Next, a PWM-type gating signal for driving the inverter is generated using a DC link voltage, which is a voltage between both ends of a capacitor connected in parallel to an inverter of the unit cell, and the voltage command value, and a first signal To the first board of the I / O interface unit in the cell controller (S1200).

In one embodiment, the first signal is a PWM gating signal gs1 for the top inverter 161T of the first leg leg, a top inverter of the second leg leg2 A 4-bit signal including a gating signal gs2 of a PWM scheme, a gating on-off control signal gon, and an analog sensing channel selection signal ass for the first and second transistors 162T and 162T.

Next, the first board converts the first signal received by the first board into a first optical signal, and outputs the first optical signal to the second board of the I / O interface unit (S1300). The second board is connected to a three-phase multilevel inverter using a high voltage and uses a high voltage. However, since the first board is connected to the second board via an optical signal, it can be driven at a relatively low voltage. Therefore, the main controller connected to the cell controller and the cell controller connected to the first board can be driven at a low voltage.

Accordingly, it is possible to electrically isolate the main controller and the cell controller from the high voltage of the unit cell, and it is not necessary to protect the main controller and the cell controller from the high voltage, It is economical because it can be manufactured as parts for use.

Next, the second board converts the input first optical signal into an electrical signal, and outputs the electrical signal to the unit cell (S1400). That is, the second board receives the first optical signal from the first board and outputs inverter drive signals gd1 to gd4 of the unit cells to the gate driver.

The first inverter drive signal gd1 is a drive signal for driving the top inverter of the first leg leg1 and the second inverter drive signal gd2 is a drive signal for driving the bottom inverter of the first leg leg1 The third inverter driving signal gd3 is a driving signal for driving the top inverter of the second leg leg2 and the fourth inverter driving signal gd4 is a driving signal for driving the second leg leg2, And is a driving signal for driving a bottom inverter.

In one embodiment, the first inverter drive signal gd1 is calculated using the PWM gating signal gs1 for the top inverter of the first leg leg1, and the second inverter drive signal gd2 ) Inverts the gating signal gs1 of the PWM scheme for the top inverter of the first leg leg1.

Likewise, the third inverter drive signal gd3 is calculated using the PWM-type gating signal gs2 for the top inverter of the second leg leg2, and the fourth inverter drive signal gd4 is calculated using the second- The gating signal gs2 of the PWM method for the top inverter of the leg 2 is inverted and calculated.

Next, a second signal including any one of the DC link voltage and the heat sink temperature of the unit cell is converted into a second optical signal and output to the first board (S1500).

In one embodiment, the multi-level inverter control method further includes blocking the gating signal output from the second board when an overvoltage of the unit cell is detected in the gate driver.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100 - Multi-level inverter control system 110 - Main controller
111 - Digital Signal Processing Unit 113 - I / O Input Terminal
115 - Communication interface part 117 - Sensing terminal
120a to 120n, 130a to 130n, 140a to 140n,
150 - I / O interface unit 151 - First board
153 - Second board
160a to 160n, 170a to 170n, 180a to 180n,
190 - Reactor 200 - Transformer
210 - switching gear

Claims (17)

A multilevel inverter having a plurality of unit cells connected in series;
A cell controller for generating a first signal including a gating signal for controlling the unit cell; And
A DC link voltage, which is a voltage between both ends of a capacitor included in an inverter of the unit cell, and a temperature of a heat sink of the unit cell, And an I / O interface unit for converting a second signal including one of the plurality of unit cells into a second optical signal and delivering the second signal to the cell controller to electrically isolate the plurality of unit cells from the cell controller. Control system. The method according to claim 1,
The I / O interface unit includes a first board connected to the cell controller and converting the first signal into the first optical signal, and a second board connected to the unit cell and converting the second signal into the second optical signal. Board control system for a multi-level inverter. delete The method according to claim 1,
Wherein the I / O interface unit includes a first board connected to the cell controller and n second boards connected to the first board,
Wherein the cell controller generates n first signals to be provided to the n second boards and provides the first signals to the I / O interface unit. delete delete delete delete The method according to claim 1,
Wherein the cell controller includes a first cell group and a second cell group,
The first group of cells of each phase are connected in series to a first CAN driver of the main controller and the second group of cells of each phase are serially connected to a second CAN driver of the main controller Wherein the inverter control system is a multi-level inverter control system. The method according to claim 1,
A PWM synchronizing command for synchronizing a PWM phase between the unit cells, an emergency stop command for stopping the multi-level inverter, a voltage command value for controlling the unit cell connected to the multi-level inverter in each phase, And a main controller for transmitting at least one of an initial charge command for charging the capacitor of the multilevel inverter to the cell controller. The method according to claim 1,
A digital signal processor (DSP) supporting a plurality of CAN drivers for communicating with the plurality of cell controllers; And an on-off control signal of a switching gear connected to the power system, a temperature signal of a transformer connected between the switching gear and the multi-level inverter, and a temperature signal of a reactor connected between the transformer and the multilevel inverter / O < / RTI > input terminal of the multi-level inverter control system. delete Transmitting the voltage command value of the unit cell calculated by the main controller to the cell controller to control the reactive power; And
A first signal including a PWM type gating signal for driving an inverter of the unit cell is converted from a first board to a first optical signal and outputted to a second board, and both ends of a capacitor connected in parallel to the inverter of the unit cell Converting a second signal including one of a DC link voltage (DC link voltage) and a heat sink temperature of the unit cell from the second board to a second optical signal and outputting the second signal to the first board and,
Wherein the cell controller generates the PWM gating signal using the voltage command value and the DC link voltage received through the first board. 14. The method of claim 13,
Wherein the first signal comprises:
Further comprising an analog sensing channel selection signal for selecting either a gating on-off control signal indicating whether the unit cell is driven by an inverter, and a temperature of the DC link voltage and a heat sink temperature of the unit cell,
The gating signal of the PWM scheme includes a first gating signal for a top inverter of a first leg and a second gating signal for a top inverter of a second leg, Bridge inverter is one of inverters connected in series to one branch of the H-bridge inverters of the unit cell, and the top inverter of the second leg is connected in series to another branch of the H-Bridge inverter Wherein the inverter is one of inverters. 15. The method of claim 14,
In the step of outputting to the first board,
And the first signal including the first gating signal, the second gating signal, the gating on / off control signal, and the analog sensing channel selection signal is converted into the first optical signal by constituting one frame. Level inverter control method. delete 14. The method of claim 13,
And the second signal is any one selected in accordance with an analog sensing channel selection signal for selecting a signal to be transmitted to the cell controller among the DC link voltage and the heat sink temperature of the unit cell. .

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